Addressmap Information for 'ns_noc_io_pcie_soc

ns_noc_io_pcie_soc_ip.csr /project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.css pcie_noc addressmap pcie_noc pcie_noc ns_noc_io_pcie_soc_ip.csr 160199 R/W Pcie_noc Memory map for rbm_m register pcie_noc.bridge_rbm_m_13_1_p_0 register pcie_noc.bridge_rbm_m_13_1_p_1 register pcie_noc.bridge_rbm_m_13_1_p_2 register pcie_noc.bridge_rbm_m_13_1_p_3 register pcie_noc.bridge_rbm_m_13_1_txe register pcie_noc.bridge_rbm_m_13_1_txem register pcie_noc.bridge_rbm_m_13_1_btus_0 register pcie_noc.bridge_rbm_m_13_1_btus_1 register pcie_noc.bridge_rbm_m_13_1_btrl_0 register pcie_noc.bridge_rbm_m_13_1_btrl_1 register pcie_noc.bridge_rbm_m_13_1_btrl_2 register pcie_noc.bridge_rbm_m_13_1_btrl_3 register pcie_noc.bridge_rbm_m_13_1_btperr register pcie_noc.bridge_rbm_m_13_1_btperrm register pcie_noc.bridge_rbm_m_13_1_rxe register pcie_noc.bridge_rbm_m_13_1_rxem register pcie_noc.bridge_rbm_m_13_1_brs_0 register pcie_noc.bridge_rbm_m_13_1_brs_1 register pcie_noc.bridge_rbm_m_13_1_brus register pcie_noc.bridge_rbm_m_13_1_brperr0 register pcie_noc.bridge_rbm_m_13_1_brperr1 register pcie_noc.bridge_rbm_m_13_1_brperrm0 register pcie_noc.bridge_rbm_m_13_1_brperrm1 register pcie_noc.bridge_rbm_m_13_1_am_tocfg register pcie_noc.bridge_rbm_m_13_1_am_osslv register pcie_noc.bridge_rbm_m_13_1_am_cgc register pcie_noc.bridge_rbm_m_13_1_am_cgo register pcie_noc.bridge_rbm_m_13_1_am_cfg register pcie_noc.bridge_rbm_m_13_1_am_sts register pcie_noc.bridge_rbm_m_13_1_am_bridge_id register pcie_noc.bridge_rbm_m_13_1_am_nocver_id register pcie_noc.bridge_rbm_m_13_1_am_err register pcie_noc.bridge_rbm_m_13_1_am_toslvid register pcie_noc.bridge_rbm_m_13_1_am_era register pcie_noc.bridge_rbm_m_13_1_am_ewa register pcie_noc.bridge_rbm_m_13_1_am_intm register pcie_noc.bridge_rbm_m_13_1_am_caddr register pcie_noc.bridge_rbm_m_13_1_am_caddrmsk register pcie_noc.bridge_rbm_m_13_1_am_ccmd0 register pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0 register pcie_noc.bridge_rbm_m_13_1_am_cntr0 register pcie_noc.bridge_rbm_m_13_1_am_latnum0 register pcie_noc.bridge_rbm_m_13_1_am_ccmd1 register pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk1 register pcie_noc.bridge_rbm_m_13_1_am_cntr1 register pcie_noc.bridge_rbm_m_13_1_am_latnum1 register pcie_noc.bridge_rbm_m_13_1_am_arovrd register pcie_noc.bridge_rbm_m_13_1_am_awovrd register pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_version register pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_id register pcie_noc.bridge_main0_apb_s_6_6_apbslv_slvs_sleep_status register pcie_noc.bridge_main0_apb_s_6_6_as_cgc register pcie_noc.bridge_main0_apb_s_6_6_as_cgo register pcie_noc.bridge_main0_apb_s_6_6_as_sts register pcie_noc.bridge_main0_apb_s_6_6_as_bridge_id register pcie_noc.bridge_main0_apb_s_6_6_as_err register pcie_noc.bridge_main0_apb_s_6_6_as_intm register pcie_noc.bridge_main0_apb_s_6_6_as_ccmd register pcie_noc.bridge_main0_apb_s_6_6_as_ccmdmsk register pcie_noc.bridge_main0_apb_s_6_6_as_cntr register pcie_noc.bridge_main0_apb_s_6_6_as_arovrd register pcie_noc.bridge_main0_apb_s_6_6_as_awovrd register pcie_noc.bridge_main0_apb_s_6_6_p_0 register pcie_noc.bridge_main0_apb_s_6_6_p_1 register pcie_noc.bridge_main0_apb_s_6_6_p_2 register pcie_noc.bridge_main0_apb_s_6_6_p_3 register pcie_noc.bridge_main0_apb_s_6_6_txe register pcie_noc.bridge_main0_apb_s_6_6_txem register pcie_noc.bridge_main0_apb_s_6_6_btus_0 register pcie_noc.bridge_main0_apb_s_6_6_btus_1 register pcie_noc.bridge_main0_apb_s_6_6_btrl_0 register pcie_noc.bridge_main0_apb_s_6_6_btrl_1 register pcie_noc.bridge_main0_apb_s_6_6_btrl_2 register pcie_noc.bridge_main0_apb_s_6_6_btrl_3 register pcie_noc.bridge_main0_apb_s_6_6_btperr register pcie_noc.bridge_main0_apb_s_6_6_btperrm register pcie_noc.bridge_main0_apb_s_6_6_rxe register pcie_noc.bridge_main0_apb_s_6_6_rxem register pcie_noc.bridge_main0_apb_s_6_6_brs_0 register pcie_noc.bridge_main0_apb_s_6_6_brs_1 register pcie_noc.bridge_main0_apb_s_6_6_brus register pcie_noc.bridge_main0_apb_s_6_6_brperr0 register pcie_noc.bridge_main0_apb_s_6_6_brperr1 register pcie_noc.bridge_main0_apb_s_6_6_brperrm0 register pcie_noc.bridge_main0_apb_s_6_6_brperrm1 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_main0_dbg_m_0_9_p_0 register pcie_noc.bridge_main0_dbg_m_0_9_p_1 register pcie_noc.bridge_main0_dbg_m_0_9_p_2 register pcie_noc.bridge_main0_dbg_m_0_9_p_3 register pcie_noc.bridge_main0_dbg_m_0_9_txe register pcie_noc.bridge_main0_dbg_m_0_9_txem register pcie_noc.bridge_main0_dbg_m_0_9_btus_0 register pcie_noc.bridge_main0_dbg_m_0_9_btus_1 register pcie_noc.bridge_main0_dbg_m_0_9_btrl_0 register pcie_noc.bridge_main0_dbg_m_0_9_btrl_1 register pcie_noc.bridge_main0_dbg_m_0_9_btrl_2 register pcie_noc.bridge_main0_dbg_m_0_9_btrl_3 register pcie_noc.bridge_main0_dbg_m_0_9_btperr register pcie_noc.bridge_main0_dbg_m_0_9_btperrm register pcie_noc.bridge_main0_dbg_m_0_9_rxe register pcie_noc.bridge_main0_dbg_m_0_9_rxem register pcie_noc.bridge_main0_dbg_m_0_9_brs_0 register pcie_noc.bridge_main0_dbg_m_0_9_brs_1 register pcie_noc.bridge_main0_dbg_m_0_9_brus register pcie_noc.bridge_main0_dbg_m_0_9_brperr0 register pcie_noc.bridge_main0_dbg_m_0_9_brperr1 register pcie_noc.bridge_main0_dbg_m_0_9_brperrm0 register pcie_noc.bridge_main0_dbg_m_0_9_brperrm1 register pcie_noc.bridge_main0_dbg_m_0_9_am_tocfg register pcie_noc.bridge_main0_dbg_m_0_9_am_osslv register pcie_noc.bridge_main0_dbg_m_0_9_am_cgc register pcie_noc.bridge_main0_dbg_m_0_9_am_cgo register pcie_noc.bridge_main0_dbg_m_0_9_am_cfg register pcie_noc.bridge_main0_dbg_m_0_9_am_sts register pcie_noc.bridge_main0_dbg_m_0_9_am_bridge_id register pcie_noc.bridge_main0_dbg_m_0_9_am_err register pcie_noc.bridge_main0_dbg_m_0_9_am_toslvid register pcie_noc.bridge_main0_dbg_m_0_9_am_era register pcie_noc.bridge_main0_dbg_m_0_9_am_ewa register pcie_noc.bridge_main0_dbg_m_0_9_am_intm register pcie_noc.bridge_main0_dbg_m_0_9_am_caddr register pcie_noc.bridge_main0_dbg_m_0_9_am_caddrmsk register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd0 register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk0 register pcie_noc.bridge_main0_dbg_m_0_9_am_cntr0 register pcie_noc.bridge_main0_dbg_m_0_9_am_latnum0 register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd1 register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk1 register pcie_noc.bridge_main0_dbg_m_0_9_am_cntr1 register pcie_noc.bridge_main0_dbg_m_0_9_am_latnum1 register pcie_noc.bridge_main0_dbg_m_0_9_am_arovrd register pcie_noc.bridge_main0_dbg_m_0_9_am_awovrd register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_main0_esr_m_1_5_p_0 register pcie_noc.bridge_main0_esr_m_1_5_p_1 register pcie_noc.bridge_main0_esr_m_1_5_p_2 register pcie_noc.bridge_main0_esr_m_1_5_p_3 register pcie_noc.bridge_main0_esr_m_1_5_txe register pcie_noc.bridge_main0_esr_m_1_5_txem register pcie_noc.bridge_main0_esr_m_1_5_btus_0 register pcie_noc.bridge_main0_esr_m_1_5_btus_1 register pcie_noc.bridge_main0_esr_m_1_5_btrl_0 register pcie_noc.bridge_main0_esr_m_1_5_btrl_1 register pcie_noc.bridge_main0_esr_m_1_5_btrl_2 register pcie_noc.bridge_main0_esr_m_1_5_btrl_3 register pcie_noc.bridge_main0_esr_m_1_5_btperr register pcie_noc.bridge_main0_esr_m_1_5_btperrm register pcie_noc.bridge_main0_esr_m_1_5_rxe register pcie_noc.bridge_main0_esr_m_1_5_rxem register pcie_noc.bridge_main0_esr_m_1_5_brs_0 register pcie_noc.bridge_main0_esr_m_1_5_brs_1 register pcie_noc.bridge_main0_esr_m_1_5_brus register pcie_noc.bridge_main0_esr_m_1_5_brperr0 register pcie_noc.bridge_main0_esr_m_1_5_brperr1 register pcie_noc.bridge_main0_esr_m_1_5_brperrm0 register pcie_noc.bridge_main0_esr_m_1_5_brperrm1 register pcie_noc.bridge_main0_esr_m_1_5_am_tocfg register pcie_noc.bridge_main0_esr_m_1_5_am_osslv register pcie_noc.bridge_main0_esr_m_1_5_am_cgc register pcie_noc.bridge_main0_esr_m_1_5_am_cgo register pcie_noc.bridge_main0_esr_m_1_5_am_cfg register pcie_noc.bridge_main0_esr_m_1_5_am_sts register pcie_noc.bridge_main0_esr_m_1_5_am_bridge_id register pcie_noc.bridge_main0_esr_m_1_5_am_err register pcie_noc.bridge_main0_esr_m_1_5_am_toslvid register pcie_noc.bridge_main0_esr_m_1_5_am_era register pcie_noc.bridge_main0_esr_m_1_5_am_ewa register pcie_noc.bridge_main0_esr_m_1_5_am_intm register pcie_noc.bridge_main0_esr_m_1_5_am_caddr register pcie_noc.bridge_main0_esr_m_1_5_am_caddrmsk register pcie_noc.bridge_main0_esr_m_1_5_am_ccmd0 register pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk0 register pcie_noc.bridge_main0_esr_m_1_5_am_cntr0 register pcie_noc.bridge_main0_esr_m_1_5_am_latnum0 register pcie_noc.bridge_main0_esr_m_1_5_am_ccmd1 register pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk1 register pcie_noc.bridge_main0_esr_m_1_5_am_cntr1 register pcie_noc.bridge_main0_esr_m_1_5_am_latnum1 register pcie_noc.bridge_main0_esr_m_1_5_am_arovrd register pcie_noc.bridge_main0_esr_m_1_5_am_awovrd register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_main0_mesh_m_2_5_p_0 register pcie_noc.bridge_main0_mesh_m_2_5_p_1 register pcie_noc.bridge_main0_mesh_m_2_5_p_2 register pcie_noc.bridge_main0_mesh_m_2_5_p_3 register pcie_noc.bridge_main0_mesh_m_2_5_txe register pcie_noc.bridge_main0_mesh_m_2_5_txem register pcie_noc.bridge_main0_mesh_m_2_5_btus_0 register pcie_noc.bridge_main0_mesh_m_2_5_btus_1 register pcie_noc.bridge_main0_mesh_m_2_5_btrl_0 register pcie_noc.bridge_main0_mesh_m_2_5_btrl_1 register pcie_noc.bridge_main0_mesh_m_2_5_btrl_2 register pcie_noc.bridge_main0_mesh_m_2_5_btrl_3 register pcie_noc.bridge_main0_mesh_m_2_5_btperr register pcie_noc.bridge_main0_mesh_m_2_5_btperrm register pcie_noc.bridge_main0_mesh_m_2_5_rxe register pcie_noc.bridge_main0_mesh_m_2_5_rxem register pcie_noc.bridge_main0_mesh_m_2_5_brs_0 register pcie_noc.bridge_main0_mesh_m_2_5_brs_1 register pcie_noc.bridge_main0_mesh_m_2_5_brus register pcie_noc.bridge_main0_mesh_m_2_5_brperr0 register pcie_noc.bridge_main0_mesh_m_2_5_brperr1 register pcie_noc.bridge_main0_mesh_m_2_5_brperrm0 register pcie_noc.bridge_main0_mesh_m_2_5_brperrm1 register pcie_noc.bridge_main0_mesh_m_2_5_am_tocfg register pcie_noc.bridge_main0_mesh_m_2_5_am_osslv register pcie_noc.bridge_main0_mesh_m_2_5_am_cgc register pcie_noc.bridge_main0_mesh_m_2_5_am_cgo register pcie_noc.bridge_main0_mesh_m_2_5_am_cfg register pcie_noc.bridge_main0_mesh_m_2_5_am_sts register pcie_noc.bridge_main0_mesh_m_2_5_am_bridge_id register pcie_noc.bridge_main0_mesh_m_2_5_am_err register pcie_noc.bridge_main0_mesh_m_2_5_am_toslvid register pcie_noc.bridge_main0_mesh_m_2_5_am_era register pcie_noc.bridge_main0_mesh_m_2_5_am_ewa register pcie_noc.bridge_main0_mesh_m_2_5_am_intm register pcie_noc.bridge_main0_mesh_m_2_5_am_caddr register pcie_noc.bridge_main0_mesh_m_2_5_am_caddrmsk register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmd0 register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmdmsk0 register pcie_noc.bridge_main0_mesh_m_2_5_am_cntr0 register pcie_noc.bridge_main0_mesh_m_2_5_am_latnum0 register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmd1 register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmdmsk1 register pcie_noc.bridge_main0_mesh_m_2_5_am_cntr1 register pcie_noc.bridge_main0_mesh_m_2_5_am_latnum1 register pcie_noc.bridge_main0_mesh_m_2_5_am_arovrd register pcie_noc.bridge_main0_mesh_m_2_5_am_awovrd register pcie_noc.bridge_main0_tol3_s_7_5_as_cgc register pcie_noc.bridge_main0_tol3_s_7_5_as_cgo register pcie_noc.bridge_main0_tol3_s_7_5_as_sts register pcie_noc.bridge_main0_tol3_s_7_5_as_bridge_id register pcie_noc.bridge_main0_tol3_s_7_5_as_err register pcie_noc.bridge_main0_tol3_s_7_5_as_intm register pcie_noc.bridge_main0_tol3_s_7_5_as_ccmd register pcie_noc.bridge_main0_tol3_s_7_5_as_ccmdmsk register pcie_noc.bridge_main0_tol3_s_7_5_as_cntr register pcie_noc.bridge_main0_tol3_s_7_5_as_arovrd register pcie_noc.bridge_main0_tol3_s_7_5_as_awovrd register pcie_noc.bridge_main0_tol3_s_7_5_p_0 register pcie_noc.bridge_main0_tol3_s_7_5_p_1 register pcie_noc.bridge_main0_tol3_s_7_5_p_2 register pcie_noc.bridge_main0_tol3_s_7_5_p_3 register pcie_noc.bridge_main0_tol3_s_7_5_txe register pcie_noc.bridge_main0_tol3_s_7_5_txem register pcie_noc.bridge_main0_tol3_s_7_5_btus_0 register pcie_noc.bridge_main0_tol3_s_7_5_btus_1 register pcie_noc.bridge_main0_tol3_s_7_5_btrl_0 register pcie_noc.bridge_main0_tol3_s_7_5_btrl_1 register pcie_noc.bridge_main0_tol3_s_7_5_btrl_2 register pcie_noc.bridge_main0_tol3_s_7_5_btrl_3 register pcie_noc.bridge_main0_tol3_s_7_5_btperr register pcie_noc.bridge_main0_tol3_s_7_5_btperrm register pcie_noc.bridge_main0_tol3_s_7_5_rxe register pcie_noc.bridge_main0_tol3_s_7_5_rxem register pcie_noc.bridge_main0_tol3_s_7_5_brs_0 register pcie_noc.bridge_main0_tol3_s_7_5_brs_1 register pcie_noc.bridge_main0_tol3_s_7_5_brus register pcie_noc.bridge_main0_tol3_s_7_5_brperr0 register pcie_noc.bridge_main0_tol3_s_7_5_brperr1 register pcie_noc.bridge_main0_tol3_s_7_5_brperrm0 register pcie_noc.bridge_main0_tol3_s_7_5_brperrm1 register pcie_noc.bridge_main0_tosys_s_8_5_as_cgc register pcie_noc.bridge_main0_tosys_s_8_5_as_cgo register pcie_noc.bridge_main0_tosys_s_8_5_as_sts register pcie_noc.bridge_main0_tosys_s_8_5_as_bridge_id register pcie_noc.bridge_main0_tosys_s_8_5_as_err register pcie_noc.bridge_main0_tosys_s_8_5_as_intm register pcie_noc.bridge_main0_tosys_s_8_5_as_ccmd register pcie_noc.bridge_main0_tosys_s_8_5_as_ccmdmsk register pcie_noc.bridge_main0_tosys_s_8_5_as_cntr register pcie_noc.bridge_main0_tosys_s_8_5_as_arovrd register pcie_noc.bridge_main0_tosys_s_8_5_as_awovrd register pcie_noc.bridge_main0_tosys_s_8_5_p_0 register pcie_noc.bridge_main0_tosys_s_8_5_p_1 register pcie_noc.bridge_main0_tosys_s_8_5_p_2 register pcie_noc.bridge_main0_tosys_s_8_5_p_3 register pcie_noc.bridge_main0_tosys_s_8_5_txe register pcie_noc.bridge_main0_tosys_s_8_5_txem register pcie_noc.bridge_main0_tosys_s_8_5_btus_0 register pcie_noc.bridge_main0_tosys_s_8_5_btus_1 register pcie_noc.bridge_main0_tosys_s_8_5_btrl_0 register pcie_noc.bridge_main0_tosys_s_8_5_btrl_1 register pcie_noc.bridge_main0_tosys_s_8_5_btrl_2 register pcie_noc.bridge_main0_tosys_s_8_5_btrl_3 register pcie_noc.bridge_main0_tosys_s_8_5_btperr register pcie_noc.bridge_main0_tosys_s_8_5_btperrm register pcie_noc.bridge_main0_tosys_s_8_5_rxe register pcie_noc.bridge_main0_tosys_s_8_5_rxem register pcie_noc.bridge_main0_tosys_s_8_5_brs_0 register pcie_noc.bridge_main0_tosys_s_8_5_brs_1 register pcie_noc.bridge_main0_tosys_s_8_5_brus register pcie_noc.bridge_main0_tosys_s_8_5_brperr0 register pcie_noc.bridge_main0_tosys_s_8_5_brperr1 register pcie_noc.bridge_main0_tosys_s_8_5_brperrm0 register pcie_noc.bridge_main0_tosys_s_8_5_brperrm1 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_p0_p0_m_3_6_p_0 register pcie_noc.bridge_p0_p0_m_3_6_p_1 register pcie_noc.bridge_p0_p0_m_3_6_p_2 register pcie_noc.bridge_p0_p0_m_3_6_p_3 register pcie_noc.bridge_p0_p0_m_3_6_txe register pcie_noc.bridge_p0_p0_m_3_6_txem register pcie_noc.bridge_p0_p0_m_3_6_btus_0 register pcie_noc.bridge_p0_p0_m_3_6_btus_1 register pcie_noc.bridge_p0_p0_m_3_6_btrl_0 register pcie_noc.bridge_p0_p0_m_3_6_btrl_1 register pcie_noc.bridge_p0_p0_m_3_6_btrl_2 register pcie_noc.bridge_p0_p0_m_3_6_btrl_3 register pcie_noc.bridge_p0_p0_m_3_6_btperr register pcie_noc.bridge_p0_p0_m_3_6_btperrm register pcie_noc.bridge_p0_p0_m_3_6_rxe register pcie_noc.bridge_p0_p0_m_3_6_rxem register pcie_noc.bridge_p0_p0_m_3_6_brs_0 register pcie_noc.bridge_p0_p0_m_3_6_brs_1 register pcie_noc.bridge_p0_p0_m_3_6_brus register pcie_noc.bridge_p0_p0_m_3_6_brperr0 register pcie_noc.bridge_p0_p0_m_3_6_brperr1 register pcie_noc.bridge_p0_p0_m_3_6_brperrm0 register pcie_noc.bridge_p0_p0_m_3_6_brperrm1 register pcie_noc.bridge_p0_p0_m_3_6_am_tocfg register pcie_noc.bridge_p0_p0_m_3_6_am_osslv register pcie_noc.bridge_p0_p0_m_3_6_am_cgc register pcie_noc.bridge_p0_p0_m_3_6_am_cgo register pcie_noc.bridge_p0_p0_m_3_6_am_cfg register pcie_noc.bridge_p0_p0_m_3_6_am_sts register pcie_noc.bridge_p0_p0_m_3_6_am_bridge_id register pcie_noc.bridge_p0_p0_m_3_6_am_err register pcie_noc.bridge_p0_p0_m_3_6_am_toslvid register pcie_noc.bridge_p0_p0_m_3_6_am_era register pcie_noc.bridge_p0_p0_m_3_6_am_ewa register pcie_noc.bridge_p0_p0_m_3_6_am_intm register pcie_noc.bridge_p0_p0_m_3_6_am_caddr register pcie_noc.bridge_p0_p0_m_3_6_am_caddrmsk register pcie_noc.bridge_p0_p0_m_3_6_am_ccmd0 register pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk0 register pcie_noc.bridge_p0_p0_m_3_6_am_cntr0 register pcie_noc.bridge_p0_p0_m_3_6_am_latnum0 register pcie_noc.bridge_p0_p0_m_3_6_am_ccmd1 register pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk1 register pcie_noc.bridge_p0_p0_m_3_6_am_cntr1 register pcie_noc.bridge_p0_p0_m_3_6_am_latnum1 register pcie_noc.bridge_p0_p0_m_3_6_am_arovrd register pcie_noc.bridge_p0_p0_m_3_6_am_awovrd register pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgc register pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgo register pcie_noc.bridge_p0_p0_reg_s_9_6_as_sts register pcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_id register pcie_noc.bridge_p0_p0_reg_s_9_6_as_err register pcie_noc.bridge_p0_p0_reg_s_9_6_as_intm register pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmd register pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmsk register pcie_noc.bridge_p0_p0_reg_s_9_6_as_cntr register pcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrd register pcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrd register pcie_noc.bridge_p0_p0_reg_s_9_6_p_0 register pcie_noc.bridge_p0_p0_reg_s_9_6_p_1 register pcie_noc.bridge_p0_p0_reg_s_9_6_p_2 register pcie_noc.bridge_p0_p0_reg_s_9_6_p_3 register pcie_noc.bridge_p0_p0_reg_s_9_6_txe register pcie_noc.bridge_p0_p0_reg_s_9_6_txem register pcie_noc.bridge_p0_p0_reg_s_9_6_btus_0 register pcie_noc.bridge_p0_p0_reg_s_9_6_btus_1 register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_0 register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_1 register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_2 register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_3 register pcie_noc.bridge_p0_p0_reg_s_9_6_btperr register pcie_noc.bridge_p0_p0_reg_s_9_6_btperrm register pcie_noc.bridge_p0_p0_reg_s_9_6_rxe register pcie_noc.bridge_p0_p0_reg_s_9_6_rxem register pcie_noc.bridge_p0_p0_reg_s_9_6_brs_0 register pcie_noc.bridge_p0_p0_reg_s_9_6_brs_1 register pcie_noc.bridge_p0_p0_reg_s_9_6_brus register pcie_noc.bridge_p0_p0_reg_s_9_6_brperr0 register pcie_noc.bridge_p0_p0_reg_s_9_6_brperr1 register pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm0 register pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm1 register pcie_noc.bridge_p0_p0_s_10_7_as_cgc register pcie_noc.bridge_p0_p0_s_10_7_as_cgo register pcie_noc.bridge_p0_p0_s_10_7_as_sts register pcie_noc.bridge_p0_p0_s_10_7_as_bridge_id register pcie_noc.bridge_p0_p0_s_10_7_as_err register pcie_noc.bridge_p0_p0_s_10_7_as_intm register pcie_noc.bridge_p0_p0_s_10_7_as_ccmd register pcie_noc.bridge_p0_p0_s_10_7_as_ccmdmsk register pcie_noc.bridge_p0_p0_s_10_7_as_cntr register pcie_noc.bridge_p0_p0_s_10_7_as_arovrd register pcie_noc.bridge_p0_p0_s_10_7_as_awovrd register pcie_noc.bridge_p0_p0_s_10_7_p_0 register pcie_noc.bridge_p0_p0_s_10_7_p_1 register pcie_noc.bridge_p0_p0_s_10_7_p_2 register pcie_noc.bridge_p0_p0_s_10_7_p_3 register pcie_noc.bridge_p0_p0_s_10_7_txe register pcie_noc.bridge_p0_p0_s_10_7_txem register pcie_noc.bridge_p0_p0_s_10_7_btus_0 register pcie_noc.bridge_p0_p0_s_10_7_btus_1 register pcie_noc.bridge_p0_p0_s_10_7_btrl_0 register pcie_noc.bridge_p0_p0_s_10_7_btrl_1 register pcie_noc.bridge_p0_p0_s_10_7_btrl_2 register pcie_noc.bridge_p0_p0_s_10_7_btrl_3 register pcie_noc.bridge_p0_p0_s_10_7_btperr register pcie_noc.bridge_p0_p0_s_10_7_btperrm register pcie_noc.bridge_p0_p0_s_10_7_rxe register pcie_noc.bridge_p0_p0_s_10_7_rxem register pcie_noc.bridge_p0_p0_s_10_7_brs_0 register pcie_noc.bridge_p0_p0_s_10_7_brs_1 register pcie_noc.bridge_p0_p0_s_10_7_brus register pcie_noc.bridge_p0_p0_s_10_7_brperr0 register pcie_noc.bridge_p0_p0_s_10_7_brperr1 register pcie_noc.bridge_p0_p0_s_10_7_brperrm0 register pcie_noc.bridge_p0_p0_s_10_7_brperrm1 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 register pcie_noc.bridge_p0_p1_m_4_6_p_0 register pcie_noc.bridge_p0_p1_m_4_6_p_1 register pcie_noc.bridge_p0_p1_m_4_6_p_2 register pcie_noc.bridge_p0_p1_m_4_6_p_3 register pcie_noc.bridge_p0_p1_m_4_6_txe register pcie_noc.bridge_p0_p1_m_4_6_txem register pcie_noc.bridge_p0_p1_m_4_6_btus_0 register pcie_noc.bridge_p0_p1_m_4_6_btus_1 register pcie_noc.bridge_p0_p1_m_4_6_btrl_0 register pcie_noc.bridge_p0_p1_m_4_6_btrl_1 register pcie_noc.bridge_p0_p1_m_4_6_btrl_2 register pcie_noc.bridge_p0_p1_m_4_6_btrl_3 register pcie_noc.bridge_p0_p1_m_4_6_btperr register pcie_noc.bridge_p0_p1_m_4_6_btperrm register pcie_noc.bridge_p0_p1_m_4_6_rxe register pcie_noc.bridge_p0_p1_m_4_6_rxem register pcie_noc.bridge_p0_p1_m_4_6_brs_0 register pcie_noc.bridge_p0_p1_m_4_6_brs_1 register pcie_noc.bridge_p0_p1_m_4_6_brus register pcie_noc.bridge_p0_p1_m_4_6_brperr0 register pcie_noc.bridge_p0_p1_m_4_6_brperr1 register pcie_noc.bridge_p0_p1_m_4_6_brperrm0 register pcie_noc.bridge_p0_p1_m_4_6_brperrm1 register pcie_noc.bridge_p0_p1_m_4_6_am_tocfg register pcie_noc.bridge_p0_p1_m_4_6_am_osslv register pcie_noc.bridge_p0_p1_m_4_6_am_cgc register pcie_noc.bridge_p0_p1_m_4_6_am_cgo register pcie_noc.bridge_p0_p1_m_4_6_am_cfg register pcie_noc.bridge_p0_p1_m_4_6_am_sts register pcie_noc.bridge_p0_p1_m_4_6_am_bridge_id register pcie_noc.bridge_p0_p1_m_4_6_am_err register pcie_noc.bridge_p0_p1_m_4_6_am_toslvid register pcie_noc.bridge_p0_p1_m_4_6_am_era register pcie_noc.bridge_p0_p1_m_4_6_am_ewa register pcie_noc.bridge_p0_p1_m_4_6_am_intm register pcie_noc.bridge_p0_p1_m_4_6_am_caddr register pcie_noc.bridge_p0_p1_m_4_6_am_caddrmsk register pcie_noc.bridge_p0_p1_m_4_6_am_ccmd0 register pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk0 register pcie_noc.bridge_p0_p1_m_4_6_am_cntr0 register pcie_noc.bridge_p0_p1_m_4_6_am_latnum0 register pcie_noc.bridge_p0_p1_m_4_6_am_ccmd1 register pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk1 register pcie_noc.bridge_p0_p1_m_4_6_am_cntr1 register pcie_noc.bridge_p0_p1_m_4_6_am_latnum1 register pcie_noc.bridge_p0_p1_m_4_6_am_arovrd register pcie_noc.bridge_p0_p1_m_4_6_am_awovrd register pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgc register pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgo register pcie_noc.bridge_p0_p1_reg_s_11_6_as_sts register pcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_id register pcie_noc.bridge_p0_p1_reg_s_11_6_as_err register pcie_noc.bridge_p0_p1_reg_s_11_6_as_intm register pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmd register pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmsk register pcie_noc.bridge_p0_p1_reg_s_11_6_as_cntr register pcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrd register pcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrd register pcie_noc.bridge_p0_p1_reg_s_11_6_p_0 register pcie_noc.bridge_p0_p1_reg_s_11_6_p_1 register pcie_noc.bridge_p0_p1_reg_s_11_6_p_2 register pcie_noc.bridge_p0_p1_reg_s_11_6_p_3 register pcie_noc.bridge_p0_p1_reg_s_11_6_txe register pcie_noc.bridge_p0_p1_reg_s_11_6_txem register pcie_noc.bridge_p0_p1_reg_s_11_6_btus_0 register pcie_noc.bridge_p0_p1_reg_s_11_6_btus_1 register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_0 register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_1 register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_2 register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_3 register pcie_noc.bridge_p0_p1_reg_s_11_6_btperr register pcie_noc.bridge_p0_p1_reg_s_11_6_btperrm register pcie_noc.bridge_p0_p1_reg_s_11_6_rxe register pcie_noc.bridge_p0_p1_reg_s_11_6_rxem register pcie_noc.bridge_p0_p1_reg_s_11_6_brs_0 register pcie_noc.bridge_p0_p1_reg_s_11_6_brs_1 register pcie_noc.bridge_p0_p1_reg_s_11_6_brus register pcie_noc.bridge_p0_p1_reg_s_11_6_brperr0 register pcie_noc.bridge_p0_p1_reg_s_11_6_brperr1 register pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm0 register pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm1 register pcie_noc.bridge_p0_p1_s_12_10_as_cgc register pcie_noc.bridge_p0_p1_s_12_10_as_cgo register pcie_noc.bridge_p0_p1_s_12_10_as_sts register pcie_noc.bridge_p0_p1_s_12_10_as_bridge_id register pcie_noc.bridge_p0_p1_s_12_10_as_err register pcie_noc.bridge_p0_p1_s_12_10_as_intm register pcie_noc.bridge_p0_p1_s_12_10_as_ccmd register pcie_noc.bridge_p0_p1_s_12_10_as_ccmdmsk register pcie_noc.bridge_p0_p1_s_12_10_as_cntr register pcie_noc.bridge_p0_p1_s_12_10_as_arovrd register pcie_noc.bridge_p0_p1_s_12_10_as_awovrd register pcie_noc.bridge_p0_p1_s_12_10_p_0 register pcie_noc.bridge_p0_p1_s_12_10_p_1 register pcie_noc.bridge_p0_p1_s_12_10_p_2 register pcie_noc.bridge_p0_p1_s_12_10_p_3 register pcie_noc.bridge_p0_p1_s_12_10_txe register pcie_noc.bridge_p0_p1_s_12_10_txem register pcie_noc.bridge_p0_p1_s_12_10_btus_0 register pcie_noc.bridge_p0_p1_s_12_10_btus_1 register pcie_noc.bridge_p0_p1_s_12_10_btrl_0 register pcie_noc.bridge_p0_p1_s_12_10_btrl_1 register pcie_noc.bridge_p0_p1_s_12_10_btrl_2 register pcie_noc.bridge_p0_p1_s_12_10_btrl_3 register pcie_noc.bridge_p0_p1_s_12_10_btperr register pcie_noc.bridge_p0_p1_s_12_10_btperrm register pcie_noc.bridge_p0_p1_s_12_10_rxe register pcie_noc.bridge_p0_p1_s_12_10_rxem register pcie_noc.bridge_p0_p1_s_12_10_brs_0 register pcie_noc.bridge_p0_p1_s_12_10_brs_1 register pcie_noc.bridge_p0_p1_s_12_10_brus register pcie_noc.bridge_p0_p1_s_12_10_brperr0 register pcie_noc.bridge_p0_p1_s_12_10_brperr1 register pcie_noc.bridge_p0_p1_s_12_10_brperrm0 register pcie_noc.bridge_p0_p1_s_12_10_brperrm1 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 register pcie_noc.bridge_p0_spio_m_5_7_p_0 register pcie_noc.bridge_p0_spio_m_5_7_p_1 register pcie_noc.bridge_p0_spio_m_5_7_p_2 register pcie_noc.bridge_p0_spio_m_5_7_p_3 register pcie_noc.bridge_p0_spio_m_5_7_txe register pcie_noc.bridge_p0_spio_m_5_7_txem register pcie_noc.bridge_p0_spio_m_5_7_btus_0 register pcie_noc.bridge_p0_spio_m_5_7_btus_1 register pcie_noc.bridge_p0_spio_m_5_7_btrl_0 register pcie_noc.bridge_p0_spio_m_5_7_btrl_1 register pcie_noc.bridge_p0_spio_m_5_7_btrl_2 register pcie_noc.bridge_p0_spio_m_5_7_btrl_3 register pcie_noc.bridge_p0_spio_m_5_7_btperr register pcie_noc.bridge_p0_spio_m_5_7_btperrm register pcie_noc.bridge_p0_spio_m_5_7_rxe register pcie_noc.bridge_p0_spio_m_5_7_rxem register pcie_noc.bridge_p0_spio_m_5_7_brs_0 register pcie_noc.bridge_p0_spio_m_5_7_brs_1 register pcie_noc.bridge_p0_spio_m_5_7_brus register pcie_noc.bridge_p0_spio_m_5_7_brperr0 register pcie_noc.bridge_p0_spio_m_5_7_brperr1 register pcie_noc.bridge_p0_spio_m_5_7_brperrm0 register pcie_noc.bridge_p0_spio_m_5_7_brperrm1 register pcie_noc.bridge_p0_spio_m_5_7_am_tocfg register pcie_noc.bridge_p0_spio_m_5_7_am_osslv register pcie_noc.bridge_p0_spio_m_5_7_am_cgc register pcie_noc.bridge_p0_spio_m_5_7_am_cgo register pcie_noc.bridge_p0_spio_m_5_7_am_cfg register pcie_noc.bridge_p0_spio_m_5_7_am_sts register pcie_noc.bridge_p0_spio_m_5_7_am_bridge_id register pcie_noc.bridge_p0_spio_m_5_7_am_err register pcie_noc.bridge_p0_spio_m_5_7_am_toslvid register pcie_noc.bridge_p0_spio_m_5_7_am_era register pcie_noc.bridge_p0_spio_m_5_7_am_ewa register pcie_noc.bridge_p0_spio_m_5_7_am_intm register pcie_noc.bridge_p0_spio_m_5_7_am_caddr register pcie_noc.bridge_p0_spio_m_5_7_am_caddrmsk register pcie_noc.bridge_p0_spio_m_5_7_am_ccmd0 register pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk0 register pcie_noc.bridge_p0_spio_m_5_7_am_cntr0 register pcie_noc.bridge_p0_spio_m_5_7_am_latnum0 register pcie_noc.bridge_p0_spio_m_5_7_am_ccmd1 register pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk1 register pcie_noc.bridge_p0_spio_m_5_7_am_cntr1 register pcie_noc.bridge_p0_spio_m_5_7_am_latnum1 register pcie_noc.bridge_p0_spio_m_5_7_am_arovrd register pcie_noc.bridge_p0_spio_m_5_7_am_awovrd register pcie_noc.router_0_5_5_rivcs_h register pcie_noc.router_0_5_5_rivcs_e register pcie_noc.router_0_5_5_rivcs_s register pcie_noc.router_0_5_5_rivcs_w register pcie_noc.router_0_5_5_rivcs_i register pcie_noc.router_0_5_5_rivcs_j register pcie_noc.router_0_5_5_rivcs_k register pcie_noc.router_0_5_5_rovcs_h register pcie_noc.router_0_5_5_rovcs_e register pcie_noc.router_0_5_5_rovcs_s register pcie_noc.router_0_5_5_rovcs_w register pcie_noc.router_0_5_5_rovcs_i register pcie_noc.router_0_5_5_rovcs_j register pcie_noc.router_0_5_5_rovcs_k register pcie_noc.router_0_5_5_re register pcie_noc.router_0_5_5_rem register pcie_noc.router_0_5_5_recc register pcie_noc.router_0_5_5_rec register pcie_noc.router_0_5_5_id register pcie_noc.router_0_5_5_rcgc register pcie_noc.router_0_5_5_rcgo register pcie_noc.router_0_5_5_p1_rperr register pcie_noc.router_0_5_5_p2_rperr register pcie_noc.router_0_5_5_p3_rperr register pcie_noc.router_0_5_5_p4_rperr register pcie_noc.router_0_5_5_p5_rperr register pcie_noc.router_0_5_5_p6_rperr register pcie_noc.router_0_5_5_p7_rperr register pcie_noc.router_0_5_5_p1_rperrm register pcie_noc.router_0_5_5_p2_rperrm register pcie_noc.router_0_5_5_p3_rperrm register pcie_noc.router_0_5_5_p4_rperrm register pcie_noc.router_0_5_5_p5_rperrm register pcie_noc.router_0_5_5_p6_rperrm register pcie_noc.router_0_5_5_p7_rperrm register pcie_noc.router_0_5_5_roecc register pcie_noc.router_0_5_5_roec register pcie_noc.router_0_6_6_rivcs_h register pcie_noc.router_0_6_6_rivcs_e register pcie_noc.router_0_6_6_rivcs_s register pcie_noc.router_0_6_6_rivcs_w register pcie_noc.router_0_6_6_rivcs_n register pcie_noc.router_0_6_6_rivcs_i register pcie_noc.router_0_6_6_rivcs_j register pcie_noc.router_0_6_6_rivcs_k register pcie_noc.router_0_6_6_rovcs_h register pcie_noc.router_0_6_6_rovcs_e register pcie_noc.router_0_6_6_rovcs_s register pcie_noc.router_0_6_6_rovcs_w register pcie_noc.router_0_6_6_rovcs_n register pcie_noc.router_0_6_6_rovcs_i register pcie_noc.router_0_6_6_rovcs_j register pcie_noc.router_0_6_6_rovcs_k register pcie_noc.router_0_6_6_re register pcie_noc.router_0_6_6_rem register pcie_noc.router_0_6_6_recc register pcie_noc.router_0_6_6_rec register pcie_noc.router_0_6_6_id register pcie_noc.router_0_6_6_rcgc register pcie_noc.router_0_6_6_rcgo register pcie_noc.router_0_6_6_p0_rperr register pcie_noc.router_0_6_6_p1_rperr register pcie_noc.router_0_6_6_p2_rperr register pcie_noc.router_0_6_6_p3_rperr register pcie_noc.router_0_6_6_p4_rperr register pcie_noc.router_0_6_6_p5_rperr register pcie_noc.router_0_6_6_p6_rperr register pcie_noc.router_0_6_6_p7_rperr register pcie_noc.router_0_6_6_p0_rperrm register pcie_noc.router_0_6_6_p1_rperrm register pcie_noc.router_0_6_6_p2_rperrm register pcie_noc.router_0_6_6_p3_rperrm register pcie_noc.router_0_6_6_p4_rperrm register pcie_noc.router_0_6_6_p5_rperrm register pcie_noc.router_0_6_6_p6_rperrm register pcie_noc.router_0_6_6_p7_rperrm register pcie_noc.router_0_6_6_roecc register pcie_noc.router_0_6_6_roec register pcie_noc.router_1_5_5_rivcs_h register pcie_noc.router_1_5_5_rivcs_e register pcie_noc.router_1_5_5_rivcs_s register pcie_noc.router_1_5_5_rivcs_w register pcie_noc.router_1_5_5_rivcs_i register pcie_noc.router_1_5_5_rivcs_j register pcie_noc.router_1_5_5_rivcs_k register pcie_noc.router_1_5_5_rovcs_h register pcie_noc.router_1_5_5_rovcs_e register pcie_noc.router_1_5_5_rovcs_s register pcie_noc.router_1_5_5_rovcs_w register pcie_noc.router_1_5_5_rovcs_i register pcie_noc.router_1_5_5_rovcs_j register pcie_noc.router_1_5_5_rovcs_k register pcie_noc.router_1_5_5_re register pcie_noc.router_1_5_5_rem register pcie_noc.router_1_5_5_recc register pcie_noc.router_1_5_5_rec register pcie_noc.router_1_5_5_id register pcie_noc.router_1_5_5_rcgc register pcie_noc.router_1_5_5_rcgo register pcie_noc.router_1_5_5_p1_rperr register pcie_noc.router_1_5_5_p2_rperr register pcie_noc.router_1_5_5_p3_rperr register pcie_noc.router_1_5_5_p4_rperr register pcie_noc.router_1_5_5_p5_rperr register pcie_noc.router_1_5_5_p6_rperr register pcie_noc.router_1_5_5_p7_rperr register pcie_noc.router_1_5_5_p1_rperrm register pcie_noc.router_1_5_5_p2_rperrm register pcie_noc.router_1_5_5_p3_rperrm register pcie_noc.router_1_5_5_p4_rperrm register pcie_noc.router_1_5_5_p5_rperrm register pcie_noc.router_1_5_5_p6_rperrm register pcie_noc.router_1_5_5_p7_rperrm register pcie_noc.router_1_5_5_roecc register pcie_noc.router_1_5_5_roec register pcie_noc.router_1_6_6_rivcs_h register pcie_noc.router_1_6_6_rivcs_e register pcie_noc.router_1_6_6_rivcs_s register pcie_noc.router_1_6_6_rivcs_w register pcie_noc.router_1_6_6_rivcs_n register pcie_noc.router_1_6_6_rivcs_i register pcie_noc.router_1_6_6_rivcs_j register pcie_noc.router_1_6_6_rivcs_k register pcie_noc.router_1_6_6_rovcs_h register pcie_noc.router_1_6_6_rovcs_e register pcie_noc.router_1_6_6_rovcs_s register pcie_noc.router_1_6_6_rovcs_w register pcie_noc.router_1_6_6_rovcs_n register pcie_noc.router_1_6_6_rovcs_i register pcie_noc.router_1_6_6_rovcs_j register pcie_noc.router_1_6_6_rovcs_k register pcie_noc.router_1_6_6_re register pcie_noc.router_1_6_6_rem register pcie_noc.router_1_6_6_recc register pcie_noc.router_1_6_6_rec register pcie_noc.router_1_6_6_id register pcie_noc.router_1_6_6_rcgc register pcie_noc.router_1_6_6_rcgo register pcie_noc.router_1_6_6_p0_rperr register pcie_noc.router_1_6_6_p1_rperr register pcie_noc.router_1_6_6_p2_rperr register pcie_noc.router_1_6_6_p3_rperr register pcie_noc.router_1_6_6_p4_rperr register pcie_noc.router_1_6_6_p5_rperr register pcie_noc.router_1_6_6_p6_rperr register pcie_noc.router_1_6_6_p7_rperr register pcie_noc.router_1_6_6_p0_rperrm register pcie_noc.router_1_6_6_p1_rperrm register pcie_noc.router_1_6_6_p2_rperrm register pcie_noc.router_1_6_6_p3_rperrm register pcie_noc.router_1_6_6_p4_rperrm register pcie_noc.router_1_6_6_p5_rperrm register pcie_noc.router_1_6_6_p6_rperrm register pcie_noc.router_1_6_6_p7_rperrm register pcie_noc.router_1_6_6_roecc register pcie_noc.router_1_6_6_roec register pcie_noc.router_2_1_1_re register pcie_noc.router_2_1_1_rem register pcie_noc.router_2_1_1_id register pcie_noc.router_2_1_1_rcgo register pcie_noc.router_2_1_1_p1_rperr register pcie_noc.router_2_1_1_p2_rperr register pcie_noc.router_2_1_1_p3_rperr register pcie_noc.router_2_1_1_p4_rperr register pcie_noc.router_2_1_1_p1_rperrm register pcie_noc.router_2_1_1_p2_rperrm register pcie_noc.router_2_1_1_p3_rperrm register pcie_noc.router_2_1_1_p4_rperrm register pcie_noc.router_2_3_3_re register pcie_noc.router_2_3_3_rem register pcie_noc.router_2_3_3_id register pcie_noc.router_2_3_3_rcgo register pcie_noc.router_2_3_3_p2_rperr register pcie_noc.router_2_3_3_p3_rperr register pcie_noc.router_2_3_3_p4_rperr register pcie_noc.router_2_3_3_p2_rperrm register pcie_noc.router_2_3_3_p3_rperrm register pcie_noc.router_2_3_3_p4_rperrm register pcie_noc.router_2_5_5_re register pcie_noc.router_2_5_5_rem register pcie_noc.router_2_5_5_id register pcie_noc.router_2_5_5_rcgo register pcie_noc.router_2_5_5_p0_rperr register pcie_noc.router_2_5_5_p1_rperr register pcie_noc.router_2_5_5_p4_rperr register pcie_noc.router_2_5_5_p0_rperrm register pcie_noc.router_2_5_5_p1_rperrm register pcie_noc.router_2_5_5_p4_rperrm register pcie_noc.router_2_7_7_re register pcie_noc.router_2_7_7_rem register pcie_noc.router_2_7_7_id register pcie_noc.router_2_7_7_rcgo register pcie_noc.router_2_7_7_p0_rperr register pcie_noc.router_2_7_7_p3_rperr register pcie_noc.router_2_7_7_p4_rperr register pcie_noc.router_2_7_7_p0_rperrm register pcie_noc.router_2_7_7_p3_rperrm register pcie_noc.router_2_7_7_p4_rperrm 0x0 0x7FFFF pcie_noc pcie_noc 0x0 0x2FFF 0x3000 0x3000 pcie_noc.bridge_rbm_m_13_1_p_0 pcie_noc.bridge_rbm_m_13_1_p_0 0x3004 0x3007 0x3008 0x3008 pcie_noc.bridge_rbm_m_13_1_p_1 pcie_noc.bridge_rbm_m_13_1_p_1 0x300C 0x300F 0x3010 0x3010 pcie_noc.bridge_rbm_m_13_1_p_2 pcie_noc.bridge_rbm_m_13_1_p_2 0x3014 0x3017 0x3018 0x3018 pcie_noc.bridge_rbm_m_13_1_p_3 pcie_noc.bridge_rbm_m_13_1_p_3 0x301C 0x303F 0x3040 0x3040 pcie_noc.bridge_rbm_m_13_1_txe pcie_noc.bridge_rbm_m_13_1_txe 0x3044 0x3047 0x3048 0x3048 pcie_noc.bridge_rbm_m_13_1_txem pcie_noc.bridge_rbm_m_13_1_txem 0x304C 0x3057 0x3058 0x3058 pcie_noc.bridge_rbm_m_13_1_btus_0 pcie_noc.bridge_rbm_m_13_1_btus_0 0x305C 0x305F 0x3060 0x3060 pcie_noc.bridge_rbm_m_13_1_btus_1 pcie_noc.bridge_rbm_m_13_1_btus_1 0x3064 0x307F 0x3080 0x3080 pcie_noc.bridge_rbm_m_13_1_btrl_0 pcie_noc.bridge_rbm_m_13_1_btrl_0 0x3084 0x3087 0x3088 0x3088 pcie_noc.bridge_rbm_m_13_1_btrl_1 pcie_noc.bridge_rbm_m_13_1_btrl_1 0x308C 0x308F 0x3090 0x3090 pcie_noc.bridge_rbm_m_13_1_btrl_2 pcie_noc.bridge_rbm_m_13_1_btrl_2 0x3094 0x3097 0x3098 0x3098 pcie_noc.bridge_rbm_m_13_1_btrl_3 pcie_noc.bridge_rbm_m_13_1_btrl_3 0x309C 0x30A7 0x30A8 0x30A8 pcie_noc.bridge_rbm_m_13_1_btperr pcie_noc.bridge_rbm_m_13_1_btperr 0x30AC 0x30AF 0x30B0 0x30B0 pcie_noc.bridge_rbm_m_13_1_btperrm pcie_noc.bridge_rbm_m_13_1_btperrm 0x30B4 0x311F 0x3120 0x3120 pcie_noc.bridge_rbm_m_13_1_rxe pcie_noc.bridge_rbm_m_13_1_rxe 0x3124 0x3127 0x3128 0x3128 pcie_noc.bridge_rbm_m_13_1_rxem pcie_noc.bridge_rbm_m_13_1_rxem 0x312C 0x312F 0x3130 0x3130 pcie_noc.bridge_rbm_m_13_1_brs_0 pcie_noc.bridge_rbm_m_13_1_brs_0 0x3134 0x3137 0x3138 0x3138 pcie_noc.bridge_rbm_m_13_1_brs_1 pcie_noc.bridge_rbm_m_13_1_brs_1 0x313C 0x31AF 0x31B0 0x31B0 pcie_noc.bridge_rbm_m_13_1_brus pcie_noc.bridge_rbm_m_13_1_brus 0x31B4 0x31CF 0x31D0 0x31D0 pcie_noc.bridge_rbm_m_13_1_brperr0 pcie_noc.bridge_rbm_m_13_1_brperr0 0x31D8 0x31D8 pcie_noc.bridge_rbm_m_13_1_brperr1 pcie_noc.bridge_rbm_m_13_1_brperr1 0x31E0 0x31E0 pcie_noc.bridge_rbm_m_13_1_brperrm0 pcie_noc.bridge_rbm_m_13_1_brperrm0 0x31E8 0x31E8 pcie_noc.bridge_rbm_m_13_1_brperrm1 pcie_noc.bridge_rbm_m_13_1_brperrm1 0x31F0 0x3BFF 0x3C00 0x3C00 pcie_noc.bridge_rbm_m_13_1_am_tocfg pcie_noc.bridge_rbm_m_13_1_am_tocfg 0x3C08 0x3C08 pcie_noc.bridge_rbm_m_13_1_am_osslv pcie_noc.bridge_rbm_m_13_1_am_osslv 0x3C10 0x3C10 pcie_noc.bridge_rbm_m_13_1_am_cgc pcie_noc.bridge_rbm_m_13_1_am_cgc 0x3C18 0x3C18 pcie_noc.bridge_rbm_m_13_1_am_cgo pcie_noc.bridge_rbm_m_13_1_am_cgo 0x3C20 0x3C20 pcie_noc.bridge_rbm_m_13_1_am_cfg pcie_noc.bridge_rbm_m_13_1_am_cfg 0x3C28 0x3CFF 0x3D00 0x3D00 pcie_noc.bridge_rbm_m_13_1_am_sts pcie_noc.bridge_rbm_m_13_1_am_sts 0x3D08 0x3D08 pcie_noc.bridge_rbm_m_13_1_am_bridge_id pcie_noc.bridge_rbm_m_13_1_am_bridge_id 0x3D10 0x3D10 pcie_noc.bridge_rbm_m_13_1_am_nocver_id pcie_noc.bridge_rbm_m_13_1_am_nocver_id 0x3D18 0x3DFF 0x3E00 0x3E00 pcie_noc.bridge_rbm_m_13_1_am_err pcie_noc.bridge_rbm_m_13_1_am_err 0x3E08 0x3E08 pcie_noc.bridge_rbm_m_13_1_am_toslvid pcie_noc.bridge_rbm_m_13_1_am_toslvid 0x3E10 0x3E10 pcie_noc.bridge_rbm_m_13_1_am_era pcie_noc.bridge_rbm_m_13_1_am_era 0x3E18 0x3E18 pcie_noc.bridge_rbm_m_13_1_am_ewa pcie_noc.bridge_rbm_m_13_1_am_ewa 0x3E20 0x3E3F 0x3E40 0x3E40 pcie_noc.bridge_rbm_m_13_1_am_intm pcie_noc.bridge_rbm_m_13_1_am_intm 0x3E48 0x3EFF 0x3F00 0x3F00 pcie_noc.bridge_rbm_m_13_1_am_caddr pcie_noc.bridge_rbm_m_13_1_am_caddr 0x3F08 0x3F08 pcie_noc.bridge_rbm_m_13_1_am_caddrmsk pcie_noc.bridge_rbm_m_13_1_am_caddrmsk 0x3F10 0x3F10 pcie_noc.bridge_rbm_m_13_1_am_ccmd0 pcie_noc.bridge_rbm_m_13_1_am_ccmd0 0x3F18 0x3F18 pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0 pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0 0x3F20 0x3F20 pcie_noc.bridge_rbm_m_13_1_am_cntr0 pcie_noc.bridge_rbm_m_13_1_am_cntr0 0x3F28 0x3F28 pcie_noc.bridge_rbm_m_13_1_am_latnum0 pcie_noc.bridge_rbm_m_13_1_am_latnum0 0x3F30 0x3F30 pcie_noc.bridge_rbm_m_13_1_am_ccmd1 pcie_noc.bridge_rbm_m_13_1_am_ccmd1 0x3F38 0x3F38 pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk1 pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk1 0x3F40 0x3F40 pcie_noc.bridge_rbm_m_13_1_am_cntr1 pcie_noc.bridge_rbm_m_13_1_am_cntr1 0x3F48 0x3F48 pcie_noc.bridge_rbm_m_13_1_am_latnum1 pcie_noc.bridge_rbm_m_13_1_am_latnum1 0x3F50 0x3F5F 0x3F60 0x3F60 pcie_noc.bridge_rbm_m_13_1_am_arovrd pcie_noc.bridge_rbm_m_13_1_am_arovrd 0x3F68 0x3F68 pcie_noc.bridge_rbm_m_13_1_am_awovrd pcie_noc.bridge_rbm_m_13_1_am_awovrd 0x3F70 0x41FF 0x4200 0x4200 pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_version pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_version 0x4208 0x4208 pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_id pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_id 0x4210 0x4210 pcie_noc.bridge_main0_apb_s_6_6_apbslv_slvs_sleep_status pcie_noc.bridge_main0_apb_s_6_6_apbslv_slvs_sleep_status 0x4218 0x5C0F 0x5C10 0x5C10 pcie_noc.bridge_main0_apb_s_6_6_as_cgc pcie_noc.bridge_main0_apb_s_6_6_as_cgc 0x5C18 0x5C18 pcie_noc.bridge_main0_apb_s_6_6_as_cgo pcie_noc.bridge_main0_apb_s_6_6_as_cgo 0x5C20 0x5CFF 0x5D00 0x5D00 pcie_noc.bridge_main0_apb_s_6_6_as_sts pcie_noc.bridge_main0_apb_s_6_6_as_sts 0x5D08 0x5D08 pcie_noc.bridge_main0_apb_s_6_6_as_bridge_id pcie_noc.bridge_main0_apb_s_6_6_as_bridge_id 0x5D10 0x5DFF 0x5E00 0x5E00 pcie_noc.bridge_main0_apb_s_6_6_as_err pcie_noc.bridge_main0_apb_s_6_6_as_err 0x5E08 0x5E3F 0x5E40 0x5E40 pcie_noc.bridge_main0_apb_s_6_6_as_intm pcie_noc.bridge_main0_apb_s_6_6_as_intm 0x5E48 0x5EFF 0x5F00 0x5F00 pcie_noc.bridge_main0_apb_s_6_6_as_ccmd pcie_noc.bridge_main0_apb_s_6_6_as_ccmd 0x5F08 0x5F08 pcie_noc.bridge_main0_apb_s_6_6_as_ccmdmsk pcie_noc.bridge_main0_apb_s_6_6_as_ccmdmsk 0x5F10 0x5F10 pcie_noc.bridge_main0_apb_s_6_6_as_cntr pcie_noc.bridge_main0_apb_s_6_6_as_cntr 0x5F18 0x5F18 pcie_noc.bridge_main0_apb_s_6_6_as_arovrd pcie_noc.bridge_main0_apb_s_6_6_as_arovrd 0x5F20 0x5F20 pcie_noc.bridge_main0_apb_s_6_6_as_awovrd pcie_noc.bridge_main0_apb_s_6_6_as_awovrd 0x5F28 0x6FFF 0x7000 0x7000 pcie_noc.bridge_main0_apb_s_6_6_p_0 pcie_noc.bridge_main0_apb_s_6_6_p_0 0x7004 0x7007 0x7008 0x7008 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pcie_noc.bridge_main0_apb_s_6_6_btrl_2 0x7094 0x7097 0x7098 0x7098 pcie_noc.bridge_main0_apb_s_6_6_btrl_3 pcie_noc.bridge_main0_apb_s_6_6_btrl_3 0x709C 0x70A7 0x70A8 0x70A8 pcie_noc.bridge_main0_apb_s_6_6_btperr pcie_noc.bridge_main0_apb_s_6_6_btperr 0x70AC 0x70AF 0x70B0 0x70B0 pcie_noc.bridge_main0_apb_s_6_6_btperrm pcie_noc.bridge_main0_apb_s_6_6_btperrm 0x70B4 0x711F 0x7120 0x7120 pcie_noc.bridge_main0_apb_s_6_6_rxe pcie_noc.bridge_main0_apb_s_6_6_rxe 0x7124 0x7127 0x7128 0x7128 pcie_noc.bridge_main0_apb_s_6_6_rxem pcie_noc.bridge_main0_apb_s_6_6_rxem 0x712C 0x712F 0x7130 0x7130 pcie_noc.bridge_main0_apb_s_6_6_brs_0 pcie_noc.bridge_main0_apb_s_6_6_brs_0 0x7134 0x7137 0x7138 0x7138 pcie_noc.bridge_main0_apb_s_6_6_brs_1 pcie_noc.bridge_main0_apb_s_6_6_brs_1 0x713C 0x71AF 0x71B0 0x71B0 pcie_noc.bridge_main0_apb_s_6_6_brus pcie_noc.bridge_main0_apb_s_6_6_brus 0x71B4 0x71CF 0x71D0 0x71D0 pcie_noc.bridge_main0_apb_s_6_6_brperr0 pcie_noc.bridge_main0_apb_s_6_6_brperr0 0x71D8 0x71D8 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pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x8590 0x859F 0x85A0 0x85A0 pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x85A8 0x85A8 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x85B0 0x85BF 0x85C0 0x85C0 pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x85C8 0x85C8 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x85D0 0x85DF 0x85E0 0x85E0 pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x85E8 0x85E8 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x85F0 0xAFFF 0xB000 0xB000 pcie_noc.bridge_main0_dbg_m_0_9_p_0 pcie_noc.bridge_main0_dbg_m_0_9_p_0 0xB004 0xB007 0xB008 0xB008 pcie_noc.bridge_main0_dbg_m_0_9_p_1 pcie_noc.bridge_main0_dbg_m_0_9_p_1 0xB00C 0xB00F 0xB010 0xB010 pcie_noc.bridge_main0_dbg_m_0_9_p_2 pcie_noc.bridge_main0_dbg_m_0_9_p_2 0xB014 0xB017 0xB018 0xB018 pcie_noc.bridge_main0_dbg_m_0_9_p_3 pcie_noc.bridge_main0_dbg_m_0_9_p_3 0xB01C 0xB03F 0xB040 0xB040 pcie_noc.bridge_main0_dbg_m_0_9_txe pcie_noc.bridge_main0_dbg_m_0_9_txe 0xB044 0xB047 0xB048 0xB048 pcie_noc.bridge_main0_dbg_m_0_9_txem pcie_noc.bridge_main0_dbg_m_0_9_txem 0xB04C 0xB057 0xB058 0xB058 pcie_noc.bridge_main0_dbg_m_0_9_btus_0 pcie_noc.bridge_main0_dbg_m_0_9_btus_0 0xB05C 0xB05F 0xB060 0xB060 pcie_noc.bridge_main0_dbg_m_0_9_btus_1 pcie_noc.bridge_main0_dbg_m_0_9_btus_1 0xB064 0xB07F 0xB080 0xB080 pcie_noc.bridge_main0_dbg_m_0_9_btrl_0 pcie_noc.bridge_main0_dbg_m_0_9_btrl_0 0xB084 0xB087 0xB088 0xB088 pcie_noc.bridge_main0_dbg_m_0_9_btrl_1 pcie_noc.bridge_main0_dbg_m_0_9_btrl_1 0xB08C 0xB08F 0xB090 0xB090 pcie_noc.bridge_main0_dbg_m_0_9_btrl_2 pcie_noc.bridge_main0_dbg_m_0_9_btrl_2 0xB094 0xB097 0xB098 0xB098 pcie_noc.bridge_main0_dbg_m_0_9_btrl_3 pcie_noc.bridge_main0_dbg_m_0_9_btrl_3 0xB09C 0xB0A7 0xB0A8 0xB0A8 pcie_noc.bridge_main0_dbg_m_0_9_btperr pcie_noc.bridge_main0_dbg_m_0_9_btperr 0xB0AC 0xB0AF 0xB0B0 0xB0B0 pcie_noc.bridge_main0_dbg_m_0_9_btperrm pcie_noc.bridge_main0_dbg_m_0_9_btperrm 0xB0B4 0xB11F 0xB120 0xB120 pcie_noc.bridge_main0_dbg_m_0_9_rxe pcie_noc.bridge_main0_dbg_m_0_9_rxe 0xB124 0xB127 0xB128 0xB128 pcie_noc.bridge_main0_dbg_m_0_9_rxem pcie_noc.bridge_main0_dbg_m_0_9_rxem 0xB12C 0xB12F 0xB130 0xB130 pcie_noc.bridge_main0_dbg_m_0_9_brs_0 pcie_noc.bridge_main0_dbg_m_0_9_brs_0 0xB134 0xB137 0xB138 0xB138 pcie_noc.bridge_main0_dbg_m_0_9_brs_1 pcie_noc.bridge_main0_dbg_m_0_9_brs_1 0xB13C 0xB1AF 0xB1B0 0xB1B0 pcie_noc.bridge_main0_dbg_m_0_9_brus pcie_noc.bridge_main0_dbg_m_0_9_brus 0xB1B4 0xB1CF 0xB1D0 0xB1D0 pcie_noc.bridge_main0_dbg_m_0_9_brperr0 pcie_noc.bridge_main0_dbg_m_0_9_brperr0 0xB1D8 0xB1D8 pcie_noc.bridge_main0_dbg_m_0_9_brperr1 pcie_noc.bridge_main0_dbg_m_0_9_brperr1 0xB1E0 0xB1E0 pcie_noc.bridge_main0_dbg_m_0_9_brperrm0 pcie_noc.bridge_main0_dbg_m_0_9_brperrm0 0xB1E8 0xB1E8 pcie_noc.bridge_main0_dbg_m_0_9_brperrm1 pcie_noc.bridge_main0_dbg_m_0_9_brperrm1 0xB1F0 0xBBFF 0xBC00 0xBC00 pcie_noc.bridge_main0_dbg_m_0_9_am_tocfg pcie_noc.bridge_main0_dbg_m_0_9_am_tocfg 0xBC08 0xBC08 pcie_noc.bridge_main0_dbg_m_0_9_am_osslv pcie_noc.bridge_main0_dbg_m_0_9_am_osslv 0xBC10 0xBC10 pcie_noc.bridge_main0_dbg_m_0_9_am_cgc pcie_noc.bridge_main0_dbg_m_0_9_am_cgc 0xBC18 0xBC18 pcie_noc.bridge_main0_dbg_m_0_9_am_cgo pcie_noc.bridge_main0_dbg_m_0_9_am_cgo 0xBC20 0xBC20 pcie_noc.bridge_main0_dbg_m_0_9_am_cfg pcie_noc.bridge_main0_dbg_m_0_9_am_cfg 0xBC28 0xBCFF 0xBD00 0xBD00 pcie_noc.bridge_main0_dbg_m_0_9_am_sts pcie_noc.bridge_main0_dbg_m_0_9_am_sts 0xBD08 0xBD08 pcie_noc.bridge_main0_dbg_m_0_9_am_bridge_id pcie_noc.bridge_main0_dbg_m_0_9_am_bridge_id 0xBD10 0xBDFF 0xBE00 0xBE00 pcie_noc.bridge_main0_dbg_m_0_9_am_err pcie_noc.bridge_main0_dbg_m_0_9_am_err 0xBE08 0xBE08 pcie_noc.bridge_main0_dbg_m_0_9_am_toslvid pcie_noc.bridge_main0_dbg_m_0_9_am_toslvid 0xBE10 0xBE10 pcie_noc.bridge_main0_dbg_m_0_9_am_era pcie_noc.bridge_main0_dbg_m_0_9_am_era 0xBE18 0xBE18 pcie_noc.bridge_main0_dbg_m_0_9_am_ewa pcie_noc.bridge_main0_dbg_m_0_9_am_ewa 0xBE20 0xBE3F 0xBE40 0xBE40 pcie_noc.bridge_main0_dbg_m_0_9_am_intm pcie_noc.bridge_main0_dbg_m_0_9_am_intm 0xBE48 0xBEFF 0xBF00 0xBF00 pcie_noc.bridge_main0_dbg_m_0_9_am_caddr pcie_noc.bridge_main0_dbg_m_0_9_am_caddr 0xBF08 0xBF08 pcie_noc.bridge_main0_dbg_m_0_9_am_caddrmsk pcie_noc.bridge_main0_dbg_m_0_9_am_caddrmsk 0xBF10 0xBF10 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd0 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd0 0xBF18 0xBF18 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk0 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk0 0xBF20 0xBF20 pcie_noc.bridge_main0_dbg_m_0_9_am_cntr0 pcie_noc.bridge_main0_dbg_m_0_9_am_cntr0 0xBF28 0xBF28 pcie_noc.bridge_main0_dbg_m_0_9_am_latnum0 pcie_noc.bridge_main0_dbg_m_0_9_am_latnum0 0xBF30 0xBF30 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd1 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd1 0xBF38 0xBF38 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk1 pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk1 0xBF40 0xBF40 pcie_noc.bridge_main0_dbg_m_0_9_am_cntr1 pcie_noc.bridge_main0_dbg_m_0_9_am_cntr1 0xBF48 0xBF48 pcie_noc.bridge_main0_dbg_m_0_9_am_latnum1 pcie_noc.bridge_main0_dbg_m_0_9_am_latnum1 0xBF50 0xBF5F 0xBF60 0xBF60 pcie_noc.bridge_main0_dbg_m_0_9_am_arovrd pcie_noc.bridge_main0_dbg_m_0_9_am_arovrd 0xBF68 0xBF68 pcie_noc.bridge_main0_dbg_m_0_9_am_awovrd pcie_noc.bridge_main0_dbg_m_0_9_am_awovrd 0xBF70 0xBFFF 0xC000 0xC000 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0xC008 0xC008 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0xC010 0xC01F 0xC020 0xC020 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0xC028 0xC028 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0xC030 0xC03F 0xC040 0xC040 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0xC048 0xC048 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0xC050 0xC05F 0xC060 0xC060 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0xC068 0xC068 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0xC070 0xC07F 0xC080 0xC080 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0xC088 0xC088 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0xC090 0xC09F 0xC0A0 0xC0A0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0xC0A8 0xC0A8 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0xC0B0 0xC0BF 0xC0C0 0xC0C0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0xC0C8 0xC0C8 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0xC0D0 0xC0DF 0xC0E0 0xC0E0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0xC0E8 0xC0E8 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0xC0F0 0xC0FF 0xC100 0xC100 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0xC108 0xC108 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0xC110 0xC11F 0xC120 0xC120 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0xC128 0xC128 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 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pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0xC408 0xC408 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0xC410 0xC41F 0xC420 0xC420 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0xC428 0xC428 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0xC430 0xC43F 0xC440 0xC440 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0xC448 0xC448 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0xC450 0xC45F 0xC460 0xC460 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0xC468 0xC468 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0xC470 0xC47F 0xC480 0xC480 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0xC488 0xC488 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0xC490 0xC49F 0xC4A0 0xC4A0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0xC4A8 0xC4A8 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0xC4B0 0xC4BF 0xC4C0 0xC4C0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0xC4C8 0xC4C8 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0xC4D0 0xC4DF 0xC4E0 0xC4E0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0xC4E8 0xC4E8 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0xC4F0 0xC4FF 0xC500 0xC500 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0xC508 0xC508 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0xC510 0xEFFF 0xF000 0xF000 pcie_noc.bridge_main0_esr_m_1_5_p_0 pcie_noc.bridge_main0_esr_m_1_5_p_0 0xF004 0xF007 0xF008 0xF008 pcie_noc.bridge_main0_esr_m_1_5_p_1 pcie_noc.bridge_main0_esr_m_1_5_p_1 0xF00C 0xF00F 0xF010 0xF010 pcie_noc.bridge_main0_esr_m_1_5_p_2 pcie_noc.bridge_main0_esr_m_1_5_p_2 0xF014 0xF017 0xF018 0xF018 pcie_noc.bridge_main0_esr_m_1_5_p_3 pcie_noc.bridge_main0_esr_m_1_5_p_3 0xF01C 0xF03F 0xF040 0xF040 pcie_noc.bridge_main0_esr_m_1_5_txe pcie_noc.bridge_main0_esr_m_1_5_txe 0xF044 0xF047 0xF048 0xF048 pcie_noc.bridge_main0_esr_m_1_5_txem pcie_noc.bridge_main0_esr_m_1_5_txem 0xF04C 0xF057 0xF058 0xF058 pcie_noc.bridge_main0_esr_m_1_5_btus_0 pcie_noc.bridge_main0_esr_m_1_5_btus_0 0xF05C 0xF05F 0xF060 0xF060 pcie_noc.bridge_main0_esr_m_1_5_btus_1 pcie_noc.bridge_main0_esr_m_1_5_btus_1 0xF064 0xF07F 0xF080 0xF080 pcie_noc.bridge_main0_esr_m_1_5_btrl_0 pcie_noc.bridge_main0_esr_m_1_5_btrl_0 0xF084 0xF087 0xF088 0xF088 pcie_noc.bridge_main0_esr_m_1_5_btrl_1 pcie_noc.bridge_main0_esr_m_1_5_btrl_1 0xF08C 0xF08F 0xF090 0xF090 pcie_noc.bridge_main0_esr_m_1_5_btrl_2 pcie_noc.bridge_main0_esr_m_1_5_btrl_2 0xF094 0xF097 0xF098 0xF098 pcie_noc.bridge_main0_esr_m_1_5_btrl_3 pcie_noc.bridge_main0_esr_m_1_5_btrl_3 0xF09C 0xF0A7 0xF0A8 0xF0A8 pcie_noc.bridge_main0_esr_m_1_5_btperr pcie_noc.bridge_main0_esr_m_1_5_btperr 0xF0AC 0xF0AF 0xF0B0 0xF0B0 pcie_noc.bridge_main0_esr_m_1_5_btperrm pcie_noc.bridge_main0_esr_m_1_5_btperrm 0xF0B4 0xF11F 0xF120 0xF120 pcie_noc.bridge_main0_esr_m_1_5_rxe pcie_noc.bridge_main0_esr_m_1_5_rxe 0xF124 0xF127 0xF128 0xF128 pcie_noc.bridge_main0_esr_m_1_5_rxem pcie_noc.bridge_main0_esr_m_1_5_rxem 0xF12C 0xF12F 0xF130 0xF130 pcie_noc.bridge_main0_esr_m_1_5_brs_0 pcie_noc.bridge_main0_esr_m_1_5_brs_0 0xF134 0xF137 0xF138 0xF138 pcie_noc.bridge_main0_esr_m_1_5_brs_1 pcie_noc.bridge_main0_esr_m_1_5_brs_1 0xF13C 0xF1AF 0xF1B0 0xF1B0 pcie_noc.bridge_main0_esr_m_1_5_brus pcie_noc.bridge_main0_esr_m_1_5_brus 0xF1B4 0xF1CF 0xF1D0 0xF1D0 pcie_noc.bridge_main0_esr_m_1_5_brperr0 pcie_noc.bridge_main0_esr_m_1_5_brperr0 0xF1D8 0xF1D8 pcie_noc.bridge_main0_esr_m_1_5_brperr1 pcie_noc.bridge_main0_esr_m_1_5_brperr1 0xF1E0 0xF1E0 pcie_noc.bridge_main0_esr_m_1_5_brperrm0 pcie_noc.bridge_main0_esr_m_1_5_brperrm0 0xF1E8 0xF1E8 pcie_noc.bridge_main0_esr_m_1_5_brperrm1 pcie_noc.bridge_main0_esr_m_1_5_brperrm1 0xF1F0 0xFBFF 0xFC00 0xFC00 pcie_noc.bridge_main0_esr_m_1_5_am_tocfg pcie_noc.bridge_main0_esr_m_1_5_am_tocfg 0xFC08 0xFC08 pcie_noc.bridge_main0_esr_m_1_5_am_osslv pcie_noc.bridge_main0_esr_m_1_5_am_osslv 0xFC10 0xFC10 pcie_noc.bridge_main0_esr_m_1_5_am_cgc pcie_noc.bridge_main0_esr_m_1_5_am_cgc 0xFC18 0xFC18 pcie_noc.bridge_main0_esr_m_1_5_am_cgo pcie_noc.bridge_main0_esr_m_1_5_am_cgo 0xFC20 0xFC20 pcie_noc.bridge_main0_esr_m_1_5_am_cfg pcie_noc.bridge_main0_esr_m_1_5_am_cfg 0xFC28 0xFCFF 0xFD00 0xFD00 pcie_noc.bridge_main0_esr_m_1_5_am_sts pcie_noc.bridge_main0_esr_m_1_5_am_sts 0xFD08 0xFD08 pcie_noc.bridge_main0_esr_m_1_5_am_bridge_id pcie_noc.bridge_main0_esr_m_1_5_am_bridge_id 0xFD10 0xFDFF 0xFE00 0xFE00 pcie_noc.bridge_main0_esr_m_1_5_am_err pcie_noc.bridge_main0_esr_m_1_5_am_err 0xFE08 0xFE08 pcie_noc.bridge_main0_esr_m_1_5_am_toslvid pcie_noc.bridge_main0_esr_m_1_5_am_toslvid 0xFE10 0xFE10 pcie_noc.bridge_main0_esr_m_1_5_am_era pcie_noc.bridge_main0_esr_m_1_5_am_era 0xFE18 0xFE18 pcie_noc.bridge_main0_esr_m_1_5_am_ewa pcie_noc.bridge_main0_esr_m_1_5_am_ewa 0xFE20 0xFE3F 0xFE40 0xFE40 pcie_noc.bridge_main0_esr_m_1_5_am_intm pcie_noc.bridge_main0_esr_m_1_5_am_intm 0xFE48 0xFEFF 0xFF00 0xFF00 pcie_noc.bridge_main0_esr_m_1_5_am_caddr pcie_noc.bridge_main0_esr_m_1_5_am_caddr 0xFF08 0xFF08 pcie_noc.bridge_main0_esr_m_1_5_am_caddrmsk pcie_noc.bridge_main0_esr_m_1_5_am_caddrmsk 0xFF10 0xFF10 pcie_noc.bridge_main0_esr_m_1_5_am_ccmd0 pcie_noc.bridge_main0_esr_m_1_5_am_ccmd0 0xFF18 0xFF18 pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk0 pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk0 0xFF20 0xFF20 pcie_noc.bridge_main0_esr_m_1_5_am_cntr0 pcie_noc.bridge_main0_esr_m_1_5_am_cntr0 0xFF28 0xFF28 pcie_noc.bridge_main0_esr_m_1_5_am_latnum0 pcie_noc.bridge_main0_esr_m_1_5_am_latnum0 0xFF30 0xFF30 pcie_noc.bridge_main0_esr_m_1_5_am_ccmd1 pcie_noc.bridge_main0_esr_m_1_5_am_ccmd1 0xFF38 0xFF38 pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk1 pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk1 0xFF40 0xFF40 pcie_noc.bridge_main0_esr_m_1_5_am_cntr1 pcie_noc.bridge_main0_esr_m_1_5_am_cntr1 0xFF48 0xFF48 pcie_noc.bridge_main0_esr_m_1_5_am_latnum1 pcie_noc.bridge_main0_esr_m_1_5_am_latnum1 0xFF50 0xFF5F 0xFF60 0xFF60 pcie_noc.bridge_main0_esr_m_1_5_am_arovrd pcie_noc.bridge_main0_esr_m_1_5_am_arovrd 0xFF68 0xFF68 pcie_noc.bridge_main0_esr_m_1_5_am_awovrd pcie_noc.bridge_main0_esr_m_1_5_am_awovrd 0xFF70 0xFFFF 0x10000 0x10000 pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x10008 0x10008 pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x10010 0x1001F 0x10020 0x10020 pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x10028 0x10028 pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x10030 0x10030 pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 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pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x1C3E8 0x1C3E8 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x1C3F0 0x1C3FF 0x1C400 0x1C400 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x1C408 0x1C408 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x1C410 0x1C41F 0x1C420 0x1C420 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x1C428 0x1C428 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x1C430 0x1C43F 0x1C440 0x1C440 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x1C448 0x1C448 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x1C450 0x1C45F 0x1C460 0x1C460 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x1C468 0x1C468 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x1C470 0x1C47F 0x1C480 0x1C480 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x1C488 0x1C488 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x1C490 0x1C49F 0x1C4A0 0x1C4A0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x1C4A8 0x1C4A8 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x1C4B0 0x1EFFF 0x1F000 0x1F000 pcie_noc.bridge_p0_p0_m_3_6_p_0 pcie_noc.bridge_p0_p0_m_3_6_p_0 0x1F004 0x1F007 0x1F008 0x1F008 pcie_noc.bridge_p0_p0_m_3_6_p_1 pcie_noc.bridge_p0_p0_m_3_6_p_1 0x1F00C 0x1F00F 0x1F010 0x1F010 pcie_noc.bridge_p0_p0_m_3_6_p_2 pcie_noc.bridge_p0_p0_m_3_6_p_2 0x1F014 0x1F017 0x1F018 0x1F018 pcie_noc.bridge_p0_p0_m_3_6_p_3 pcie_noc.bridge_p0_p0_m_3_6_p_3 0x1F01C 0x1F03F 0x1F040 0x1F040 pcie_noc.bridge_p0_p0_m_3_6_txe pcie_noc.bridge_p0_p0_m_3_6_txe 0x1F044 0x1F047 0x1F048 0x1F048 pcie_noc.bridge_p0_p0_m_3_6_txem pcie_noc.bridge_p0_p0_m_3_6_txem 0x1F04C 0x1F057 0x1F058 0x1F058 pcie_noc.bridge_p0_p0_m_3_6_btus_0 pcie_noc.bridge_p0_p0_m_3_6_btus_0 0x1F05C 0x1F05F 0x1F060 0x1F060 pcie_noc.bridge_p0_p0_m_3_6_btus_1 pcie_noc.bridge_p0_p0_m_3_6_btus_1 0x1F064 0x1F07F 0x1F080 0x1F080 pcie_noc.bridge_p0_p0_m_3_6_btrl_0 pcie_noc.bridge_p0_p0_m_3_6_btrl_0 0x1F084 0x1F087 0x1F088 0x1F088 pcie_noc.bridge_p0_p0_m_3_6_btrl_1 pcie_noc.bridge_p0_p0_m_3_6_btrl_1 0x1F08C 0x1F08F 0x1F090 0x1F090 pcie_noc.bridge_p0_p0_m_3_6_btrl_2 pcie_noc.bridge_p0_p0_m_3_6_btrl_2 0x1F094 0x1F097 0x1F098 0x1F098 pcie_noc.bridge_p0_p0_m_3_6_btrl_3 pcie_noc.bridge_p0_p0_m_3_6_btrl_3 0x1F09C 0x1F0A7 0x1F0A8 0x1F0A8 pcie_noc.bridge_p0_p0_m_3_6_btperr pcie_noc.bridge_p0_p0_m_3_6_btperr 0x1F0AC 0x1F0AF 0x1F0B0 0x1F0B0 pcie_noc.bridge_p0_p0_m_3_6_btperrm pcie_noc.bridge_p0_p0_m_3_6_btperrm 0x1F0B4 0x1F11F 0x1F120 0x1F120 pcie_noc.bridge_p0_p0_m_3_6_rxe pcie_noc.bridge_p0_p0_m_3_6_rxe 0x1F124 0x1F127 0x1F128 0x1F128 pcie_noc.bridge_p0_p0_m_3_6_rxem pcie_noc.bridge_p0_p0_m_3_6_rxem 0x1F12C 0x1F12F 0x1F130 0x1F130 pcie_noc.bridge_p0_p0_m_3_6_brs_0 pcie_noc.bridge_p0_p0_m_3_6_brs_0 0x1F134 0x1F137 0x1F138 0x1F138 pcie_noc.bridge_p0_p0_m_3_6_brs_1 pcie_noc.bridge_p0_p0_m_3_6_brs_1 0x1F13C 0x1F1AF 0x1F1B0 0x1F1B0 pcie_noc.bridge_p0_p0_m_3_6_brus pcie_noc.bridge_p0_p0_m_3_6_brus 0x1F1B4 0x1F1CF 0x1F1D0 0x1F1D0 pcie_noc.bridge_p0_p0_m_3_6_brperr0 pcie_noc.bridge_p0_p0_m_3_6_brperr0 0x1F1D8 0x1F1D8 pcie_noc.bridge_p0_p0_m_3_6_brperr1 pcie_noc.bridge_p0_p0_m_3_6_brperr1 0x1F1E0 0x1F1E0 pcie_noc.bridge_p0_p0_m_3_6_brperrm0 pcie_noc.bridge_p0_p0_m_3_6_brperrm0 0x1F1E8 0x1F1E8 pcie_noc.bridge_p0_p0_m_3_6_brperrm1 pcie_noc.bridge_p0_p0_m_3_6_brperrm1 0x1F1F0 0x1FBFF 0x1FC00 0x1FC00 pcie_noc.bridge_p0_p0_m_3_6_am_tocfg pcie_noc.bridge_p0_p0_m_3_6_am_tocfg 0x1FC08 0x1FC08 pcie_noc.bridge_p0_p0_m_3_6_am_osslv pcie_noc.bridge_p0_p0_m_3_6_am_osslv 0x1FC10 0x1FC10 pcie_noc.bridge_p0_p0_m_3_6_am_cgc pcie_noc.bridge_p0_p0_m_3_6_am_cgc 0x1FC18 0x1FC18 pcie_noc.bridge_p0_p0_m_3_6_am_cgo pcie_noc.bridge_p0_p0_m_3_6_am_cgo 0x1FC20 0x1FC20 pcie_noc.bridge_p0_p0_m_3_6_am_cfg pcie_noc.bridge_p0_p0_m_3_6_am_cfg 0x1FC28 0x1FCFF 0x1FD00 0x1FD00 pcie_noc.bridge_p0_p0_m_3_6_am_sts pcie_noc.bridge_p0_p0_m_3_6_am_sts 0x1FD08 0x1FD08 pcie_noc.bridge_p0_p0_m_3_6_am_bridge_id pcie_noc.bridge_p0_p0_m_3_6_am_bridge_id 0x1FD10 0x1FDFF 0x1FE00 0x1FE00 pcie_noc.bridge_p0_p0_m_3_6_am_err pcie_noc.bridge_p0_p0_m_3_6_am_err 0x1FE08 0x1FE08 pcie_noc.bridge_p0_p0_m_3_6_am_toslvid pcie_noc.bridge_p0_p0_m_3_6_am_toslvid 0x1FE10 0x1FE10 pcie_noc.bridge_p0_p0_m_3_6_am_era pcie_noc.bridge_p0_p0_m_3_6_am_era 0x1FE18 0x1FE18 pcie_noc.bridge_p0_p0_m_3_6_am_ewa pcie_noc.bridge_p0_p0_m_3_6_am_ewa 0x1FE20 0x1FE3F 0x1FE40 0x1FE40 pcie_noc.bridge_p0_p0_m_3_6_am_intm pcie_noc.bridge_p0_p0_m_3_6_am_intm 0x1FE48 0x1FEFF 0x1FF00 0x1FF00 pcie_noc.bridge_p0_p0_m_3_6_am_caddr pcie_noc.bridge_p0_p0_m_3_6_am_caddr 0x1FF08 0x1FF08 pcie_noc.bridge_p0_p0_m_3_6_am_caddrmsk pcie_noc.bridge_p0_p0_m_3_6_am_caddrmsk 0x1FF10 0x1FF10 pcie_noc.bridge_p0_p0_m_3_6_am_ccmd0 pcie_noc.bridge_p0_p0_m_3_6_am_ccmd0 0x1FF18 0x1FF18 pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk0 pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk0 0x1FF20 0x1FF20 pcie_noc.bridge_p0_p0_m_3_6_am_cntr0 pcie_noc.bridge_p0_p0_m_3_6_am_cntr0 0x1FF28 0x1FF28 pcie_noc.bridge_p0_p0_m_3_6_am_latnum0 pcie_noc.bridge_p0_p0_m_3_6_am_latnum0 0x1FF30 0x1FF30 pcie_noc.bridge_p0_p0_m_3_6_am_ccmd1 pcie_noc.bridge_p0_p0_m_3_6_am_ccmd1 0x1FF38 0x1FF38 pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk1 pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk1 0x1FF40 0x1FF40 pcie_noc.bridge_p0_p0_m_3_6_am_cntr1 pcie_noc.bridge_p0_p0_m_3_6_am_cntr1 0x1FF48 0x1FF48 pcie_noc.bridge_p0_p0_m_3_6_am_latnum1 pcie_noc.bridge_p0_p0_m_3_6_am_latnum1 0x1FF50 0x1FF5F 0x1FF60 0x1FF60 pcie_noc.bridge_p0_p0_m_3_6_am_arovrd pcie_noc.bridge_p0_p0_m_3_6_am_arovrd 0x1FF68 0x1FF68 pcie_noc.bridge_p0_p0_m_3_6_am_awovrd pcie_noc.bridge_p0_p0_m_3_6_am_awovrd 0x1FF70 0x21C0F 0x21C10 0x21C10 pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgc pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgc 0x21C18 0x21C18 pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgo pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgo 0x21C20 0x21CFF 0x21D00 0x21D00 pcie_noc.bridge_p0_p0_reg_s_9_6_as_sts pcie_noc.bridge_p0_p0_reg_s_9_6_as_sts 0x21D08 0x21D08 pcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_id pcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_id 0x21D10 0x21DFF 0x21E00 0x21E00 pcie_noc.bridge_p0_p0_reg_s_9_6_as_err pcie_noc.bridge_p0_p0_reg_s_9_6_as_err 0x21E08 0x21E3F 0x21E40 0x21E40 pcie_noc.bridge_p0_p0_reg_s_9_6_as_intm pcie_noc.bridge_p0_p0_reg_s_9_6_as_intm 0x21E48 0x21EFF 0x21F00 0x21F00 pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmd pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmd 0x21F08 0x21F08 pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmsk pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmsk 0x21F10 0x21F10 pcie_noc.bridge_p0_p0_reg_s_9_6_as_cntr pcie_noc.bridge_p0_p0_reg_s_9_6_as_cntr 0x21F18 0x21F18 pcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrd pcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrd 0x21F20 0x21F20 pcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrd pcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrd 0x21F28 0x22FFF 0x23000 0x23000 pcie_noc.bridge_p0_p0_reg_s_9_6_p_0 pcie_noc.bridge_p0_p0_reg_s_9_6_p_0 0x23004 0x23007 0x23008 0x23008 pcie_noc.bridge_p0_p0_reg_s_9_6_p_1 pcie_noc.bridge_p0_p0_reg_s_9_6_p_1 0x2300C 0x2300F 0x23010 0x23010 pcie_noc.bridge_p0_p0_reg_s_9_6_p_2 pcie_noc.bridge_p0_p0_reg_s_9_6_p_2 0x23014 0x23017 0x23018 0x23018 pcie_noc.bridge_p0_p0_reg_s_9_6_p_3 pcie_noc.bridge_p0_p0_reg_s_9_6_p_3 0x2301C 0x2303F 0x23040 0x23040 pcie_noc.bridge_p0_p0_reg_s_9_6_txe pcie_noc.bridge_p0_p0_reg_s_9_6_txe 0x23044 0x23047 0x23048 0x23048 pcie_noc.bridge_p0_p0_reg_s_9_6_txem pcie_noc.bridge_p0_p0_reg_s_9_6_txem 0x2304C 0x23057 0x23058 0x23058 pcie_noc.bridge_p0_p0_reg_s_9_6_btus_0 pcie_noc.bridge_p0_p0_reg_s_9_6_btus_0 0x2305C 0x2305F 0x23060 0x23060 pcie_noc.bridge_p0_p0_reg_s_9_6_btus_1 pcie_noc.bridge_p0_p0_reg_s_9_6_btus_1 0x23064 0x2307F 0x23080 0x23080 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_0 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_0 0x23084 0x23087 0x23088 0x23088 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_1 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_1 0x2308C 0x2308F 0x23090 0x23090 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_2 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_2 0x23094 0x23097 0x23098 0x23098 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_3 pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_3 0x2309C 0x230A7 0x230A8 0x230A8 pcie_noc.bridge_p0_p0_reg_s_9_6_btperr pcie_noc.bridge_p0_p0_reg_s_9_6_btperr 0x230AC 0x230AF 0x230B0 0x230B0 pcie_noc.bridge_p0_p0_reg_s_9_6_btperrm pcie_noc.bridge_p0_p0_reg_s_9_6_btperrm 0x230B4 0x2311F 0x23120 0x23120 pcie_noc.bridge_p0_p0_reg_s_9_6_rxe pcie_noc.bridge_p0_p0_reg_s_9_6_rxe 0x23124 0x23127 0x23128 0x23128 pcie_noc.bridge_p0_p0_reg_s_9_6_rxem pcie_noc.bridge_p0_p0_reg_s_9_6_rxem 0x2312C 0x2312F 0x23130 0x23130 pcie_noc.bridge_p0_p0_reg_s_9_6_brs_0 pcie_noc.bridge_p0_p0_reg_s_9_6_brs_0 0x23134 0x23137 0x23138 0x23138 pcie_noc.bridge_p0_p0_reg_s_9_6_brs_1 pcie_noc.bridge_p0_p0_reg_s_9_6_brs_1 0x2313C 0x231AF 0x231B0 0x231B0 pcie_noc.bridge_p0_p0_reg_s_9_6_brus pcie_noc.bridge_p0_p0_reg_s_9_6_brus 0x231B4 0x231CF 0x231D0 0x231D0 pcie_noc.bridge_p0_p0_reg_s_9_6_brperr0 pcie_noc.bridge_p0_p0_reg_s_9_6_brperr0 0x231D8 0x231D8 pcie_noc.bridge_p0_p0_reg_s_9_6_brperr1 pcie_noc.bridge_p0_p0_reg_s_9_6_brperr1 0x231E0 0x231E0 pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm0 pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm0 0x231E8 0x231E8 pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm1 pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm1 0x231F0 0x25C0F 0x25C10 0x25C10 pcie_noc.bridge_p0_p0_s_10_7_as_cgc pcie_noc.bridge_p0_p0_s_10_7_as_cgc 0x25C18 0x25C18 pcie_noc.bridge_p0_p0_s_10_7_as_cgo pcie_noc.bridge_p0_p0_s_10_7_as_cgo 0x25C20 0x25CFF 0x25D00 0x25D00 pcie_noc.bridge_p0_p0_s_10_7_as_sts pcie_noc.bridge_p0_p0_s_10_7_as_sts 0x25D08 0x25D08 pcie_noc.bridge_p0_p0_s_10_7_as_bridge_id pcie_noc.bridge_p0_p0_s_10_7_as_bridge_id 0x25D10 0x25DFF 0x25E00 0x25E00 pcie_noc.bridge_p0_p0_s_10_7_as_err pcie_noc.bridge_p0_p0_s_10_7_as_err 0x25E08 0x25E3F 0x25E40 0x25E40 pcie_noc.bridge_p0_p0_s_10_7_as_intm pcie_noc.bridge_p0_p0_s_10_7_as_intm 0x25E48 0x25EFF 0x25F00 0x25F00 pcie_noc.bridge_p0_p0_s_10_7_as_ccmd pcie_noc.bridge_p0_p0_s_10_7_as_ccmd 0x25F08 0x25F08 pcie_noc.bridge_p0_p0_s_10_7_as_ccmdmsk pcie_noc.bridge_p0_p0_s_10_7_as_ccmdmsk 0x25F10 0x25F10 pcie_noc.bridge_p0_p0_s_10_7_as_cntr pcie_noc.bridge_p0_p0_s_10_7_as_cntr 0x25F18 0x25F18 pcie_noc.bridge_p0_p0_s_10_7_as_arovrd pcie_noc.bridge_p0_p0_s_10_7_as_arovrd 0x25F20 0x25F20 pcie_noc.bridge_p0_p0_s_10_7_as_awovrd pcie_noc.bridge_p0_p0_s_10_7_as_awovrd 0x25F28 0x26FFF 0x27000 0x27000 pcie_noc.bridge_p0_p0_s_10_7_p_0 pcie_noc.bridge_p0_p0_s_10_7_p_0 0x27004 0x27007 0x27008 0x27008 pcie_noc.bridge_p0_p0_s_10_7_p_1 pcie_noc.bridge_p0_p0_s_10_7_p_1 0x2700C 0x2700F 0x27010 0x27010 pcie_noc.bridge_p0_p0_s_10_7_p_2 pcie_noc.bridge_p0_p0_s_10_7_p_2 0x27014 0x27017 0x27018 0x27018 pcie_noc.bridge_p0_p0_s_10_7_p_3 pcie_noc.bridge_p0_p0_s_10_7_p_3 0x2701C 0x2703F 0x27040 0x27040 pcie_noc.bridge_p0_p0_s_10_7_txe pcie_noc.bridge_p0_p0_s_10_7_txe 0x27044 0x27047 0x27048 0x27048 pcie_noc.bridge_p0_p0_s_10_7_txem pcie_noc.bridge_p0_p0_s_10_7_txem 0x2704C 0x27057 0x27058 0x27058 pcie_noc.bridge_p0_p0_s_10_7_btus_0 pcie_noc.bridge_p0_p0_s_10_7_btus_0 0x2705C 0x2705F 0x27060 0x27060 pcie_noc.bridge_p0_p0_s_10_7_btus_1 pcie_noc.bridge_p0_p0_s_10_7_btus_1 0x27064 0x2707F 0x27080 0x27080 pcie_noc.bridge_p0_p0_s_10_7_btrl_0 pcie_noc.bridge_p0_p0_s_10_7_btrl_0 0x27084 0x27087 0x27088 0x27088 pcie_noc.bridge_p0_p0_s_10_7_btrl_1 pcie_noc.bridge_p0_p0_s_10_7_btrl_1 0x2708C 0x2708F 0x27090 0x27090 pcie_noc.bridge_p0_p0_s_10_7_btrl_2 pcie_noc.bridge_p0_p0_s_10_7_btrl_2 0x27094 0x27097 0x27098 0x27098 pcie_noc.bridge_p0_p0_s_10_7_btrl_3 pcie_noc.bridge_p0_p0_s_10_7_btrl_3 0x2709C 0x270A7 0x270A8 0x270A8 pcie_noc.bridge_p0_p0_s_10_7_btperr pcie_noc.bridge_p0_p0_s_10_7_btperr 0x270AC 0x270AF 0x270B0 0x270B0 pcie_noc.bridge_p0_p0_s_10_7_btperrm pcie_noc.bridge_p0_p0_s_10_7_btperrm 0x270B4 0x2711F 0x27120 0x27120 pcie_noc.bridge_p0_p0_s_10_7_rxe pcie_noc.bridge_p0_p0_s_10_7_rxe 0x27124 0x27127 0x27128 0x27128 pcie_noc.bridge_p0_p0_s_10_7_rxem pcie_noc.bridge_p0_p0_s_10_7_rxem 0x2712C 0x2712F 0x27130 0x27130 pcie_noc.bridge_p0_p0_s_10_7_brs_0 pcie_noc.bridge_p0_p0_s_10_7_brs_0 0x27134 0x27137 0x27138 0x27138 pcie_noc.bridge_p0_p0_s_10_7_brs_1 pcie_noc.bridge_p0_p0_s_10_7_brs_1 0x2713C 0x271AF 0x271B0 0x271B0 pcie_noc.bridge_p0_p0_s_10_7_brus pcie_noc.bridge_p0_p0_s_10_7_brus 0x271B4 0x271CF 0x271D0 0x271D0 pcie_noc.bridge_p0_p0_s_10_7_brperr0 pcie_noc.bridge_p0_p0_s_10_7_brperr0 0x271D8 0x271D8 pcie_noc.bridge_p0_p0_s_10_7_brperr1 pcie_noc.bridge_p0_p0_s_10_7_brperr1 0x271E0 0x271E0 pcie_noc.bridge_p0_p0_s_10_7_brperrm0 pcie_noc.bridge_p0_p0_s_10_7_brperrm0 0x271E8 0x271E8 pcie_noc.bridge_p0_p0_s_10_7_brperrm1 pcie_noc.bridge_p0_p0_s_10_7_brperrm1 0x271F0 0x27FFF 0x28000 0x28000 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x28008 0x28008 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x28010 0x2801F 0x28020 0x28020 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x28028 0x28028 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x28030 0x28030 pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x28038 0x2803F 0x28040 0x28040 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x28048 0x28048 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x28050 0x28050 pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x28058 0x2805F 0x28060 0x28060 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x28068 0x28068 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x28070 0x2807F 0x28080 0x28080 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x28088 0x28088 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x28090 0x2809F 0x280A0 0x280A0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x280A8 0x280A8 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x280B0 0x280BF 0x280C0 0x280C0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x280C8 0x280C8 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x280D0 0x280DF 0x280E0 0x280E0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x280E8 0x280E8 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x280F0 0x280FF 0x28100 0x28100 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x28108 0x28108 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x28110 0x2811F 0x28120 0x28120 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x28128 0x28128 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x28130 0x2813F 0x28140 0x28140 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x28148 0x28148 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x28150 0x2815F 0x28160 0x28160 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x28168 0x28168 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 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pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x28450 0x2845F 0x28460 0x28460 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x28468 0x28468 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x28470 0x2847F 0x28480 0x28480 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x28488 0x28488 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x28490 0x2849F 0x284A0 0x284A0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x284A8 0x284A8 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x284B0 0x2AFFF 0x2B000 0x2B000 pcie_noc.bridge_p0_p1_m_4_6_p_0 pcie_noc.bridge_p0_p1_m_4_6_p_0 0x2B004 0x2B007 0x2B008 0x2B008 pcie_noc.bridge_p0_p1_m_4_6_p_1 pcie_noc.bridge_p0_p1_m_4_6_p_1 0x2B00C 0x2B00F 0x2B010 0x2B010 pcie_noc.bridge_p0_p1_m_4_6_p_2 pcie_noc.bridge_p0_p1_m_4_6_p_2 0x2B014 0x2B017 0x2B018 0x2B018 pcie_noc.bridge_p0_p1_m_4_6_p_3 pcie_noc.bridge_p0_p1_m_4_6_p_3 0x2B01C 0x2B03F 0x2B040 0x2B040 pcie_noc.bridge_p0_p1_m_4_6_txe pcie_noc.bridge_p0_p1_m_4_6_txe 0x2B044 0x2B047 0x2B048 0x2B048 pcie_noc.bridge_p0_p1_m_4_6_txem pcie_noc.bridge_p0_p1_m_4_6_txem 0x2B04C 0x2B057 0x2B058 0x2B058 pcie_noc.bridge_p0_p1_m_4_6_btus_0 pcie_noc.bridge_p0_p1_m_4_6_btus_0 0x2B05C 0x2B05F 0x2B060 0x2B060 pcie_noc.bridge_p0_p1_m_4_6_btus_1 pcie_noc.bridge_p0_p1_m_4_6_btus_1 0x2B064 0x2B07F 0x2B080 0x2B080 pcie_noc.bridge_p0_p1_m_4_6_btrl_0 pcie_noc.bridge_p0_p1_m_4_6_btrl_0 0x2B084 0x2B087 0x2B088 0x2B088 pcie_noc.bridge_p0_p1_m_4_6_btrl_1 pcie_noc.bridge_p0_p1_m_4_6_btrl_1 0x2B08C 0x2B08F 0x2B090 0x2B090 pcie_noc.bridge_p0_p1_m_4_6_btrl_2 pcie_noc.bridge_p0_p1_m_4_6_btrl_2 0x2B094 0x2B097 0x2B098 0x2B098 pcie_noc.bridge_p0_p1_m_4_6_btrl_3 pcie_noc.bridge_p0_p1_m_4_6_btrl_3 0x2B09C 0x2B0A7 0x2B0A8 0x2B0A8 pcie_noc.bridge_p0_p1_m_4_6_btperr pcie_noc.bridge_p0_p1_m_4_6_btperr 0x2B0AC 0x2B0AF 0x2B0B0 0x2B0B0 pcie_noc.bridge_p0_p1_m_4_6_btperrm pcie_noc.bridge_p0_p1_m_4_6_btperrm 0x2B0B4 0x2B11F 0x2B120 0x2B120 pcie_noc.bridge_p0_p1_m_4_6_rxe pcie_noc.bridge_p0_p1_m_4_6_rxe 0x2B124 0x2B127 0x2B128 0x2B128 pcie_noc.bridge_p0_p1_m_4_6_rxem pcie_noc.bridge_p0_p1_m_4_6_rxem 0x2B12C 0x2B12F 0x2B130 0x2B130 pcie_noc.bridge_p0_p1_m_4_6_brs_0 pcie_noc.bridge_p0_p1_m_4_6_brs_0 0x2B134 0x2B137 0x2B138 0x2B138 pcie_noc.bridge_p0_p1_m_4_6_brs_1 pcie_noc.bridge_p0_p1_m_4_6_brs_1 0x2B13C 0x2B1AF 0x2B1B0 0x2B1B0 pcie_noc.bridge_p0_p1_m_4_6_brus pcie_noc.bridge_p0_p1_m_4_6_brus 0x2B1B4 0x2B1CF 0x2B1D0 0x2B1D0 pcie_noc.bridge_p0_p1_m_4_6_brperr0 pcie_noc.bridge_p0_p1_m_4_6_brperr0 0x2B1D8 0x2B1D8 pcie_noc.bridge_p0_p1_m_4_6_brperr1 pcie_noc.bridge_p0_p1_m_4_6_brperr1 0x2B1E0 0x2B1E0 pcie_noc.bridge_p0_p1_m_4_6_brperrm0 pcie_noc.bridge_p0_p1_m_4_6_brperrm0 0x2B1E8 0x2B1E8 pcie_noc.bridge_p0_p1_m_4_6_brperrm1 pcie_noc.bridge_p0_p1_m_4_6_brperrm1 0x2B1F0 0x2BBFF 0x2BC00 0x2BC00 pcie_noc.bridge_p0_p1_m_4_6_am_tocfg pcie_noc.bridge_p0_p1_m_4_6_am_tocfg 0x2BC08 0x2BC08 pcie_noc.bridge_p0_p1_m_4_6_am_osslv pcie_noc.bridge_p0_p1_m_4_6_am_osslv 0x2BC10 0x2BC10 pcie_noc.bridge_p0_p1_m_4_6_am_cgc pcie_noc.bridge_p0_p1_m_4_6_am_cgc 0x2BC18 0x2BC18 pcie_noc.bridge_p0_p1_m_4_6_am_cgo pcie_noc.bridge_p0_p1_m_4_6_am_cgo 0x2BC20 0x2BC20 pcie_noc.bridge_p0_p1_m_4_6_am_cfg pcie_noc.bridge_p0_p1_m_4_6_am_cfg 0x2BC28 0x2BCFF 0x2BD00 0x2BD00 pcie_noc.bridge_p0_p1_m_4_6_am_sts pcie_noc.bridge_p0_p1_m_4_6_am_sts 0x2BD08 0x2BD08 pcie_noc.bridge_p0_p1_m_4_6_am_bridge_id pcie_noc.bridge_p0_p1_m_4_6_am_bridge_id 0x2BD10 0x2BDFF 0x2BE00 0x2BE00 pcie_noc.bridge_p0_p1_m_4_6_am_err pcie_noc.bridge_p0_p1_m_4_6_am_err 0x2BE08 0x2BE08 pcie_noc.bridge_p0_p1_m_4_6_am_toslvid pcie_noc.bridge_p0_p1_m_4_6_am_toslvid 0x2BE10 0x2BE10 pcie_noc.bridge_p0_p1_m_4_6_am_era pcie_noc.bridge_p0_p1_m_4_6_am_era 0x2BE18 0x2BE18 pcie_noc.bridge_p0_p1_m_4_6_am_ewa pcie_noc.bridge_p0_p1_m_4_6_am_ewa 0x2BE20 0x2BE3F 0x2BE40 0x2BE40 pcie_noc.bridge_p0_p1_m_4_6_am_intm pcie_noc.bridge_p0_p1_m_4_6_am_intm 0x2BE48 0x2BEFF 0x2BF00 0x2BF00 pcie_noc.bridge_p0_p1_m_4_6_am_caddr pcie_noc.bridge_p0_p1_m_4_6_am_caddr 0x2BF08 0x2BF08 pcie_noc.bridge_p0_p1_m_4_6_am_caddrmsk pcie_noc.bridge_p0_p1_m_4_6_am_caddrmsk 0x2BF10 0x2BF10 pcie_noc.bridge_p0_p1_m_4_6_am_ccmd0 pcie_noc.bridge_p0_p1_m_4_6_am_ccmd0 0x2BF18 0x2BF18 pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk0 pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk0 0x2BF20 0x2BF20 pcie_noc.bridge_p0_p1_m_4_6_am_cntr0 pcie_noc.bridge_p0_p1_m_4_6_am_cntr0 0x2BF28 0x2BF28 pcie_noc.bridge_p0_p1_m_4_6_am_latnum0 pcie_noc.bridge_p0_p1_m_4_6_am_latnum0 0x2BF30 0x2BF30 pcie_noc.bridge_p0_p1_m_4_6_am_ccmd1 pcie_noc.bridge_p0_p1_m_4_6_am_ccmd1 0x2BF38 0x2BF38 pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk1 pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk1 0x2BF40 0x2BF40 pcie_noc.bridge_p0_p1_m_4_6_am_cntr1 pcie_noc.bridge_p0_p1_m_4_6_am_cntr1 0x2BF48 0x2BF48 pcie_noc.bridge_p0_p1_m_4_6_am_latnum1 pcie_noc.bridge_p0_p1_m_4_6_am_latnum1 0x2BF50 0x2BF5F 0x2BF60 0x2BF60 pcie_noc.bridge_p0_p1_m_4_6_am_arovrd pcie_noc.bridge_p0_p1_m_4_6_am_arovrd 0x2BF68 0x2BF68 pcie_noc.bridge_p0_p1_m_4_6_am_awovrd pcie_noc.bridge_p0_p1_m_4_6_am_awovrd 0x2BF70 0x2DC0F 0x2DC10 0x2DC10 pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgc pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgc 0x2DC18 0x2DC18 pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgo pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgo 0x2DC20 0x2DCFF 0x2DD00 0x2DD00 pcie_noc.bridge_p0_p1_reg_s_11_6_as_sts pcie_noc.bridge_p0_p1_reg_s_11_6_as_sts 0x2DD08 0x2DD08 pcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_id pcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_id 0x2DD10 0x2DDFF 0x2DE00 0x2DE00 pcie_noc.bridge_p0_p1_reg_s_11_6_as_err pcie_noc.bridge_p0_p1_reg_s_11_6_as_err 0x2DE08 0x2DE3F 0x2DE40 0x2DE40 pcie_noc.bridge_p0_p1_reg_s_11_6_as_intm pcie_noc.bridge_p0_p1_reg_s_11_6_as_intm 0x2DE48 0x2DEFF 0x2DF00 0x2DF00 pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmd pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmd 0x2DF08 0x2DF08 pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmsk pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmsk 0x2DF10 0x2DF10 pcie_noc.bridge_p0_p1_reg_s_11_6_as_cntr pcie_noc.bridge_p0_p1_reg_s_11_6_as_cntr 0x2DF18 0x2DF18 pcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrd pcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrd 0x2DF20 0x2DF20 pcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrd pcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrd 0x2DF28 0x2EFFF 0x2F000 0x2F000 pcie_noc.bridge_p0_p1_reg_s_11_6_p_0 pcie_noc.bridge_p0_p1_reg_s_11_6_p_0 0x2F004 0x2F007 0x2F008 0x2F008 pcie_noc.bridge_p0_p1_reg_s_11_6_p_1 pcie_noc.bridge_p0_p1_reg_s_11_6_p_1 0x2F00C 0x2F00F 0x2F010 0x2F010 pcie_noc.bridge_p0_p1_reg_s_11_6_p_2 pcie_noc.bridge_p0_p1_reg_s_11_6_p_2 0x2F014 0x2F017 0x2F018 0x2F018 pcie_noc.bridge_p0_p1_reg_s_11_6_p_3 pcie_noc.bridge_p0_p1_reg_s_11_6_p_3 0x2F01C 0x2F03F 0x2F040 0x2F040 pcie_noc.bridge_p0_p1_reg_s_11_6_txe pcie_noc.bridge_p0_p1_reg_s_11_6_txe 0x2F044 0x2F047 0x2F048 0x2F048 pcie_noc.bridge_p0_p1_reg_s_11_6_txem pcie_noc.bridge_p0_p1_reg_s_11_6_txem 0x2F04C 0x2F057 0x2F058 0x2F058 pcie_noc.bridge_p0_p1_reg_s_11_6_btus_0 pcie_noc.bridge_p0_p1_reg_s_11_6_btus_0 0x2F05C 0x2F05F 0x2F060 0x2F060 pcie_noc.bridge_p0_p1_reg_s_11_6_btus_1 pcie_noc.bridge_p0_p1_reg_s_11_6_btus_1 0x2F064 0x2F07F 0x2F080 0x2F080 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_0 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_0 0x2F084 0x2F087 0x2F088 0x2F088 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_1 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_1 0x2F08C 0x2F08F 0x2F090 0x2F090 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_2 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_2 0x2F094 0x2F097 0x2F098 0x2F098 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_3 pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_3 0x2F09C 0x2F0A7 0x2F0A8 0x2F0A8 pcie_noc.bridge_p0_p1_reg_s_11_6_btperr pcie_noc.bridge_p0_p1_reg_s_11_6_btperr 0x2F0AC 0x2F0AF 0x2F0B0 0x2F0B0 pcie_noc.bridge_p0_p1_reg_s_11_6_btperrm pcie_noc.bridge_p0_p1_reg_s_11_6_btperrm 0x2F0B4 0x2F11F 0x2F120 0x2F120 pcie_noc.bridge_p0_p1_reg_s_11_6_rxe pcie_noc.bridge_p0_p1_reg_s_11_6_rxe 0x2F124 0x2F127 0x2F128 0x2F128 pcie_noc.bridge_p0_p1_reg_s_11_6_rxem pcie_noc.bridge_p0_p1_reg_s_11_6_rxem 0x2F12C 0x2F12F 0x2F130 0x2F130 pcie_noc.bridge_p0_p1_reg_s_11_6_brs_0 pcie_noc.bridge_p0_p1_reg_s_11_6_brs_0 0x2F134 0x2F137 0x2F138 0x2F138 pcie_noc.bridge_p0_p1_reg_s_11_6_brs_1 pcie_noc.bridge_p0_p1_reg_s_11_6_brs_1 0x2F13C 0x2F1AF 0x2F1B0 0x2F1B0 pcie_noc.bridge_p0_p1_reg_s_11_6_brus pcie_noc.bridge_p0_p1_reg_s_11_6_brus 0x2F1B4 0x2F1CF 0x2F1D0 0x2F1D0 pcie_noc.bridge_p0_p1_reg_s_11_6_brperr0 pcie_noc.bridge_p0_p1_reg_s_11_6_brperr0 0x2F1D8 0x2F1D8 pcie_noc.bridge_p0_p1_reg_s_11_6_brperr1 pcie_noc.bridge_p0_p1_reg_s_11_6_brperr1 0x2F1E0 0x2F1E0 pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm0 pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm0 0x2F1E8 0x2F1E8 pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm1 pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm1 0x2F1F0 0x31C0F 0x31C10 0x31C10 pcie_noc.bridge_p0_p1_s_12_10_as_cgc pcie_noc.bridge_p0_p1_s_12_10_as_cgc 0x31C18 0x31C18 pcie_noc.bridge_p0_p1_s_12_10_as_cgo pcie_noc.bridge_p0_p1_s_12_10_as_cgo 0x31C20 0x31CFF 0x31D00 0x31D00 pcie_noc.bridge_p0_p1_s_12_10_as_sts pcie_noc.bridge_p0_p1_s_12_10_as_sts 0x31D08 0x31D08 pcie_noc.bridge_p0_p1_s_12_10_as_bridge_id pcie_noc.bridge_p0_p1_s_12_10_as_bridge_id 0x31D10 0x31DFF 0x31E00 0x31E00 pcie_noc.bridge_p0_p1_s_12_10_as_err pcie_noc.bridge_p0_p1_s_12_10_as_err 0x31E08 0x31E3F 0x31E40 0x31E40 pcie_noc.bridge_p0_p1_s_12_10_as_intm pcie_noc.bridge_p0_p1_s_12_10_as_intm 0x31E48 0x31EFF 0x31F00 0x31F00 pcie_noc.bridge_p0_p1_s_12_10_as_ccmd pcie_noc.bridge_p0_p1_s_12_10_as_ccmd 0x31F08 0x31F08 pcie_noc.bridge_p0_p1_s_12_10_as_ccmdmsk pcie_noc.bridge_p0_p1_s_12_10_as_ccmdmsk 0x31F10 0x31F10 pcie_noc.bridge_p0_p1_s_12_10_as_cntr pcie_noc.bridge_p0_p1_s_12_10_as_cntr 0x31F18 0x31F18 pcie_noc.bridge_p0_p1_s_12_10_as_arovrd pcie_noc.bridge_p0_p1_s_12_10_as_arovrd 0x31F20 0x31F20 pcie_noc.bridge_p0_p1_s_12_10_as_awovrd pcie_noc.bridge_p0_p1_s_12_10_as_awovrd 0x31F28 0x32FFF 0x33000 0x33000 pcie_noc.bridge_p0_p1_s_12_10_p_0 pcie_noc.bridge_p0_p1_s_12_10_p_0 0x33004 0x33007 0x33008 0x33008 pcie_noc.bridge_p0_p1_s_12_10_p_1 pcie_noc.bridge_p0_p1_s_12_10_p_1 0x3300C 0x3300F 0x33010 0x33010 pcie_noc.bridge_p0_p1_s_12_10_p_2 pcie_noc.bridge_p0_p1_s_12_10_p_2 0x33014 0x33017 0x33018 0x33018 pcie_noc.bridge_p0_p1_s_12_10_p_3 pcie_noc.bridge_p0_p1_s_12_10_p_3 0x3301C 0x3303F 0x33040 0x33040 pcie_noc.bridge_p0_p1_s_12_10_txe pcie_noc.bridge_p0_p1_s_12_10_txe 0x33044 0x33047 0x33048 0x33048 pcie_noc.bridge_p0_p1_s_12_10_txem pcie_noc.bridge_p0_p1_s_12_10_txem 0x3304C 0x33057 0x33058 0x33058 pcie_noc.bridge_p0_p1_s_12_10_btus_0 pcie_noc.bridge_p0_p1_s_12_10_btus_0 0x3305C 0x3305F 0x33060 0x33060 pcie_noc.bridge_p0_p1_s_12_10_btus_1 pcie_noc.bridge_p0_p1_s_12_10_btus_1 0x33064 0x3307F 0x33080 0x33080 pcie_noc.bridge_p0_p1_s_12_10_btrl_0 pcie_noc.bridge_p0_p1_s_12_10_btrl_0 0x33084 0x33087 0x33088 0x33088 pcie_noc.bridge_p0_p1_s_12_10_btrl_1 pcie_noc.bridge_p0_p1_s_12_10_btrl_1 0x3308C 0x3308F 0x33090 0x33090 pcie_noc.bridge_p0_p1_s_12_10_btrl_2 pcie_noc.bridge_p0_p1_s_12_10_btrl_2 0x33094 0x33097 0x33098 0x33098 pcie_noc.bridge_p0_p1_s_12_10_btrl_3 pcie_noc.bridge_p0_p1_s_12_10_btrl_3 0x3309C 0x330A7 0x330A8 0x330A8 pcie_noc.bridge_p0_p1_s_12_10_btperr pcie_noc.bridge_p0_p1_s_12_10_btperr 0x330AC 0x330AF 0x330B0 0x330B0 pcie_noc.bridge_p0_p1_s_12_10_btperrm pcie_noc.bridge_p0_p1_s_12_10_btperrm 0x330B4 0x3311F 0x33120 0x33120 pcie_noc.bridge_p0_p1_s_12_10_rxe pcie_noc.bridge_p0_p1_s_12_10_rxe 0x33124 0x33127 0x33128 0x33128 pcie_noc.bridge_p0_p1_s_12_10_rxem pcie_noc.bridge_p0_p1_s_12_10_rxem 0x3312C 0x3312F 0x33130 0x33130 pcie_noc.bridge_p0_p1_s_12_10_brs_0 pcie_noc.bridge_p0_p1_s_12_10_brs_0 0x33134 0x33137 0x33138 0x33138 pcie_noc.bridge_p0_p1_s_12_10_brs_1 pcie_noc.bridge_p0_p1_s_12_10_brs_1 0x3313C 0x331AF 0x331B0 0x331B0 pcie_noc.bridge_p0_p1_s_12_10_brus pcie_noc.bridge_p0_p1_s_12_10_brus 0x331B4 0x331CF 0x331D0 0x331D0 pcie_noc.bridge_p0_p1_s_12_10_brperr0 pcie_noc.bridge_p0_p1_s_12_10_brperr0 0x331D8 0x331D8 pcie_noc.bridge_p0_p1_s_12_10_brperr1 pcie_noc.bridge_p0_p1_s_12_10_brperr1 0x331E0 0x331E0 pcie_noc.bridge_p0_p1_s_12_10_brperrm0 pcie_noc.bridge_p0_p1_s_12_10_brperrm0 0x331E8 0x331E8 pcie_noc.bridge_p0_p1_s_12_10_brperrm1 pcie_noc.bridge_p0_p1_s_12_10_brperrm1 0x331F0 0x33FFF 0x34000 0x34000 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x34008 0x34008 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x34010 0x3401F 0x34020 0x34020 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 0x34028 0x34028 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 0x34030 0x3403F 0x34040 0x34040 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 0x34048 0x34048 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 0x34050 0x3405F 0x34060 0x34060 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x34068 0x34068 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x34070 0x34070 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x34078 0x3407F 0x34080 0x34080 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x34088 0x34088 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x34090 0x34090 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x34098 0x3409F 0x340A0 0x340A0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x340A8 0x340A8 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x340B0 0x340B0 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x340B8 0x340BF 0x340C0 0x340C0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x340C8 0x340C8 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x340D0 0x340DF 0x340E0 0x340E0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x340E8 0x340E8 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x340F0 0x340F0 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x340F8 0x340FF 0x34100 0x34100 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x34108 0x34108 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x34110 0x3411F 0x34120 0x34120 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x34128 0x34128 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x34130 0x3413F 0x34140 0x34140 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x34148 0x34148 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x34150 0x3415F 0x34160 0x34160 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x34168 0x34168 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x34170 0x3417F 0x34180 0x34180 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x34188 0x34188 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x34190 0x36FFF 0x37000 0x37000 pcie_noc.bridge_p0_spio_m_5_7_p_0 pcie_noc.bridge_p0_spio_m_5_7_p_0 0x37004 0x37007 0x37008 0x37008 pcie_noc.bridge_p0_spio_m_5_7_p_1 pcie_noc.bridge_p0_spio_m_5_7_p_1 0x3700C 0x3700F 0x37010 0x37010 pcie_noc.bridge_p0_spio_m_5_7_p_2 pcie_noc.bridge_p0_spio_m_5_7_p_2 0x37014 0x37017 0x37018 0x37018 pcie_noc.bridge_p0_spio_m_5_7_p_3 pcie_noc.bridge_p0_spio_m_5_7_p_3 0x3701C 0x3703F 0x37040 0x37040 pcie_noc.bridge_p0_spio_m_5_7_txe pcie_noc.bridge_p0_spio_m_5_7_txe 0x37044 0x37047 0x37048 0x37048 pcie_noc.bridge_p0_spio_m_5_7_txem pcie_noc.bridge_p0_spio_m_5_7_txem 0x3704C 0x37057 0x37058 0x37058 pcie_noc.bridge_p0_spio_m_5_7_btus_0 pcie_noc.bridge_p0_spio_m_5_7_btus_0 0x3705C 0x3705F 0x37060 0x37060 pcie_noc.bridge_p0_spio_m_5_7_btus_1 pcie_noc.bridge_p0_spio_m_5_7_btus_1 0x37064 0x3707F 0x37080 0x37080 pcie_noc.bridge_p0_spio_m_5_7_btrl_0 pcie_noc.bridge_p0_spio_m_5_7_btrl_0 0x37084 0x37087 0x37088 0x37088 pcie_noc.bridge_p0_spio_m_5_7_btrl_1 pcie_noc.bridge_p0_spio_m_5_7_btrl_1 0x3708C 0x3708F 0x37090 0x37090 pcie_noc.bridge_p0_spio_m_5_7_btrl_2 pcie_noc.bridge_p0_spio_m_5_7_btrl_2 0x37094 0x37097 0x37098 0x37098 pcie_noc.bridge_p0_spio_m_5_7_btrl_3 pcie_noc.bridge_p0_spio_m_5_7_btrl_3 0x3709C 0x370A7 0x370A8 0x370A8 pcie_noc.bridge_p0_spio_m_5_7_btperr pcie_noc.bridge_p0_spio_m_5_7_btperr 0x370AC 0x370AF 0x370B0 0x370B0 pcie_noc.bridge_p0_spio_m_5_7_btperrm pcie_noc.bridge_p0_spio_m_5_7_btperrm 0x370B4 0x3711F 0x37120 0x37120 pcie_noc.bridge_p0_spio_m_5_7_rxe pcie_noc.bridge_p0_spio_m_5_7_rxe 0x37124 0x37127 0x37128 0x37128 pcie_noc.bridge_p0_spio_m_5_7_rxem pcie_noc.bridge_p0_spio_m_5_7_rxem 0x3712C 0x3712F 0x37130 0x37130 pcie_noc.bridge_p0_spio_m_5_7_brs_0 pcie_noc.bridge_p0_spio_m_5_7_brs_0 0x37134 0x37137 0x37138 0x37138 pcie_noc.bridge_p0_spio_m_5_7_brs_1 pcie_noc.bridge_p0_spio_m_5_7_brs_1 0x3713C 0x371AF 0x371B0 0x371B0 pcie_noc.bridge_p0_spio_m_5_7_brus pcie_noc.bridge_p0_spio_m_5_7_brus 0x371B4 0x371CF 0x371D0 0x371D0 pcie_noc.bridge_p0_spio_m_5_7_brperr0 pcie_noc.bridge_p0_spio_m_5_7_brperr0 0x371D8 0x371D8 pcie_noc.bridge_p0_spio_m_5_7_brperr1 pcie_noc.bridge_p0_spio_m_5_7_brperr1 0x371E0 0x371E0 pcie_noc.bridge_p0_spio_m_5_7_brperrm0 pcie_noc.bridge_p0_spio_m_5_7_brperrm0 0x371E8 0x371E8 pcie_noc.bridge_p0_spio_m_5_7_brperrm1 pcie_noc.bridge_p0_spio_m_5_7_brperrm1 0x371F0 0x37BFF 0x37C00 0x37C00 pcie_noc.bridge_p0_spio_m_5_7_am_tocfg pcie_noc.bridge_p0_spio_m_5_7_am_tocfg 0x37C08 0x37C08 pcie_noc.bridge_p0_spio_m_5_7_am_osslv pcie_noc.bridge_p0_spio_m_5_7_am_osslv 0x37C10 0x37C10 pcie_noc.bridge_p0_spio_m_5_7_am_cgc pcie_noc.bridge_p0_spio_m_5_7_am_cgc 0x37C18 0x37C18 pcie_noc.bridge_p0_spio_m_5_7_am_cgo pcie_noc.bridge_p0_spio_m_5_7_am_cgo 0x37C20 0x37C20 pcie_noc.bridge_p0_spio_m_5_7_am_cfg pcie_noc.bridge_p0_spio_m_5_7_am_cfg 0x37C28 0x37CFF 0x37D00 0x37D00 pcie_noc.bridge_p0_spio_m_5_7_am_sts pcie_noc.bridge_p0_spio_m_5_7_am_sts 0x37D08 0x37D08 pcie_noc.bridge_p0_spio_m_5_7_am_bridge_id pcie_noc.bridge_p0_spio_m_5_7_am_bridge_id 0x37D10 0x37DFF 0x37E00 0x37E00 pcie_noc.bridge_p0_spio_m_5_7_am_err pcie_noc.bridge_p0_spio_m_5_7_am_err 0x37E08 0x37E08 pcie_noc.bridge_p0_spio_m_5_7_am_toslvid pcie_noc.bridge_p0_spio_m_5_7_am_toslvid 0x37E10 0x37E10 pcie_noc.bridge_p0_spio_m_5_7_am_era pcie_noc.bridge_p0_spio_m_5_7_am_era 0x37E18 0x37E18 pcie_noc.bridge_p0_spio_m_5_7_am_ewa pcie_noc.bridge_p0_spio_m_5_7_am_ewa 0x37E20 0x37E3F 0x37E40 0x37E40 pcie_noc.bridge_p0_spio_m_5_7_am_intm pcie_noc.bridge_p0_spio_m_5_7_am_intm 0x37E48 0x37EFF 0x37F00 0x37F00 pcie_noc.bridge_p0_spio_m_5_7_am_caddr pcie_noc.bridge_p0_spio_m_5_7_am_caddr 0x37F08 0x37F08 pcie_noc.bridge_p0_spio_m_5_7_am_caddrmsk pcie_noc.bridge_p0_spio_m_5_7_am_caddrmsk 0x37F10 0x37F10 pcie_noc.bridge_p0_spio_m_5_7_am_ccmd0 pcie_noc.bridge_p0_spio_m_5_7_am_ccmd0 0x37F18 0x37F18 pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk0 pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk0 0x37F20 0x37F20 pcie_noc.bridge_p0_spio_m_5_7_am_cntr0 pcie_noc.bridge_p0_spio_m_5_7_am_cntr0 0x37F28 0x37F28 pcie_noc.bridge_p0_spio_m_5_7_am_latnum0 pcie_noc.bridge_p0_spio_m_5_7_am_latnum0 0x37F30 0x37F30 pcie_noc.bridge_p0_spio_m_5_7_am_ccmd1 pcie_noc.bridge_p0_spio_m_5_7_am_ccmd1 0x37F38 0x37F38 pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk1 pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk1 0x37F40 0x37F40 pcie_noc.bridge_p0_spio_m_5_7_am_cntr1 pcie_noc.bridge_p0_spio_m_5_7_am_cntr1 0x37F48 0x37F48 pcie_noc.bridge_p0_spio_m_5_7_am_latnum1 pcie_noc.bridge_p0_spio_m_5_7_am_latnum1 0x37F50 0x37F5F 0x37F60 0x37F60 pcie_noc.bridge_p0_spio_m_5_7_am_arovrd pcie_noc.bridge_p0_spio_m_5_7_am_arovrd 0x37F68 0x37F68 pcie_noc.bridge_p0_spio_m_5_7_am_awovrd pcie_noc.bridge_p0_spio_m_5_7_am_awovrd 0x37F70 0x37FFF 0x38000 0x38000 pcie_noc.router_0_5_5_rivcs_h pcie_noc.router_0_5_5_rivcs_h 0x38004 0x38007 0x38008 0x38008 pcie_noc.router_0_5_5_rivcs_e pcie_noc.router_0_5_5_rivcs_e 0x3800C 0x3800F 0x38010 0x38010 pcie_noc.router_0_5_5_rivcs_s pcie_noc.router_0_5_5_rivcs_s 0x38014 0x38017 0x38018 0x38018 pcie_noc.router_0_5_5_rivcs_w pcie_noc.router_0_5_5_rivcs_w 0x3801C 0x38027 0x38028 0x38028 pcie_noc.router_0_5_5_rivcs_i pcie_noc.router_0_5_5_rivcs_i 0x3802C 0x3802F 0x38030 0x38030 pcie_noc.router_0_5_5_rivcs_j pcie_noc.router_0_5_5_rivcs_j 0x38034 0x38037 0x38038 0x38038 pcie_noc.router_0_5_5_rivcs_k pcie_noc.router_0_5_5_rivcs_k 0x3803C 0x3803F 0x38040 0x38040 pcie_noc.router_0_5_5_rovcs_h pcie_noc.router_0_5_5_rovcs_h 0x38044 0x38047 0x38048 0x38048 pcie_noc.router_0_5_5_rovcs_e pcie_noc.router_0_5_5_rovcs_e 0x3804C 0x3804F 0x38050 0x38050 pcie_noc.router_0_5_5_rovcs_s pcie_noc.router_0_5_5_rovcs_s 0x38054 0x38057 0x38058 0x38058 pcie_noc.router_0_5_5_rovcs_w pcie_noc.router_0_5_5_rovcs_w 0x3805C 0x38067 0x38068 0x38068 pcie_noc.router_0_5_5_rovcs_i pcie_noc.router_0_5_5_rovcs_i 0x3806C 0x3806F 0x38070 0x38070 pcie_noc.router_0_5_5_rovcs_j pcie_noc.router_0_5_5_rovcs_j 0x38074 0x38077 0x38078 0x38078 pcie_noc.router_0_5_5_rovcs_k pcie_noc.router_0_5_5_rovcs_k 0x3807C 0x3807F 0x38080 0x38080 pcie_noc.router_0_5_5_re pcie_noc.router_0_5_5_re 0x38084 0x38087 0x38088 0x38088 pcie_noc.router_0_5_5_rem pcie_noc.router_0_5_5_rem 0x3808C 0x3808F 0x38090 0x38090 pcie_noc.router_0_5_5_recc pcie_noc.router_0_5_5_recc 0x38094 0x38097 0x38098 0x38098 pcie_noc.router_0_5_5_rec pcie_noc.router_0_5_5_rec 0x3809C 0x3809F 0x380A0 0x380A0 pcie_noc.router_0_5_5_id pcie_noc.router_0_5_5_id 0x380A4 0x380A7 0x380A8 0x380A8 pcie_noc.router_0_5_5_rcgc pcie_noc.router_0_5_5_rcgc 0x380AC 0x380AF 0x380B0 0x380B0 pcie_noc.router_0_5_5_rcgo pcie_noc.router_0_5_5_rcgo 0x380B4 0x380BF 0x380C0 0x380C0 pcie_noc.router_0_5_5_p1_rperr pcie_noc.router_0_5_5_p1_rperr 0x380C4 0x380C7 0x380C8 0x380C8 pcie_noc.router_0_5_5_p2_rperr pcie_noc.router_0_5_5_p2_rperr 0x380CC 0x380CF 0x380D0 0x380D0 pcie_noc.router_0_5_5_p3_rperr pcie_noc.router_0_5_5_p3_rperr 0x380D4 0x380D7 0x380D8 0x380D8 pcie_noc.router_0_5_5_p4_rperr pcie_noc.router_0_5_5_p4_rperr 0x380DC 0x380DF 0x380E0 0x380E0 pcie_noc.router_0_5_5_p5_rperr pcie_noc.router_0_5_5_p5_rperr 0x380E4 0x380E7 0x380E8 0x380E8 pcie_noc.router_0_5_5_p6_rperr pcie_noc.router_0_5_5_p6_rperr 0x380EC 0x380EF 0x380F0 0x380F0 pcie_noc.router_0_5_5_p7_rperr pcie_noc.router_0_5_5_p7_rperr 0x380F4 0x380FF 0x38100 0x38100 pcie_noc.router_0_5_5_p1_rperrm pcie_noc.router_0_5_5_p1_rperrm 0x38104 0x38107 0x38108 0x38108 pcie_noc.router_0_5_5_p2_rperrm pcie_noc.router_0_5_5_p2_rperrm 0x3810C 0x3810F 0x38110 0x38110 pcie_noc.router_0_5_5_p3_rperrm pcie_noc.router_0_5_5_p3_rperrm 0x38114 0x38117 0x38118 0x38118 pcie_noc.router_0_5_5_p4_rperrm pcie_noc.router_0_5_5_p4_rperrm 0x3811C 0x3811F 0x38120 0x38120 pcie_noc.router_0_5_5_p5_rperrm pcie_noc.router_0_5_5_p5_rperrm 0x38124 0x38127 0x38128 0x38128 pcie_noc.router_0_5_5_p6_rperrm pcie_noc.router_0_5_5_p6_rperrm 0x3812C 0x3812F 0x38130 0x38130 pcie_noc.router_0_5_5_p7_rperrm pcie_noc.router_0_5_5_p7_rperrm 0x38134 0x38137 0x38138 0x38138 pcie_noc.router_0_5_5_roecc pcie_noc.router_0_5_5_roecc 0x3813C 0x3813F 0x38140 0x38140 pcie_noc.router_0_5_5_roec pcie_noc.router_0_5_5_roec 0x38144 0x3BFFF 0x3C000 0x3C000 pcie_noc.router_0_6_6_rivcs_h pcie_noc.router_0_6_6_rivcs_h 0x3C004 0x3C007 0x3C008 0x3C008 pcie_noc.router_0_6_6_rivcs_e pcie_noc.router_0_6_6_rivcs_e 0x3C00C 0x3C00F 0x3C010 0x3C010 pcie_noc.router_0_6_6_rivcs_s pcie_noc.router_0_6_6_rivcs_s 0x3C014 0x3C017 0x3C018 0x3C018 pcie_noc.router_0_6_6_rivcs_w pcie_noc.router_0_6_6_rivcs_w 0x3C01C 0x3C01F 0x3C020 0x3C020 pcie_noc.router_0_6_6_rivcs_n pcie_noc.router_0_6_6_rivcs_n 0x3C024 0x3C027 0x3C028 0x3C028 pcie_noc.router_0_6_6_rivcs_i pcie_noc.router_0_6_6_rivcs_i 0x3C02C 0x3C02F 0x3C030 0x3C030 pcie_noc.router_0_6_6_rivcs_j pcie_noc.router_0_6_6_rivcs_j 0x3C034 0x3C037 0x3C038 0x3C038 pcie_noc.router_0_6_6_rivcs_k pcie_noc.router_0_6_6_rivcs_k 0x3C03C 0x3C03F 0x3C040 0x3C040 pcie_noc.router_0_6_6_rovcs_h pcie_noc.router_0_6_6_rovcs_h 0x3C044 0x3C047 0x3C048 0x3C048 pcie_noc.router_0_6_6_rovcs_e pcie_noc.router_0_6_6_rovcs_e 0x3C04C 0x3C04F 0x3C050 0x3C050 pcie_noc.router_0_6_6_rovcs_s pcie_noc.router_0_6_6_rovcs_s 0x3C054 0x3C057 0x3C058 0x3C058 pcie_noc.router_0_6_6_rovcs_w pcie_noc.router_0_6_6_rovcs_w 0x3C05C 0x3C05F 0x3C060 0x3C060 pcie_noc.router_0_6_6_rovcs_n pcie_noc.router_0_6_6_rovcs_n 0x3C064 0x3C067 0x3C068 0x3C068 pcie_noc.router_0_6_6_rovcs_i pcie_noc.router_0_6_6_rovcs_i 0x3C06C 0x3C06F 0x3C070 0x3C070 pcie_noc.router_0_6_6_rovcs_j pcie_noc.router_0_6_6_rovcs_j 0x3C074 0x3C077 0x3C078 0x3C078 pcie_noc.router_0_6_6_rovcs_k pcie_noc.router_0_6_6_rovcs_k 0x3C07C 0x3C07F 0x3C080 0x3C080 pcie_noc.router_0_6_6_re pcie_noc.router_0_6_6_re 0x3C084 0x3C087 0x3C088 0x3C088 pcie_noc.router_0_6_6_rem pcie_noc.router_0_6_6_rem 0x3C08C 0x3C08F 0x3C090 0x3C090 pcie_noc.router_0_6_6_recc pcie_noc.router_0_6_6_recc 0x3C094 0x3C097 0x3C098 0x3C098 pcie_noc.router_0_6_6_rec pcie_noc.router_0_6_6_rec 0x3C09C 0x3C09F 0x3C0A0 0x3C0A0 pcie_noc.router_0_6_6_id pcie_noc.router_0_6_6_id 0x3C0A4 0x3C0A7 0x3C0A8 0x3C0A8 pcie_noc.router_0_6_6_rcgc pcie_noc.router_0_6_6_rcgc 0x3C0AC 0x3C0AF 0x3C0B0 0x3C0B0 pcie_noc.router_0_6_6_rcgo pcie_noc.router_0_6_6_rcgo 0x3C0B4 0x3C0B7 0x3C0B8 0x3C0B8 pcie_noc.router_0_6_6_p0_rperr pcie_noc.router_0_6_6_p0_rperr 0x3C0BC 0x3C0BF 0x3C0C0 0x3C0C0 pcie_noc.router_0_6_6_p1_rperr pcie_noc.router_0_6_6_p1_rperr 0x3C0C4 0x3C0C7 0x3C0C8 0x3C0C8 pcie_noc.router_0_6_6_p2_rperr pcie_noc.router_0_6_6_p2_rperr 0x3C0CC 0x3C0CF 0x3C0D0 0x3C0D0 pcie_noc.router_0_6_6_p3_rperr pcie_noc.router_0_6_6_p3_rperr 0x3C0D4 0x3C0D7 0x3C0D8 0x3C0D8 pcie_noc.router_0_6_6_p4_rperr pcie_noc.router_0_6_6_p4_rperr 0x3C0DC 0x3C0DF 0x3C0E0 0x3C0E0 pcie_noc.router_0_6_6_p5_rperr pcie_noc.router_0_6_6_p5_rperr 0x3C0E4 0x3C0E7 0x3C0E8 0x3C0E8 pcie_noc.router_0_6_6_p6_rperr pcie_noc.router_0_6_6_p6_rperr 0x3C0EC 0x3C0EF 0x3C0F0 0x3C0F0 pcie_noc.router_0_6_6_p7_rperr pcie_noc.router_0_6_6_p7_rperr 0x3C0F4 0x3C0F7 0x3C0F8 0x3C0F8 pcie_noc.router_0_6_6_p0_rperrm pcie_noc.router_0_6_6_p0_rperrm 0x3C0FC 0x3C0FF 0x3C100 0x3C100 pcie_noc.router_0_6_6_p1_rperrm pcie_noc.router_0_6_6_p1_rperrm 0x3C104 0x3C107 0x3C108 0x3C108 pcie_noc.router_0_6_6_p2_rperrm pcie_noc.router_0_6_6_p2_rperrm 0x3C10C 0x3C10F 0x3C110 0x3C110 pcie_noc.router_0_6_6_p3_rperrm pcie_noc.router_0_6_6_p3_rperrm 0x3C114 0x3C117 0x3C118 0x3C118 pcie_noc.router_0_6_6_p4_rperrm pcie_noc.router_0_6_6_p4_rperrm 0x3C11C 0x3C11F 0x3C120 0x3C120 pcie_noc.router_0_6_6_p5_rperrm pcie_noc.router_0_6_6_p5_rperrm 0x3C124 0x3C127 0x3C128 0x3C128 pcie_noc.router_0_6_6_p6_rperrm pcie_noc.router_0_6_6_p6_rperrm 0x3C12C 0x3C12F 0x3C130 0x3C130 pcie_noc.router_0_6_6_p7_rperrm pcie_noc.router_0_6_6_p7_rperrm 0x3C134 0x3C137 0x3C138 0x3C138 pcie_noc.router_0_6_6_roecc pcie_noc.router_0_6_6_roecc 0x3C13C 0x3C13F 0x3C140 0x3C140 pcie_noc.router_0_6_6_roec pcie_noc.router_0_6_6_roec 0x3C144 0x3FFFF 0x40000 0x40000 pcie_noc.router_1_5_5_rivcs_h pcie_noc.router_1_5_5_rivcs_h 0x40004 0x40007 0x40008 0x40008 pcie_noc.router_1_5_5_rivcs_e pcie_noc.router_1_5_5_rivcs_e 0x4000C 0x4000F 0x40010 0x40010 pcie_noc.router_1_5_5_rivcs_s pcie_noc.router_1_5_5_rivcs_s 0x40014 0x40017 0x40018 0x40018 pcie_noc.router_1_5_5_rivcs_w pcie_noc.router_1_5_5_rivcs_w 0x4001C 0x40027 0x40028 0x40028 pcie_noc.router_1_5_5_rivcs_i pcie_noc.router_1_5_5_rivcs_i 0x4002C 0x4002F 0x40030 0x40030 pcie_noc.router_1_5_5_rivcs_j pcie_noc.router_1_5_5_rivcs_j 0x40034 0x40037 0x40038 0x40038 pcie_noc.router_1_5_5_rivcs_k pcie_noc.router_1_5_5_rivcs_k 0x4003C 0x4003F 0x40040 0x40040 pcie_noc.router_1_5_5_rovcs_h pcie_noc.router_1_5_5_rovcs_h 0x40044 0x40047 0x40048 0x40048 pcie_noc.router_1_5_5_rovcs_e pcie_noc.router_1_5_5_rovcs_e 0x4004C 0x4004F 0x40050 0x40050 pcie_noc.router_1_5_5_rovcs_s pcie_noc.router_1_5_5_rovcs_s 0x40054 0x40057 0x40058 0x40058 pcie_noc.router_1_5_5_rovcs_w pcie_noc.router_1_5_5_rovcs_w 0x4005C 0x40067 0x40068 0x40068 pcie_noc.router_1_5_5_rovcs_i pcie_noc.router_1_5_5_rovcs_i 0x4006C 0x4006F 0x40070 0x40070 pcie_noc.router_1_5_5_rovcs_j pcie_noc.router_1_5_5_rovcs_j 0x40074 0x40077 0x40078 0x40078 pcie_noc.router_1_5_5_rovcs_k pcie_noc.router_1_5_5_rovcs_k 0x4007C 0x4007F 0x40080 0x40080 pcie_noc.router_1_5_5_re pcie_noc.router_1_5_5_re 0x40084 0x40087 0x40088 0x40088 pcie_noc.router_1_5_5_rem pcie_noc.router_1_5_5_rem 0x4008C 0x4008F 0x40090 0x40090 pcie_noc.router_1_5_5_recc pcie_noc.router_1_5_5_recc 0x40094 0x40097 0x40098 0x40098 pcie_noc.router_1_5_5_rec pcie_noc.router_1_5_5_rec 0x4009C 0x4009F 0x400A0 0x400A0 pcie_noc.router_1_5_5_id pcie_noc.router_1_5_5_id 0x400A4 0x400A7 0x400A8 0x400A8 pcie_noc.router_1_5_5_rcgc pcie_noc.router_1_5_5_rcgc 0x400AC 0x400AF 0x400B0 0x400B0 pcie_noc.router_1_5_5_rcgo pcie_noc.router_1_5_5_rcgo 0x400B4 0x400BF 0x400C0 0x400C0 pcie_noc.router_1_5_5_p1_rperr pcie_noc.router_1_5_5_p1_rperr 0x400C4 0x400C7 0x400C8 0x400C8 pcie_noc.router_1_5_5_p2_rperr pcie_noc.router_1_5_5_p2_rperr 0x400CC 0x400CF 0x400D0 0x400D0 pcie_noc.router_1_5_5_p3_rperr pcie_noc.router_1_5_5_p3_rperr 0x400D4 0x400D7 0x400D8 0x400D8 pcie_noc.router_1_5_5_p4_rperr pcie_noc.router_1_5_5_p4_rperr 0x400DC 0x400DF 0x400E0 0x400E0 pcie_noc.router_1_5_5_p5_rperr pcie_noc.router_1_5_5_p5_rperr 0x400E4 0x400E7 0x400E8 0x400E8 pcie_noc.router_1_5_5_p6_rperr pcie_noc.router_1_5_5_p6_rperr 0x400EC 0x400EF 0x400F0 0x400F0 pcie_noc.router_1_5_5_p7_rperr pcie_noc.router_1_5_5_p7_rperr 0x400F4 0x400FF 0x40100 0x40100 pcie_noc.router_1_5_5_p1_rperrm pcie_noc.router_1_5_5_p1_rperrm 0x40104 0x40107 0x40108 0x40108 pcie_noc.router_1_5_5_p2_rperrm pcie_noc.router_1_5_5_p2_rperrm 0x4010C 0x4010F 0x40110 0x40110 pcie_noc.router_1_5_5_p3_rperrm pcie_noc.router_1_5_5_p3_rperrm 0x40114 0x40117 0x40118 0x40118 pcie_noc.router_1_5_5_p4_rperrm pcie_noc.router_1_5_5_p4_rperrm 0x4011C 0x4011F 0x40120 0x40120 pcie_noc.router_1_5_5_p5_rperrm pcie_noc.router_1_5_5_p5_rperrm 0x40124 0x40127 0x40128 0x40128 pcie_noc.router_1_5_5_p6_rperrm pcie_noc.router_1_5_5_p6_rperrm 0x4012C 0x4012F 0x40130 0x40130 pcie_noc.router_1_5_5_p7_rperrm pcie_noc.router_1_5_5_p7_rperrm 0x40134 0x40137 0x40138 0x40138 pcie_noc.router_1_5_5_roecc pcie_noc.router_1_5_5_roecc 0x4013C 0x4013F 0x40140 0x40140 pcie_noc.router_1_5_5_roec pcie_noc.router_1_5_5_roec 0x40144 0x43FFF 0x44000 0x44000 pcie_noc.router_1_6_6_rivcs_h pcie_noc.router_1_6_6_rivcs_h 0x44004 0x44007 0x44008 0x44008 pcie_noc.router_1_6_6_rivcs_e pcie_noc.router_1_6_6_rivcs_e 0x4400C 0x4400F 0x44010 0x44010 pcie_noc.router_1_6_6_rivcs_s pcie_noc.router_1_6_6_rivcs_s 0x44014 0x44017 0x44018 0x44018 pcie_noc.router_1_6_6_rivcs_w pcie_noc.router_1_6_6_rivcs_w 0x4401C 0x4401F 0x44020 0x44020 pcie_noc.router_1_6_6_rivcs_n pcie_noc.router_1_6_6_rivcs_n 0x44024 0x44027 0x44028 0x44028 pcie_noc.router_1_6_6_rivcs_i pcie_noc.router_1_6_6_rivcs_i 0x4402C 0x4402F 0x44030 0x44030 pcie_noc.router_1_6_6_rivcs_j pcie_noc.router_1_6_6_rivcs_j 0x44034 0x44037 0x44038 0x44038 pcie_noc.router_1_6_6_rivcs_k pcie_noc.router_1_6_6_rivcs_k 0x4403C 0x4403F 0x44040 0x44040 pcie_noc.router_1_6_6_rovcs_h pcie_noc.router_1_6_6_rovcs_h 0x44044 0x44047 0x44048 0x44048 pcie_noc.router_1_6_6_rovcs_e pcie_noc.router_1_6_6_rovcs_e 0x4404C 0x4404F 0x44050 0x44050 pcie_noc.router_1_6_6_rovcs_s pcie_noc.router_1_6_6_rovcs_s 0x44054 0x44057 0x44058 0x44058 pcie_noc.router_1_6_6_rovcs_w pcie_noc.router_1_6_6_rovcs_w 0x4405C 0x4405F 0x44060 0x44060 pcie_noc.router_1_6_6_rovcs_n pcie_noc.router_1_6_6_rovcs_n 0x44064 0x44067 0x44068 0x44068 pcie_noc.router_1_6_6_rovcs_i pcie_noc.router_1_6_6_rovcs_i 0x4406C 0x4406F 0x44070 0x44070 pcie_noc.router_1_6_6_rovcs_j pcie_noc.router_1_6_6_rovcs_j 0x44074 0x44077 0x44078 0x44078 pcie_noc.router_1_6_6_rovcs_k pcie_noc.router_1_6_6_rovcs_k 0x4407C 0x4407F 0x44080 0x44080 pcie_noc.router_1_6_6_re pcie_noc.router_1_6_6_re 0x44084 0x44087 0x44088 0x44088 pcie_noc.router_1_6_6_rem pcie_noc.router_1_6_6_rem 0x4408C 0x4408F 0x44090 0x44090 pcie_noc.router_1_6_6_recc pcie_noc.router_1_6_6_recc 0x44094 0x44097 0x44098 0x44098 pcie_noc.router_1_6_6_rec pcie_noc.router_1_6_6_rec 0x4409C 0x4409F 0x440A0 0x440A0 pcie_noc.router_1_6_6_id pcie_noc.router_1_6_6_id 0x440A4 0x440A7 0x440A8 0x440A8 pcie_noc.router_1_6_6_rcgc pcie_noc.router_1_6_6_rcgc 0x440AC 0x440AF 0x440B0 0x440B0 pcie_noc.router_1_6_6_rcgo pcie_noc.router_1_6_6_rcgo 0x440B4 0x440B7 0x440B8 0x440B8 pcie_noc.router_1_6_6_p0_rperr pcie_noc.router_1_6_6_p0_rperr 0x440BC 0x440BF 0x440C0 0x440C0 pcie_noc.router_1_6_6_p1_rperr pcie_noc.router_1_6_6_p1_rperr 0x440C4 0x440C7 0x440C8 0x440C8 pcie_noc.router_1_6_6_p2_rperr pcie_noc.router_1_6_6_p2_rperr 0x440CC 0x440CF 0x440D0 0x440D0 pcie_noc.router_1_6_6_p3_rperr pcie_noc.router_1_6_6_p3_rperr 0x440D4 0x440D7 0x440D8 0x440D8 pcie_noc.router_1_6_6_p4_rperr pcie_noc.router_1_6_6_p4_rperr 0x440DC 0x440DF 0x440E0 0x440E0 pcie_noc.router_1_6_6_p5_rperr pcie_noc.router_1_6_6_p5_rperr 0x440E4 0x440E7 0x440E8 0x440E8 pcie_noc.router_1_6_6_p6_rperr pcie_noc.router_1_6_6_p6_rperr 0x440EC 0x440EF 0x440F0 0x440F0 pcie_noc.router_1_6_6_p7_rperr pcie_noc.router_1_6_6_p7_rperr 0x440F4 0x440F7 0x440F8 0x440F8 pcie_noc.router_1_6_6_p0_rperrm pcie_noc.router_1_6_6_p0_rperrm 0x440FC 0x440FF 0x44100 0x44100 pcie_noc.router_1_6_6_p1_rperrm pcie_noc.router_1_6_6_p1_rperrm 0x44104 0x44107 0x44108 0x44108 pcie_noc.router_1_6_6_p2_rperrm pcie_noc.router_1_6_6_p2_rperrm 0x4410C 0x4410F 0x44110 0x44110 pcie_noc.router_1_6_6_p3_rperrm pcie_noc.router_1_6_6_p3_rperrm 0x44114 0x44117 0x44118 0x44118 pcie_noc.router_1_6_6_p4_rperrm pcie_noc.router_1_6_6_p4_rperrm 0x4411C 0x4411F 0x44120 0x44120 pcie_noc.router_1_6_6_p5_rperrm pcie_noc.router_1_6_6_p5_rperrm 0x44124 0x44127 0x44128 0x44128 pcie_noc.router_1_6_6_p6_rperrm pcie_noc.router_1_6_6_p6_rperrm 0x4412C 0x4412F 0x44130 0x44130 pcie_noc.router_1_6_6_p7_rperrm pcie_noc.router_1_6_6_p7_rperrm 0x44134 0x44137 0x44138 0x44138 pcie_noc.router_1_6_6_roecc pcie_noc.router_1_6_6_roecc 0x4413C 0x4413F 0x44140 0x44140 pcie_noc.router_1_6_6_roec pcie_noc.router_1_6_6_roec 0x44144 0x4807F 0x48080 0x48080 pcie_noc.router_2_1_1_re pcie_noc.router_2_1_1_re 0x48084 0x48087 0x48088 0x48088 pcie_noc.router_2_1_1_rem pcie_noc.router_2_1_1_rem 0x4808C 0x4809F 0x480A0 0x480A0 pcie_noc.router_2_1_1_id pcie_noc.router_2_1_1_id 0x480A4 0x480AF 0x480B0 0x480B0 pcie_noc.router_2_1_1_rcgo pcie_noc.router_2_1_1_rcgo 0x480B4 0x480BF 0x480C0 0x480C0 pcie_noc.router_2_1_1_p1_rperr pcie_noc.router_2_1_1_p1_rperr 0x480C4 0x480C7 0x480C8 0x480C8 pcie_noc.router_2_1_1_p2_rperr pcie_noc.router_2_1_1_p2_rperr 0x480CC 0x480CF 0x480D0 0x480D0 pcie_noc.router_2_1_1_p3_rperr pcie_noc.router_2_1_1_p3_rperr 0x480D4 0x480D7 0x480D8 0x480D8 pcie_noc.router_2_1_1_p4_rperr pcie_noc.router_2_1_1_p4_rperr 0x480DC 0x480FF 0x48100 0x48100 pcie_noc.router_2_1_1_p1_rperrm pcie_noc.router_2_1_1_p1_rperrm 0x48104 0x48107 0x48108 0x48108 pcie_noc.router_2_1_1_p2_rperrm pcie_noc.router_2_1_1_p2_rperrm 0x4810C 0x4810F 0x48110 0x48110 pcie_noc.router_2_1_1_p3_rperrm pcie_noc.router_2_1_1_p3_rperrm 0x48114 0x48117 0x48118 0x48118 pcie_noc.router_2_1_1_p4_rperrm pcie_noc.router_2_1_1_p4_rperrm 0x4811C 0x4C07F 0x4C080 0x4C080 pcie_noc.router_2_3_3_re pcie_noc.router_2_3_3_re 0x4C084 0x4C087 0x4C088 0x4C088 pcie_noc.router_2_3_3_rem pcie_noc.router_2_3_3_rem 0x4C08C 0x4C09F 0x4C0A0 0x4C0A0 pcie_noc.router_2_3_3_id pcie_noc.router_2_3_3_id 0x4C0A4 0x4C0AF 0x4C0B0 0x4C0B0 pcie_noc.router_2_3_3_rcgo pcie_noc.router_2_3_3_rcgo 0x4C0B4 0x4C0C7 0x4C0C8 0x4C0C8 pcie_noc.router_2_3_3_p2_rperr pcie_noc.router_2_3_3_p2_rperr 0x4C0CC 0x4C0CF 0x4C0D0 0x4C0D0 pcie_noc.router_2_3_3_p3_rperr pcie_noc.router_2_3_3_p3_rperr 0x4C0D4 0x4C0D7 0x4C0D8 0x4C0D8 pcie_noc.router_2_3_3_p4_rperr pcie_noc.router_2_3_3_p4_rperr 0x4C0DC 0x4C107 0x4C108 0x4C108 pcie_noc.router_2_3_3_p2_rperrm pcie_noc.router_2_3_3_p2_rperrm 0x4C10C 0x4C10F 0x4C110 0x4C110 pcie_noc.router_2_3_3_p3_rperrm pcie_noc.router_2_3_3_p3_rperrm 0x4C114 0x4C117 0x4C118 0x4C118 pcie_noc.router_2_3_3_p4_rperrm pcie_noc.router_2_3_3_p4_rperrm 0x4C11C 0x5007F 0x50080 0x50080 pcie_noc.router_2_5_5_re pcie_noc.router_2_5_5_re 0x50084 0x50087 0x50088 0x50088 pcie_noc.router_2_5_5_rem pcie_noc.router_2_5_5_rem 0x5008C 0x5009F 0x500A0 0x500A0 pcie_noc.router_2_5_5_id pcie_noc.router_2_5_5_id 0x500A4 0x500AF 0x500B0 0x500B0 pcie_noc.router_2_5_5_rcgo pcie_noc.router_2_5_5_rcgo 0x500B4 0x500B7 0x500B8 0x500B8 pcie_noc.router_2_5_5_p0_rperr pcie_noc.router_2_5_5_p0_rperr 0x500BC 0x500BF 0x500C0 0x500C0 pcie_noc.router_2_5_5_p1_rperr pcie_noc.router_2_5_5_p1_rperr 0x500C4 0x500D7 0x500D8 0x500D8 pcie_noc.router_2_5_5_p4_rperr pcie_noc.router_2_5_5_p4_rperr 0x500DC 0x500F7 0x500F8 0x500F8 pcie_noc.router_2_5_5_p0_rperrm pcie_noc.router_2_5_5_p0_rperrm 0x500FC 0x500FF 0x50100 0x50100 pcie_noc.router_2_5_5_p1_rperrm pcie_noc.router_2_5_5_p1_rperrm 0x50104 0x50117 0x50118 0x50118 pcie_noc.router_2_5_5_p4_rperrm pcie_noc.router_2_5_5_p4_rperrm 0x5011C 0x5407F 0x54080 0x54080 pcie_noc.router_2_7_7_re pcie_noc.router_2_7_7_re 0x54084 0x54087 0x54088 0x54088 pcie_noc.router_2_7_7_rem pcie_noc.router_2_7_7_rem 0x5408C 0x5409F 0x540A0 0x540A0 pcie_noc.router_2_7_7_id pcie_noc.router_2_7_7_id 0x540A4 0x540AF 0x540B0 0x540B0 pcie_noc.router_2_7_7_rcgo pcie_noc.router_2_7_7_rcgo 0x540B4 0x540B7 0x540B8 0x540B8 pcie_noc.router_2_7_7_p0_rperr pcie_noc.router_2_7_7_p0_rperr 0x540BC 0x540CF 0x540D0 0x540D0 pcie_noc.router_2_7_7_p3_rperr pcie_noc.router_2_7_7_p3_rperr 0x540D4 0x540D7 0x540D8 0x540D8 pcie_noc.router_2_7_7_p4_rperr pcie_noc.router_2_7_7_p4_rperr 0x540DC 0x540F7 0x540F8 0x540F8 pcie_noc.router_2_7_7_p0_rperrm pcie_noc.router_2_7_7_p0_rperrm 0x540FC 0x5410F 0x54110 0x54110 pcie_noc.router_2_7_7_p3_rperrm pcie_noc.router_2_7_7_p3_rperrm 0x54114 0x54117 0x54118 0x54118 pcie_noc.router_2_7_7_p4_rperrm pcie_noc.router_2_7_7_p4_rperrm 0x5411C 0x7FFFF register pcie_noc.bridge_rbm_m_13_1_p_0 bridge_rbm_m_13_1_p_0 PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72 rbm_m register p_0 0x3000 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 35 WT_QOS_0 Weight of QoS profile 0 7 0 0x00 R WT_QOS_1 PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 47 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 59 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 71 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_rbm_m_13_1_p_1 bridge_rbm_m_13_1_p_1 PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 138 rbm_m register p_1 0x3008 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 101 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 113 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 125 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 137 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_rbm_m_13_1_p_2 bridge_rbm_m_13_1_p_2 PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 204 rbm_m register p_2 0x3010 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 167 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 179 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 191 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 203 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_rbm_m_13_1_p_3 bridge_rbm_m_13_1_p_3 PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 270 rbm_m register p_3 0x3018 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 233 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 245 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 257 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 269 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_rbm_m_13_1_txe bridge_rbm_m_13_1_txe PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 416 rbm_m register txe 0x3040 R/W 0x00000000 Pcie_noc_bridge_rbm_m_13_1_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 297 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 309 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 324 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 337 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 351 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 365 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 379 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 393 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 404 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 415 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_rbm_m_13_1_txem bridge_rbm_m_13_1_txem PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 495 rbm_m register txem 0x3048 R/W 0x00000008 Pcie_noc_bridge_rbm_m_13_1_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 439 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 450 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 461 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 472 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 483 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 494 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_rbm_m_13_1_btus_0 bridge_rbm_m_13_1_btus_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 863 rbm_m register btus_0 0x3058 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 521 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 532 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 543 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 554 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 565 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 576 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 587 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 598 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 609 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 620 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 631 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 642 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 653 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 664 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 675 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 686 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 697 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 708 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 719 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 730 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 741 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 752 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 763 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 774 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 785 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 796 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 807 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 818 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 829 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 840 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 851 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 862 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_rbm_m_13_1_btus_1 bridge_rbm_m_13_1_btus_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1231 rbm_m register btus_1 0x3060 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 889 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 900 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 911 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 922 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 933 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 944 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 955 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 966 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 977 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 988 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 999 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 1010 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 1021 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 1032 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 1043 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 1054 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 1065 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 1076 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 1087 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 1098 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 1109 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 1120 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 1131 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 1142 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 1153 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 1164 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 1175 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 1186 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 1197 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 1208 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 1219 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 1230 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_rbm_m_13_1_btrl_0 bridge_rbm_m_13_1_btrl_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1307 rbm_m register btrl_0 0x3080 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 1255 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 1266 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 1281 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 1295 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 1306 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_rbm_m_13_1_btrl_1 bridge_rbm_m_13_1_btrl_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1383 rbm_m register btrl_1 0x3088 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 1331 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 1342 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 1357 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 1371 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 1382 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_rbm_m_13_1_btrl_2 bridge_rbm_m_13_1_btrl_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1459 rbm_m register btrl_2 0x3090 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 1407 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 1418 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 1433 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 1447 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 1458 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_rbm_m_13_1_btrl_3 bridge_rbm_m_13_1_btrl_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1535 rbm_m register btrl_3 0x3098 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 1483 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 1494 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 1509 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 1523 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 1534 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_rbm_m_13_1_btperr bridge_rbm_m_13_1_btperr PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1737 rbm_m register btperr 0x30A8 R/W 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 1560 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 1571 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 1582 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 1593 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 1604 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 1615 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 1626 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 1637 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 1648 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 1659 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 1670 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 1681 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 1692 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 1703 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 1714 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 1725 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 1736 UNSD 31 16 0x0000 R register pcie_noc.bridge_rbm_m_13_1_btperrm bridge_rbm_m_13_1_btperrm PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 1937 rbm_m register btperrm 0x30B0 R/W 0x00000000 Pcie_noc_bridge_rbm_m_13_1_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 1760 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 1771 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 1782 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 1793 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 1804 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 1815 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 1826 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 1837 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 1848 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 1859 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 1870 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 1881 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 1892 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 1903 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 1914 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 1925 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 1936 UNSD 31 16 0x0000 R register pcie_noc.bridge_rbm_m_13_1_rxe bridge_rbm_m_13_1_rxe PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 2045 rbm_m register rxe 0x3120 R/W 0x00000000 Pcie_noc_bridge_rbm_m_13_1_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 1965 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 1976 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 1987 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 1998 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 2010 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 2021 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 2033 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 2044 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_rbm_m_13_1_rxem bridge_rbm_m_13_1_rxem PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 2117 rbm_m register rxem 0x3128 R/W 0x00000050 Pcie_noc_bridge_rbm_m_13_1_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 2066 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 2080 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 2091 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 2105 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 2116 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_rbm_m_13_1_brs_0 bridge_rbm_m_13_1_brs_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 2391 rbm_m register brs_0 0x3130 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 2141 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 2152 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 2163 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 2174 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 2185 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 2195 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 2206 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 2217 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 2228 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 2239 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 2250 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 2260 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 2271 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 2282 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 2293 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 2304 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 2315 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 2325 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 2336 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 2347 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 2358 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 2369 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 2380 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 2390 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_rbm_m_13_1_brs_1 bridge_rbm_m_13_1_brs_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 2665 rbm_m register brs_1 0x3138 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 2415 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 2426 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 2437 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 2448 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 2459 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 2469 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 2480 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 2491 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 2502 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 2513 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 2524 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 2534 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 2545 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 2556 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 2567 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 2578 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 2589 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 2599 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 2610 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 2621 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 2632 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 2643 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 2654 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 2664 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_rbm_m_13_1_brus bridge_rbm_m_13_1_brus PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 2734 rbm_m register brus 0x31B0 R 0x00000000 Pcie_noc_bridge_rbm_m_13_1_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 2690 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 2701 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 2712 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 2723 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 2733 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_rbm_m_13_1_brperr0 bridge_rbm_m_13_1_brperr0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 2962 rbm_m register brperr0 0x31D0 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 2772 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 2783 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 2794 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 2806 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 2817 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 2828 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 2839 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 2850 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 2861 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 2873 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 2884 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 2895 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 2906 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 2917 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 2928 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 2939 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 2950 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 2961 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_rbm_m_13_1_brperr1 bridge_rbm_m_13_1_brperr1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3078 rbm_m register brperr1 0x31D8 R 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 3000 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 3011 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 3022 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 3033 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 3044 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 3055 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 3066 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 3077 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_rbm_m_13_1_brperrm0 bridge_rbm_m_13_1_brperrm0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3299 rbm_m register brperrm0 0x31E0 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 3105 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 3117 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 3128 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 3140 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 3152 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 3163 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 3174 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 3186 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 3197 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 3209 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 3221 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 3232 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 3243 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 3254 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 3265 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 3276 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 3287 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 3298 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_rbm_m_13_1_brperrm1 bridge_rbm_m_13_1_brperrm1 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3404 rbm_m register brperrm1 0x31E8 R 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 3326 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 3337 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 3348 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 3359 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 3370 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 3381 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 3392 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 3403 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_rbm_m_13_1_am_tocfg bridge_rbm_m_13_1_am_tocfg PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3478 rbm_m register am_tocfg 0x3C00 R/W 0x000000000000001f Pcie_noc_bridge_rbm_m_13_1_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 3441 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 3452 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 3466 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 3477 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_osslv bridge_rbm_m_13_1_am_osslv PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3513 rbm_m register am_osslv 0x3C08 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 3501 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 3512 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_cgc bridge_rbm_m_13_1_am_cgc PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3550 rbm_m register am_cgc 0x3C10 R/W 0x0000000000000064 Pcie_noc_bridge_rbm_m_13_1_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 3538 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 3549 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_cgo bridge_rbm_m_13_1_am_cgo PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3585 rbm_m register am_cgo 0x3C18 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 3573 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 3584 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_cfg bridge_rbm_m_13_1_am_cfg PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3622 rbm_m register am_cfg 0x3C20 R/W 0x0000000000000001 Pcie_noc_bridge_rbm_m_13_1_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 3610 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 3621 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_sts bridge_rbm_m_13_1_am_sts PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3750 rbm_m register am_sts 0x3D00 R 0x000000000000000c Pcie_noc_bridge_rbm_m_13_1_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 3655 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 3669 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 3681 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 3693 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 3704 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 3715 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 3727 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 3739 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 3749 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_bridge_id bridge_rbm_m_13_1_am_bridge_id PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3780 rbm_m register am_bridge_id 0x3D08 R 0x000000000000000d Pcie_noc_bridge_rbm_m_13_1_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 3769 ID Unique bridge ID 15 0 0x000d R UNSD_63_16 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 3779 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_nocver_id bridge_rbm_m_13_1_am_nocver_id PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 3813 rbm_m register am_nocver_id 0x3D10 R 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_nocver_id Version identifier for the NoC. This read-only register is available only on the regbus master. This register is not available on pother master bridges and access will result in decode error response. false false false false NOC_VERSION_ID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_SET ns_noc_io_pcie_soc_ip.csr 3802 NOC_VERSION_ID NoC version ID 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 3812 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_err bridge_rbm_m_13_1_am_err PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4309 rbm_m register am_err 0x3E00 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 3835 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 3847 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 3859 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 3871 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 3883 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 3895 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 3908 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 3921 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 3932 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 3943 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 3954 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 3965 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 3976 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 3987 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 3998 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 4009 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 4020 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 4032 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 4043 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 4054 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 4065 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 4076 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 4088 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 4100 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 4111 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 4123 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 4134 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 4145 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 4156 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 4167 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 4178 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 4189 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 4201 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 4213 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 4225 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 4237 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 4249 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 4261 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 4273 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 4285 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 4297 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 4308 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_rbm_m_13_1_am_toslvid bridge_rbm_m_13_1_am_toslvid PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4354 rbm_m register am_toslvid 0x3E08 R 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 4332 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 4343 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 4353 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_era bridge_rbm_m_13_1_am_era PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4376 rbm_m register am_era 0x3E10 R 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 4375 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_ewa bridge_rbm_m_13_1_am_ewa PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4398 rbm_m register am_ewa 0x3E18 R 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 4397 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_rbm_m_13_1_am_intm bridge_rbm_m_13_1_am_intm PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4882 rbm_m register am_intm 0x3E40 R/W 0x00007e07004f004f Pcie_noc_bridge_rbm_m_13_1_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 4420 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 4431 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 4442 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 4453 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 4464 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 4475 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 4486 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 4497 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 4508 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 4519 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 4530 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 4541 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 4552 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 4563 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 4574 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 4585 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 4596 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 4607 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 4618 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 4629 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 4640 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 4651 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 4662 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 4673 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 4684 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 4696 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 4707 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 4718 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 4729 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 4740 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 4751 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 4762 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 4774 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 4786 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 4798 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 4810 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 4822 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 4834 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 4846 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 4858 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 4870 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 4881 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_rbm_m_13_1_am_caddr bridge_rbm_m_13_1_am_caddr PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4904 rbm_m register am_caddr 0x3F00 R/W 0xffffffffffffffff Pcie_noc_bridge_rbm_m_13_1_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 4903 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_rbm_m_13_1_am_caddrmsk bridge_rbm_m_13_1_am_caddrmsk PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 4927 rbm_m register am_caddrmsk 0x3F08 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 4926 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_rbm_m_13_1_am_ccmd0 bridge_rbm_m_13_1_am_ccmd0 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5117 rbm_m register am_ccmd0 0x3F10 R/W 0x0000000003fff33f Pcie_noc_bridge_rbm_m_13_1_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 4949 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 4960 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 4971 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 4982 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 4993 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 5004 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 5015 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 5026 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 5037 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 5048 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 5059 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 5070 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 5082 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 5093 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 5105 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 5116 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0 bridge_rbm_m_13_1_am_ccmdmsk0 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5261 rbm_m register am_ccmdmsk0 0x3F18 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 5139 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 5150 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 5161 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 5172 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 5183 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 5194 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 5205 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 5216 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 5227 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 5238 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 5249 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 5260 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_rbm_m_13_1_am_cntr0 bridge_rbm_m_13_1_am_cntr0 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5296 rbm_m register am_cntr0 0x3F20 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 5284 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 5295 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_latnum0 bridge_rbm_m_13_1_am_latnum0 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5335 rbm_m register am_latnum0 0x3F28 R/W 0x0000000000000007 Pcie_noc_bridge_rbm_m_13_1_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 5323 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 5334 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_ccmd1 bridge_rbm_m_13_1_am_ccmd1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5525 rbm_m register am_ccmd1 0x3F30 R/W 0x0000000003fff33f Pcie_noc_bridge_rbm_m_13_1_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 5357 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 5368 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 5379 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 5390 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 5401 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 5412 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 5423 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 5434 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 5445 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 5456 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 5467 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 5478 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 5490 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 5501 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 5513 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 5524 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk1 bridge_rbm_m_13_1_am_ccmdmsk1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5669 rbm_m register am_ccmdmsk1 0x3F38 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 5547 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 5558 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 5569 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 5580 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 5591 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 5602 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 5613 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 5624 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 5635 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 5646 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 5657 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 5668 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_rbm_m_13_1_am_cntr1 bridge_rbm_m_13_1_am_cntr1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5704 rbm_m register am_cntr1 0x3F40 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 5692 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 5703 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_latnum1 bridge_rbm_m_13_1_am_latnum1 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5743 rbm_m register am_latnum1 0x3F48 R/W 0x0000000000000007 Pcie_noc_bridge_rbm_m_13_1_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 5731 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 5742 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_rbm_m_13_1_am_arovrd bridge_rbm_m_13_1_am_arovrd PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5856 rbm_m register am_arovrd 0x3F60 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 5761 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 5774 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 5785 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 5796 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 5809 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 5820 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 5831 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 5844 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 5855 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_rbm_m_13_1_am_awovrd bridge_rbm_m_13_1_am_awovrd PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5969 rbm_m register am_awovrd 0x3F68 R/W 0x0000000000000000 Pcie_noc_bridge_rbm_m_13_1_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 5874 awcache_val Value to override incoming ARCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 5887 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 5898 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 5909 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 5922 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 5933 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 5944 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 5957 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 5968 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_version bridge_main0_apb_s_6_6_apbslv_bridge_version PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 5997 main0_apb_s register apbslv_bridge_version 0x4200 R 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_apbslv_bridge_version Bridge version register. false false false false VER PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_SET ns_noc_io_pcie_soc_ip.csr 5986 VER Bridge version. 3 0 0x0 R UNSD_63_4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 5996 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_id bridge_main0_apb_s_6_6_apbslv_bridge_id PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6037 main0_apb_s register apbslv_bridge_id 0x4208 R 0x0000000000000006 Pcie_noc_bridge_main0_apb_s_6_6_apbslv_bridge_id Bridge ID register. false false false false ID PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 6014 ID Unique bridge id. 9 0 0x006 R ZEROES PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_SET ns_noc_io_pcie_soc_ip.csr 6025 ZEROES Zeroes 15 10 0x00 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 6036 UNSD_63_16 Unused 63 16 0x000000000000 R register pcie_noc.bridge_main0_apb_s_6_6_apbslv_slvs_sleep_status bridge_main0_apb_s_6_6_apbslv_slvs_sleep_status PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6246 main0_apb_s register apbslv_slvs_sleep_status 0x4210 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_apbslv_slvs_sleep_status Slave sleep status register. false false false false STS_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_SET ns_noc_io_pcie_soc_ip.csr 6054 STS_0 1'b1: Slave is in sleep mode 1'b0: Slave is active 0 0 0x0 R/W STS_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_SET ns_noc_io_pcie_soc_ip.csr 6066 STS_1 1'b1: Slave is in sleep mode 1'b0: Slave is active 1 1 0x0 R/W STS_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_SET ns_noc_io_pcie_soc_ip.csr 6078 STS_2 1'b1: Slave is in sleep mode 1'b0: Slave is active 2 2 0x0 R/W STS_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_SET ns_noc_io_pcie_soc_ip.csr 6090 STS_3 1'b1: Slave is in sleep mode 1'b0: Slave is active 3 3 0x0 R/W STS_4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_SET ns_noc_io_pcie_soc_ip.csr 6102 STS_4 1'b1: Slave is in sleep mode 1'b0: Slave is active 4 4 0x0 R/W STS_5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_SET ns_noc_io_pcie_soc_ip.csr 6114 STS_5 1'b1: Slave is in sleep mode 1'b0: Slave is active 5 5 0x0 R/W STS_6 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_SET ns_noc_io_pcie_soc_ip.csr 6126 STS_6 1'b1: Slave is in sleep mode 1'b0: Slave is active 6 6 0x0 R/W STS_7 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_SET ns_noc_io_pcie_soc_ip.csr 6138 STS_7 1'b1: Slave is in sleep mode 1'b0: Slave is active 7 7 0x0 R/W STS_8 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_SET ns_noc_io_pcie_soc_ip.csr 6150 STS_8 1'b1: Slave is in sleep mode 1'b0: Slave is active 8 8 0x0 R/W STS_9 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_SET ns_noc_io_pcie_soc_ip.csr 6162 STS_9 1'b1: Slave is in sleep mode 1'b0: Slave is active 9 9 0x0 R/W STS_10 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_SET ns_noc_io_pcie_soc_ip.csr 6174 STS_10 1'b1: Slave is in sleep mode 1'b0: Slave is active 10 10 0x0 R/W STS_11 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_SET ns_noc_io_pcie_soc_ip.csr 6186 STS_11 1'b1: Slave is in sleep mode 1'b0: Slave is active 11 11 0x0 R/W STS_12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_SET ns_noc_io_pcie_soc_ip.csr 6198 STS_12 1'b1: Slave is in sleep mode 1'b0: Slave is active 12 12 0x0 R/W STS_13 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_SET ns_noc_io_pcie_soc_ip.csr 6210 STS_13 1'b1: Slave is in sleep mode 1'b0: Slave is active 13 13 0x0 R/W STS_14 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_SET ns_noc_io_pcie_soc_ip.csr 6222 STS_14 1'b1: Slave is in sleep mode 1'b0: Slave is active 14 14 0x0 R/W STS_15 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_SET ns_noc_io_pcie_soc_ip.csr 6234 STS_15 1'b1: Slave is in sleep mode 1'b0: Slave is active 15 15 0x0 R/W UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 6245 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_cgc bridge_main0_apb_s_6_6_as_cgc PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6283 main0_apb_s register as_cgc 0x5C10 R/W 0x0000000000000064 Pcie_noc_bridge_main0_apb_s_6_6_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 6271 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 6282 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_cgo bridge_main0_apb_s_6_6_as_cgo PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6318 main0_apb_s register as_cgo 0x5C18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 6306 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 6317 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_sts bridge_main0_apb_s_6_6_as_sts PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6392 main0_apb_s register as_sts 0x5D00 R 0x000000000000000c Pcie_noc_bridge_main0_apb_s_6_6_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 6341 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 6357 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 6369 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 6381 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 6391 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_bridge_id bridge_main0_apb_s_6_6_as_bridge_id PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6422 main0_apb_s register as_bridge_id 0x5D08 R 0x0000000000000006 Pcie_noc_bridge_main0_apb_s_6_6_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 6411 ID Unique bridge ID 15 0 0x0006 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 6421 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_err bridge_main0_apb_s_6_6_as_err PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 6775 main0_apb_s register as_err 0x5E00 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 6443 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 6455 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 6468 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 6482 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 6494 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 6505 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 6517 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 6529 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 6542 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 6554 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 6565 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 6577 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 6588 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 6599 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 6610 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 6621 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 6632 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 6643 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 6655 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 6667 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 6679 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 6691 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 6703 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 6715 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 6727 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 6739 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 6751 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 6763 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 6774 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_main0_apb_s_6_6_as_intm bridge_main0_apb_s_6_6_as_intm PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7115 main0_apb_s register as_intm 0x5E40 R/W 0x0000007d000b0013 Pcie_noc_bridge_main0_apb_s_6_6_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 6796 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 6807 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 6818 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 6829 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 6840 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 6851 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 6862 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 6873 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 6884 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 6895 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 6906 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 6917 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 6928 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 6939 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 6950 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 6961 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 6972 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 6983 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 6995 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 7007 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 7019 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 7031 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 7043 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 7055 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 7067 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 7079 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 7091 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 7103 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 7114 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_main0_apb_s_6_6_as_ccmd bridge_main0_apb_s_6_6_as_ccmd PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7190 main0_apb_s register as_ccmd 0x5F00 R/W 0x0000000003000000 Pcie_noc_bridge_main0_apb_s_6_6_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 7133 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 7144 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 7155 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 7166 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 7178 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 7189 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_ccmdmsk bridge_main0_apb_s_6_6_as_ccmdmsk PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7242 main0_apb_s register as_ccmdmsk 0x5F08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 7208 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 7219 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 7230 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 7241 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_cntr bridge_main0_apb_s_6_6_as_cntr PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7272 main0_apb_s register as_cntr 0x5F10 R 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 7261 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 7271 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_arovrd bridge_main0_apb_s_6_6_as_arovrd PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7385 main0_apb_s register as_arovrd 0x5F18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 7290 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 7303 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 7314 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 7325 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 7338 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 7349 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 7360 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 7373 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 7384 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_apb_s_6_6_as_awovrd bridge_main0_apb_s_6_6_as_awovrd PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7498 main0_apb_s register as_awovrd 0x5F20 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 7403 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 7416 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 7427 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 7438 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 7451 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 7462 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 7473 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 7486 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 7497 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_apb_s_6_6_p_0 bridge_main0_apb_s_6_6_p_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7563 main0_apb_s register p_0 0x7000 R/W 0x00000003 Pcie_noc_bridge_main0_apb_s_6_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 7526 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 7538 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 7550 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 7562 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_p_1 bridge_main0_apb_s_6_6_p_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7629 main0_apb_s register p_1 0x7008 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 7592 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 7604 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 7616 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 7628 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_p_2 bridge_main0_apb_s_6_6_p_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7695 main0_apb_s register p_2 0x7010 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 7658 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 7670 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 7682 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 7694 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_p_3 bridge_main0_apb_s_6_6_p_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7761 main0_apb_s register p_3 0x7018 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 7724 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 7736 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 7748 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 7760 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_txe bridge_main0_apb_s_6_6_txe PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7907 main0_apb_s register txe 0x7040 R/W 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 7788 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 7800 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 7815 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 7828 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 7842 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 7856 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 7870 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 7884 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 7895 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 7906 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_apb_s_6_6_txem bridge_main0_apb_s_6_6_txem PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 7986 main0_apb_s register txem 0x7048 R/W 0x00000008 Pcie_noc_bridge_main0_apb_s_6_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 7930 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 7941 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 7952 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 7963 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 7974 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 7985 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_apb_s_6_6_btus_0 bridge_main0_apb_s_6_6_btus_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 8354 main0_apb_s register btus_0 0x7058 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 8012 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 8023 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 8034 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 8045 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 8056 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 8067 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 8078 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 8089 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 8100 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 8111 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 8122 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 8133 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 8144 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 8155 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 8166 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 8177 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 8188 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 8199 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 8210 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 8221 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 8232 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 8243 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 8254 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 8265 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 8276 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 8287 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 8298 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 8309 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 8320 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 8331 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 8342 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 8353 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_main0_apb_s_6_6_btus_1 bridge_main0_apb_s_6_6_btus_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 8722 main0_apb_s register btus_1 0x7060 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 8380 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 8391 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 8402 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 8413 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 8424 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 8435 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 8446 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 8457 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 8468 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 8479 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 8490 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 8501 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 8512 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 8523 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 8534 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 8545 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 8556 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 8567 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 8578 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 8589 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 8600 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 8611 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 8622 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 8633 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 8644 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 8655 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 8666 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 8677 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 8688 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 8699 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 8710 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 8721 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_main0_apb_s_6_6_btrl_0 bridge_main0_apb_s_6_6_btrl_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 8798 main0_apb_s register btrl_0 0x7080 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 8746 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 8757 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 8772 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 8786 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 8797 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_apb_s_6_6_btrl_1 bridge_main0_apb_s_6_6_btrl_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 8874 main0_apb_s register btrl_1 0x7088 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 8822 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 8833 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 8848 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 8862 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 8873 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_apb_s_6_6_btrl_2 bridge_main0_apb_s_6_6_btrl_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 8950 main0_apb_s register btrl_2 0x7090 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 8898 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 8909 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 8924 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 8938 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 8949 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_apb_s_6_6_btrl_3 bridge_main0_apb_s_6_6_btrl_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 9026 main0_apb_s register btrl_3 0x7098 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 8974 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 8985 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 9000 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 9014 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 9025 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_apb_s_6_6_btperr bridge_main0_apb_s_6_6_btperr PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 9228 main0_apb_s register btperr 0x70A8 R/W 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 9051 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 9062 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 9073 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 9084 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 9095 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 9106 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 9117 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 9128 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 9139 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 9150 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 9161 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 9172 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 9183 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 9194 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 9205 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 9216 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 9227 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_apb_s_6_6_btperrm bridge_main0_apb_s_6_6_btperrm PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 9428 main0_apb_s register btperrm 0x70B0 R/W 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 9251 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 9262 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 9273 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 9284 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 9295 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 9306 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 9317 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 9328 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 9339 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 9350 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 9361 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 9372 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 9383 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 9394 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 9405 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 9416 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 9427 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_apb_s_6_6_rxe bridge_main0_apb_s_6_6_rxe PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 9536 main0_apb_s register rxe 0x7120 R/W 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 9456 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 9467 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 9478 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 9489 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 9501 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 9512 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 9524 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 9535 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_apb_s_6_6_rxem bridge_main0_apb_s_6_6_rxem PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 9608 main0_apb_s register rxem 0x7128 R/W 0x00000050 Pcie_noc_bridge_main0_apb_s_6_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 9557 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 9571 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 9582 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 9596 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 9607 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_apb_s_6_6_brs_0 bridge_main0_apb_s_6_6_brs_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 9882 main0_apb_s register brs_0 0x7130 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 9632 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 9643 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 9654 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 9665 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 9676 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 9686 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 9697 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 9708 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 9719 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 9730 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 9741 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 9751 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 9762 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 9773 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 9784 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 9795 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 9806 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 9816 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 9827 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 9838 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 9849 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 9860 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 9871 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 9881 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_apb_s_6_6_brs_1 bridge_main0_apb_s_6_6_brs_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 10156 main0_apb_s register brs_1 0x7138 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 9906 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 9917 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 9928 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 9939 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 9950 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 9960 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 9971 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 9982 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 9993 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 10004 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 10015 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 10025 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 10036 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 10047 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 10058 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 10069 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 10080 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 10090 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 10101 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 10112 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 10123 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 10134 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 10145 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 10155 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_apb_s_6_6_brus bridge_main0_apb_s_6_6_brus PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 10225 main0_apb_s register brus 0x71B0 R 0x00000000 Pcie_noc_bridge_main0_apb_s_6_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 10181 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 10192 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 10203 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 10214 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 10224 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_main0_apb_s_6_6_brperr0 bridge_main0_apb_s_6_6_brperr0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 10453 main0_apb_s register brperr0 0x71D0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 10263 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 10274 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 10285 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 10297 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 10308 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 10319 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 10330 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 10341 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 10352 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 10364 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 10375 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 10386 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 10397 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 10408 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 10419 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 10430 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 10441 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 10452 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_brperr1 bridge_main0_apb_s_6_6_brperr1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 10569 main0_apb_s register brperr1 0x71D8 R 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 10491 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 10502 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 10513 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 10524 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 10535 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 10546 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 10557 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 10568 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_brperrm0 bridge_main0_apb_s_6_6_brperrm0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 10790 main0_apb_s register brperrm0 0x71E0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 10596 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 10608 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 10619 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 10631 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 10643 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 10654 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 10665 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 10677 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 10688 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 10700 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 10712 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 10723 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 10734 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 10745 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 10756 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 10767 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 10778 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 10789 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_apb_s_6_6_brperrm1 bridge_main0_apb_s_6_6_brperrm1 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 10895 main0_apb_s register brperrm1 0x71E8 R 0x0000000000000000 Pcie_noc_bridge_main0_apb_s_6_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 10817 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 10828 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 10839 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 10850 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 10861 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 10872 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 10883 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 10894 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11011 main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x8000 R/W 0x0000000058200000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 10935 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 10946 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 10957 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 10969 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 10980 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 10992 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 11003 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11010 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11103 main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x8008 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 11028 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11039 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 11050 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 11061 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 11073 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 11084 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 11095 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11102 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11219 main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 0x8020 R/W 0x0000000058201000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 11143 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11154 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 11165 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 11177 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 11188 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 11200 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 11211 BASE_ADDRESS_0_33 Base address 39 6 0x001608040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11218 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11311 main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 0x8028 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 11236 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11247 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 11258 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 11269 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 11281 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 11292 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 11303 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11310 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11427 main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 0x8040 R/W 0x0000000058400000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 11351 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11362 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 11373 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 11385 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 11396 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 11408 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 11419 BASE_ADDRESS_0_33 Base address 39 6 0x001610000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11426 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11519 main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 0x8048 R/W 0x000000ffffe00000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 11444 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11455 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 11466 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 11477 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 11489 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 11500 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 11511 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11518 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11635 main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x8060 R/W 0x0000007f80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 11559 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11570 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 11581 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 11593 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 11604 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 11616 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 11627 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11634 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11727 main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x8068 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 11652 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11663 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 11674 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 11685 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 11697 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 11708 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 11719 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11726 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11768 main0_dbg_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x8070 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 11745 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 11756 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 11767 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11884 main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x8080 R/W 0x0000007f80001000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 11808 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11819 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 11830 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 11842 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 11853 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 11865 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 11876 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11883 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 11976 main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x8088 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 11901 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 11912 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 11923 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 11934 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 11946 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 11957 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 11968 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 11975 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12017 main0_dbg_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x8090 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 11994 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 12005 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 12016 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12133 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x80A0 R/W 0x0000000080000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 12057 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12068 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 12079 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 12091 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 12102 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 12114 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 12125 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12132 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12225 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x80A8 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 12150 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12161 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 12172 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 12183 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 12195 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 12206 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 12217 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12224 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12341 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x80C0 R/W 0x0000008000200000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 12265 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12276 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 12287 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 12299 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 12310 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 12322 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 12333 BASE_ADDRESS_0_33 Base address 39 6 0x200008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12340 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12433 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x80C8 R/W 0x000000ffffe00000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 12358 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12369 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 12380 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 12391 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 12403 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 12414 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 12425 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12432 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12549 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x80E0 R/W 0x0000008000400000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 12473 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12484 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 12495 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 12507 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 12518 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 12530 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 12541 BASE_ADDRESS_0_33 Base address 39 6 0x200010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12548 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12641 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x80E8 R/W 0x000000ffffc00000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 12566 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12577 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 12588 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 12599 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 12611 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 12622 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 12633 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12640 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12757 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x8100 R/W 0x0000008000800000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 12681 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12692 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 12703 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 12715 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 12726 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 12738 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 12749 BASE_ADDRESS_0_33 Base address 39 6 0x200020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12756 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12849 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x8108 R/W 0x000000ffff800000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 12774 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12785 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 12796 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 12807 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 12819 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 12830 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 12841 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12848 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 12965 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x8120 R/W 0x0000008001000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 12889 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12900 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 12911 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 12923 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 12934 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 12946 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 12957 BASE_ADDRESS_0_33 Base address 39 6 0x200040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 12964 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13057 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x8128 R/W 0x000000ffff000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 12982 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 12993 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 13004 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 13015 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 13027 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 13038 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 13049 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13056 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13173 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x8140 R/W 0x0000008002000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 13097 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13108 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 13119 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 13131 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 13142 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 13154 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 13165 BASE_ADDRESS_0_33 Base address 39 6 0x200080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13172 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13265 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x8148 R/W 0x000000fffe000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 13190 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13201 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 13212 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 13223 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 13235 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 13246 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 13257 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13264 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13381 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x8160 R/W 0x0000008004000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 13305 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13316 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 13327 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 13339 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 13350 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 13362 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 13373 BASE_ADDRESS_0_33 Base address 39 6 0x200100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13380 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13473 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x8168 R/W 0x000000fffc000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 13398 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13409 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 13420 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 13431 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 13443 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 13454 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 13465 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13472 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13589 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x8180 R/W 0x0000008008000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 13513 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13524 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 13535 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 13547 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 13558 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 13570 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 13581 BASE_ADDRESS_0_33 Base address 39 6 0x200200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13588 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13681 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x8188 R/W 0x000000fff8000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 13606 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13617 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 13628 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 13639 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 13651 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 13662 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 13673 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13680 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13797 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x81A0 R/W 0x0000008010000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 13721 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13732 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 13743 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 13755 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 13766 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 13778 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 13789 BASE_ADDRESS_0_33 Base address 39 6 0x200400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13796 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 13889 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x81A8 R/W 0x000000fff0000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 13814 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13825 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 13836 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 13847 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 13859 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 13870 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 13881 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 13888 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14005 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0x81C0 R/W 0x0000008020000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 13929 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 13940 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 13951 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 13963 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 13974 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 13986 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 13997 BASE_ADDRESS_0_33 Base address 39 6 0x200800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14004 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14097 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0x81C8 R/W 0x000000ffe0000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 14022 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14033 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 14044 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 14055 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 14067 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 14078 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 14089 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14096 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14213 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0x81E0 R/W 0x0000008040000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 14137 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14148 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 14159 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 14171 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 14182 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 14194 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 14205 BASE_ADDRESS_0_33 Base address 39 6 0x201000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14212 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14305 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0x81E8 R/W 0x000000ffc0000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 14230 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14241 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 14252 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 14263 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 14275 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 14286 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 14297 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14304 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14421 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0x8200 R/W 0x0000008080000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 14345 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14356 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 14367 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 14379 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 14390 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 14402 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 14413 BASE_ADDRESS_0_33 Base address 39 6 0x202000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14420 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14513 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0x8208 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 14438 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14449 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 14460 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 14471 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 14483 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 14494 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 14505 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14512 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14629 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0x8220 R/W 0x0000008100000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 14553 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14564 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 14575 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 14587 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 14598 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 14610 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 14621 BASE_ADDRESS_0_33 Base address 39 6 0x204000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14628 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14721 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0x8228 R/W 0x000000ff00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 14646 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14657 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 14668 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 14679 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 14691 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 14702 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 14713 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14720 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14837 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0x8240 R/W 0x0000008200000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 14761 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14772 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 14783 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 14795 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 14806 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 14818 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 14829 BASE_ADDRESS_0_33 Base address 39 6 0x208000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14836 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 14929 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0x8248 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 14854 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14865 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 14876 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 14887 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 14899 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 14910 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 14921 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 14928 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15045 main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0x8260 R/W 0x0000008400000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 14969 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 14980 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 14991 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 15003 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 15014 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 15026 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 15037 BASE_ADDRESS_0_33 Base address 39 6 0x210000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15044 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15137 main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0x8268 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 15062 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15073 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 15084 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 15095 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 15107 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 15118 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 15129 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15136 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15253 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0x8280 R/W 0x0000000002000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 15177 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15188 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 15199 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 15211 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 15222 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 15234 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 15245 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15252 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15345 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0x8288 R/W 0x000000ffffff0000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 15270 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15281 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 15292 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 15303 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 15315 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 15326 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 15337 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15344 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15461 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0x82A0 R/W 0x0000000020007000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 15385 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15396 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 15407 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 15419 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 15430 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 15442 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 15453 BASE_ADDRESS_0_33 Base address 39 6 0x0008001c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15460 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15553 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0x82A8 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 15478 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15489 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 15500 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 15511 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 15523 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 15534 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 15545 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15552 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15669 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0x82C0 R/W 0x0000000030001000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 15593 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15604 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 15615 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 15627 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 15638 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 15650 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 15661 BASE_ADDRESS_0_33 Base address 39 6 0x000c00040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15668 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15761 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0x82C8 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 15686 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15697 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 15708 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 15719 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 15731 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 15742 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 15753 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15760 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15877 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0x82E0 R/W 0x0000000030003000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 15801 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15812 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 15823 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 15835 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 15846 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 15858 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 15869 BASE_ADDRESS_0_33 Base address 39 6 0x000c000c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15876 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 15969 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0x82E8 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 15894 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 15905 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 15916 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 15927 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 15939 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 15950 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 15961 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 15968 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16085 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0x8300 R/W 0x0000000030008000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 16009 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16020 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 16031 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 16043 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 16054 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 16066 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 16077 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16084 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16177 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0x8308 R/W 0x000000ffffffe000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 16102 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16113 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 16124 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 16135 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 16147 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 16158 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 16169 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16176 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16293 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0x8320 R/W 0x0000000100000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 16217 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16228 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 16239 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 16251 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 16262 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 16274 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 16285 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16292 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16385 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0x8328 R/W 0x000000ff00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 16310 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16321 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 16332 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 16343 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 16355 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 16366 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 16377 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16384 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16501 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0x8340 R/W 0x000000c000200000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 16425 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16436 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 16447 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 16459 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 16470 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 16482 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 16493 BASE_ADDRESS_0_33 Base address 39 6 0x300008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16500 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16593 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0x8348 R/W 0x000000ffffe00000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 16518 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16529 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 16540 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 16551 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 16563 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 16574 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 16585 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16592 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16709 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0x8360 R/W 0x000000c000400000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 16633 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16644 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 16655 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 16667 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 16678 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 16690 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 16701 BASE_ADDRESS_0_33 Base address 39 6 0x300010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16708 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16801 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0x8368 R/W 0x000000ffffc00000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 16726 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16737 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 16748 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 16759 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 16771 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 16782 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 16793 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16800 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 16917 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0x8380 R/W 0x000000c000800000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 16841 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16852 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 16863 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 16875 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 16886 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 16898 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 16909 BASE_ADDRESS_0_33 Base address 39 6 0x300020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 16916 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17009 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0x8388 R/W 0x000000ffff800000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 16934 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 16945 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 16956 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 16967 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 16979 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 16990 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 17001 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17008 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17125 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0x83A0 R/W 0x000000c001000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 17049 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17060 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 17071 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 17083 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 17094 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 17106 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 17117 BASE_ADDRESS_0_33 Base address 39 6 0x300040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17124 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17217 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0x83A8 R/W 0x000000ffff000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 17142 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17153 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 17164 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 17175 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 17187 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 17198 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 17209 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17216 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17333 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0x83C0 R/W 0x000000c002000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 17257 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17268 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 17279 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 17291 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 17302 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 17314 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 17325 BASE_ADDRESS_0_33 Base address 39 6 0x300080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17332 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17425 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0x83C8 R/W 0x000000fffe000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 17350 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17361 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 17372 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 17383 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 17395 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 17406 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 17417 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17424 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17541 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0x83E0 R/W 0x000000c004000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 17465 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17476 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 17487 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 17499 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 17510 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 17522 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 17533 BASE_ADDRESS_0_33 Base address 39 6 0x300100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17540 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17633 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0x83E8 R/W 0x000000fffc000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 17558 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17569 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 17580 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 17591 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 17603 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 17614 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 17625 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17632 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17749 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0x8400 R/W 0x000000c008000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 17673 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17684 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 17695 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 17707 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 17718 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 17730 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 17741 BASE_ADDRESS_0_33 Base address 39 6 0x300200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17748 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17841 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0x8408 R/W 0x000000fff8000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 17766 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17777 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 17788 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 17799 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 17811 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 17822 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 17833 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17840 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 17957 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x8420 R/W 0x000000c010000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 17881 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17892 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 17903 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 17915 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 17926 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 17938 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 17949 BASE_ADDRESS_0_33 Base address 39 6 0x300400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 17956 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18049 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x8428 R/W 0x000000fff0000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 17974 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 17985 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 17996 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 18007 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 18019 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 18030 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 18041 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18048 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18165 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x8440 R/W 0x000000c020000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 18089 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18100 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 18111 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 18123 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 18134 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 18146 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 18157 BASE_ADDRESS_0_33 Base address 39 6 0x300800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18164 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18257 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x8448 R/W 0x000000ffe0000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 18182 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18193 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 18204 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 18215 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 18227 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 18238 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 18249 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18256 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18373 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x8460 R/W 0x000000c040000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 18297 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18308 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 18319 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 18331 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SET ns_noc_io_pcie_soc_ip.csr 18342 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 18354 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 18365 BASE_ADDRESS_0_33 Base address 39 6 0x301000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18372 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18465 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x8468 R/W 0x000000ffc0000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 18390 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18401 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 18412 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 18423 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SET ns_noc_io_pcie_soc_ip.csr 18435 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 18446 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 18457 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18464 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18581 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x8480 R/W 0x000000c080000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 18505 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18516 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 18527 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 18539 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SET ns_noc_io_pcie_soc_ip.csr 18550 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 18562 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 18573 BASE_ADDRESS_0_33 Base address 39 6 0x302000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18580 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18673 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x8488 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 18598 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18609 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 18620 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 18631 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SET ns_noc_io_pcie_soc_ip.csr 18643 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 18654 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 18665 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18672 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18789 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x84A0 R/W 0x000000c100000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 18713 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18724 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 18735 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 18747 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SET ns_noc_io_pcie_soc_ip.csr 18758 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 18770 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 18781 BASE_ADDRESS_0_33 Base address 39 6 0x304000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18788 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18881 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x84A8 R/W 0x000000ff00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 18806 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18817 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 18828 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 18839 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SET ns_noc_io_pcie_soc_ip.csr 18851 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 18862 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 18873 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18880 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 18997 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x84C0 R/W 0x000000c200000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 18921 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 18932 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 18943 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 18955 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SET ns_noc_io_pcie_soc_ip.csr 18966 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 18978 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 18989 BASE_ADDRESS_0_33 Base address 39 6 0x308000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 18996 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19089 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x84C8 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 19014 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19025 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 19036 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 19047 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SET ns_noc_io_pcie_soc_ip.csr 19059 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 19070 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 19081 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19088 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19205 main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x84E0 R/W 0x000000c400000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 19129 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19140 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 19151 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 19163 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SET ns_noc_io_pcie_soc_ip.csr 19174 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 19186 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 19197 BASE_ADDRESS_0_33 Base address 39 6 0x310000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19204 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19297 main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x84E8 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 19222 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19233 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 19244 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 19255 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SET ns_noc_io_pcie_soc_ip.csr 19267 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 19278 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 19289 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19296 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19413 main0_dbg_m register am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x8500 R/W 0x0000007e80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 19337 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19348 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 19359 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 19371 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 19382 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 19394 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 19405 BASE_ADDRESS_0_33 Base address 39 6 0x1fa000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19412 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19505 main0_dbg_m register am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x8508 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 19430 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19441 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 19452 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 19463 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 19475 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 19486 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 19497 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19504 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19546 main0_dbg_m register am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x8510 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 19523 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 19534 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 19545 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19662 main0_dbg_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x8520 R/W 0x0000004000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 19586 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19597 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 19608 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 19620 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 19631 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 19643 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 19654 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19661 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19754 main0_dbg_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x8528 R/W 0x000000e000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 19679 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19690 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 19701 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 19712 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 19724 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 19735 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 19746 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19753 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19870 main0_dbg_m register am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x8540 R/W 0x0000007f00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 19794 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19805 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 19816 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 19828 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 19839 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 19851 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 19862 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19869 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 19962 main0_dbg_m register am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x8548 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 19887 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 19898 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 19909 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 19920 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 19932 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 19943 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 19954 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 19961 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20003 main0_dbg_m register am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x8550 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 19980 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 19991 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 20002 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20119 main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x8560 R/W 0x0000006000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 20043 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20054 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 20065 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 20077 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 20088 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 20100 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 20111 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20118 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20211 main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x8568 R/W 0x000000f000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 20136 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20147 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 20158 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 20169 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 20181 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 20192 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 20203 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20210 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20327 main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x8580 R/W 0x0000007000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 20251 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20262 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 20273 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 20285 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 20296 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 20308 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 20319 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20326 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20419 main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x8588 R/W 0x000000f800000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 20344 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20355 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 20366 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 20377 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 20389 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 20400 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 20411 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20418 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20535 main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x85A0 R/W 0x0000007800000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 20459 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20470 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 20481 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 20493 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 20504 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 20516 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 20527 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20534 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20627 main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x85A8 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 20552 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20563 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 20574 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 20585 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 20597 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 20608 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 20619 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20626 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20743 main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x85C0 R/W 0x0000007c00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 20667 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20678 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 20689 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 20701 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 20712 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 20724 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 20735 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20742 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20835 main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x85C8 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 20760 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20771 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 20782 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 20793 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 20805 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 20816 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 20827 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20834 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 20951 main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x85E0 R/W 0x0000007e00000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 20875 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20886 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 20897 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 20909 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 20920 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 20932 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 20943 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 20950 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21043 main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x85E8 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 20968 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 20979 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 20990 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 21001 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 21013 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 21024 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 21035 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 21042 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_p_0 bridge_main0_dbg_m_0_9_p_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21108 main0_dbg_m register p_0 0xB000 R/W 0x00000003 Pcie_noc_bridge_main0_dbg_m_0_9_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 21071 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 21083 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 21095 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 21107 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_p_1 bridge_main0_dbg_m_0_9_p_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21174 main0_dbg_m register p_1 0xB008 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 21137 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 21149 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 21161 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 21173 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_p_2 bridge_main0_dbg_m_0_9_p_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21240 main0_dbg_m register p_2 0xB010 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 21203 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 21215 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 21227 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 21239 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_p_3 bridge_main0_dbg_m_0_9_p_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21306 main0_dbg_m register p_3 0xB018 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 21269 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 21281 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 21293 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 21305 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_txe bridge_main0_dbg_m_0_9_txe PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21452 main0_dbg_m register txe 0xB040 R/W 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 21333 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 21345 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 21360 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 21373 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 21387 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 21401 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 21415 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 21429 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 21440 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 21451 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_txem bridge_main0_dbg_m_0_9_txem PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21531 main0_dbg_m register txem 0xB048 R/W 0x00000008 Pcie_noc_bridge_main0_dbg_m_0_9_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 21475 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 21486 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 21497 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 21508 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 21519 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 21530 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_dbg_m_0_9_btus_0 bridge_main0_dbg_m_0_9_btus_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 21899 main0_dbg_m register btus_0 0xB058 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 21557 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 21568 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 21579 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 21590 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 21601 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 21612 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 21623 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 21634 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 21645 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 21656 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 21667 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 21678 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 21689 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 21700 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 21711 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 21722 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 21733 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 21744 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 21755 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 21766 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 21777 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 21788 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 21799 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 21810 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 21821 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 21832 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 21843 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 21854 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 21865 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 21876 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 21887 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 21898 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_main0_dbg_m_0_9_btus_1 bridge_main0_dbg_m_0_9_btus_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22267 main0_dbg_m register btus_1 0xB060 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 21925 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 21936 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 21947 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 21958 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 21969 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 21980 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 21991 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 22002 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 22013 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 22024 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 22035 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 22046 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 22057 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 22068 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 22079 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 22090 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 22101 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 22112 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 22123 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 22134 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 22145 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 22156 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 22167 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 22178 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 22189 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 22200 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 22211 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 22222 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 22233 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 22244 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 22255 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 22266 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_main0_dbg_m_0_9_btrl_0 bridge_main0_dbg_m_0_9_btrl_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22343 main0_dbg_m register btrl_0 0xB080 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 22291 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 22302 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 22317 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 22331 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 22342 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_dbg_m_0_9_btrl_1 bridge_main0_dbg_m_0_9_btrl_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22419 main0_dbg_m register btrl_1 0xB088 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 22367 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 22378 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 22393 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 22407 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 22418 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_dbg_m_0_9_btrl_2 bridge_main0_dbg_m_0_9_btrl_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22495 main0_dbg_m register btrl_2 0xB090 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 22443 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 22454 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 22469 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 22483 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 22494 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_dbg_m_0_9_btrl_3 bridge_main0_dbg_m_0_9_btrl_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22571 main0_dbg_m register btrl_3 0xB098 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 22519 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 22530 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 22545 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 22559 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 22570 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_dbg_m_0_9_btperr bridge_main0_dbg_m_0_9_btperr PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22773 main0_dbg_m register btperr 0xB0A8 R/W 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 22596 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 22607 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 22618 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 22629 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 22640 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 22651 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 22662 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 22673 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 22684 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 22695 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 22706 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 22717 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 22728 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 22739 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 22750 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 22761 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 22772 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_dbg_m_0_9_btperrm bridge_main0_dbg_m_0_9_btperrm PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 22973 main0_dbg_m register btperrm 0xB0B0 R/W 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 22796 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 22807 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 22818 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 22829 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 22840 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 22851 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 22862 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 22873 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 22884 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 22895 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 22906 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 22917 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 22928 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 22939 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 22950 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 22961 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 22972 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_dbg_m_0_9_rxe bridge_main0_dbg_m_0_9_rxe PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 23081 main0_dbg_m register rxe 0xB120 R/W 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 23001 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 23012 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 23023 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 23034 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 23046 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 23057 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 23069 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 23080 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_dbg_m_0_9_rxem bridge_main0_dbg_m_0_9_rxem PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 23153 main0_dbg_m register rxem 0xB128 R/W 0x00000050 Pcie_noc_bridge_main0_dbg_m_0_9_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 23102 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 23116 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 23127 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 23141 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 23152 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_dbg_m_0_9_brs_0 bridge_main0_dbg_m_0_9_brs_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 23427 main0_dbg_m register brs_0 0xB130 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 23177 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 23188 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 23199 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 23210 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 23221 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 23231 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 23242 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 23253 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 23264 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 23275 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 23286 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 23296 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 23307 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 23318 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 23329 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 23340 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 23351 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 23361 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 23372 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 23383 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 23394 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 23405 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 23416 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 23426 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_dbg_m_0_9_brs_1 bridge_main0_dbg_m_0_9_brs_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 23701 main0_dbg_m register brs_1 0xB138 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 23451 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 23462 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 23473 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 23484 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 23495 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 23505 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 23516 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 23527 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 23538 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 23549 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 23560 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 23570 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 23581 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 23592 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 23603 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 23614 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 23625 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 23635 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 23646 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 23657 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 23668 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 23679 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 23690 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 23700 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_dbg_m_0_9_brus bridge_main0_dbg_m_0_9_brus PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 23770 main0_dbg_m register brus 0xB1B0 R 0x00000000 Pcie_noc_bridge_main0_dbg_m_0_9_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 23726 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 23737 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 23748 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 23759 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 23769 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_main0_dbg_m_0_9_brperr0 bridge_main0_dbg_m_0_9_brperr0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 23998 main0_dbg_m register brperr0 0xB1D0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 23808 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 23819 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 23830 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 23842 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 23853 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 23864 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 23875 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 23886 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 23897 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 23909 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 23920 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 23931 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 23942 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 23953 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 23964 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 23975 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 23986 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 23997 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_brperr1 bridge_main0_dbg_m_0_9_brperr1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24114 main0_dbg_m register brperr1 0xB1D8 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 24036 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 24047 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 24058 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 24069 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 24080 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 24091 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 24102 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 24113 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_brperrm0 bridge_main0_dbg_m_0_9_brperrm0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24335 main0_dbg_m register brperrm0 0xB1E0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 24141 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 24153 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 24164 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 24176 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 24188 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 24199 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 24210 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 24222 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 24233 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 24245 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 24257 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 24268 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 24279 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 24290 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 24301 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 24312 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 24323 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 24334 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_brperrm1 bridge_main0_dbg_m_0_9_brperrm1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24440 main0_dbg_m register brperrm1 0xB1E8 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 24362 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 24373 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 24384 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 24395 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 24406 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 24417 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 24428 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 24439 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_am_tocfg bridge_main0_dbg_m_0_9_am_tocfg PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24514 main0_dbg_m register am_tocfg 0xBC00 R/W 0x000000000000001f Pcie_noc_bridge_main0_dbg_m_0_9_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 24477 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 24488 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 24502 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 24513 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_osslv bridge_main0_dbg_m_0_9_am_osslv PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24549 main0_dbg_m register am_osslv 0xBC08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 24537 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 24548 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_cgc bridge_main0_dbg_m_0_9_am_cgc PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24586 main0_dbg_m register am_cgc 0xBC10 R/W 0x0000000000000064 Pcie_noc_bridge_main0_dbg_m_0_9_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 24574 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 24585 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_cgo bridge_main0_dbg_m_0_9_am_cgo PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24621 main0_dbg_m register am_cgo 0xBC18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 24609 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 24620 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_cfg bridge_main0_dbg_m_0_9_am_cfg PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24658 main0_dbg_m register am_cfg 0xBC20 R/W 0x0000000000000001 Pcie_noc_bridge_main0_dbg_m_0_9_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 24646 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 24657 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_sts bridge_main0_dbg_m_0_9_am_sts PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24786 main0_dbg_m register am_sts 0xBD00 R 0x000000000000000c Pcie_noc_bridge_main0_dbg_m_0_9_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 24691 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 24705 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 24717 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 24729 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 24740 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 24751 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 24763 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 24775 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 24785 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_bridge_id bridge_main0_dbg_m_0_9_am_bridge_id PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 24816 main0_dbg_m register am_bridge_id 0xBD08 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 24805 ID Unique bridge ID 15 0 0x0000 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 24815 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_err bridge_main0_dbg_m_0_9_am_err PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25312 main0_dbg_m register am_err 0xBE00 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 24838 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 24850 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 24862 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 24874 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 24886 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 24898 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 24911 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 24924 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 24935 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 24946 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 24957 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 24968 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 24979 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 24990 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 25001 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 25012 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 25023 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 25035 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 25046 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 25057 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 25068 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 25079 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 25091 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 25103 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 25114 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 25126 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 25137 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 25148 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 25159 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 25170 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 25181 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 25192 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 25204 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 25216 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 25228 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 25240 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 25252 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 25264 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 25276 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 25288 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 25300 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 25311 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_am_toslvid bridge_main0_dbg_m_0_9_am_toslvid PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25357 main0_dbg_m register am_toslvid 0xBE08 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 25335 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 25346 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 25356 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_era bridge_main0_dbg_m_0_9_am_era PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25379 main0_dbg_m register am_era 0xBE10 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 25378 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_ewa bridge_main0_dbg_m_0_9_am_ewa PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25401 main0_dbg_m register am_ewa 0xBE18 R 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 25400 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_intm bridge_main0_dbg_m_0_9_am_intm PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25885 main0_dbg_m register am_intm 0xBE40 R/W 0x00007e07004f004f Pcie_noc_bridge_main0_dbg_m_0_9_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 25423 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 25434 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 25445 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 25456 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 25467 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 25478 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 25489 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 25500 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 25511 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 25522 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 25533 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 25544 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 25555 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 25566 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 25577 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 25588 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 25599 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 25610 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 25621 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 25632 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 25643 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 25654 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 25665 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 25676 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 25687 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 25699 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 25710 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 25721 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 25732 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 25743 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 25754 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 25765 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 25777 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 25789 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 25801 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 25813 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 25825 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 25837 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 25849 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 25861 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 25873 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 25884 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_dbg_m_0_9_am_caddr bridge_main0_dbg_m_0_9_am_caddr PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25907 main0_dbg_m register am_caddr 0xBF00 R/W 0xffffffffffffffff Pcie_noc_bridge_main0_dbg_m_0_9_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 25906 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_main0_dbg_m_0_9_am_caddrmsk bridge_main0_dbg_m_0_9_am_caddrmsk PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 25930 main0_dbg_m register am_caddrmsk 0xBF08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 25929 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd0 bridge_main0_dbg_m_0_9_am_ccmd0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26120 main0_dbg_m register am_ccmd0 0xBF10 R/W 0x0000000003fff33f Pcie_noc_bridge_main0_dbg_m_0_9_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 25952 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 25963 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 25974 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 25985 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 25996 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 26007 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 26018 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 26029 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 26040 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 26051 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 26062 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 26073 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 26085 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 26096 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 26108 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 26119 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk0 bridge_main0_dbg_m_0_9_am_ccmdmsk0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26264 main0_dbg_m register am_ccmdmsk0 0xBF18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 26142 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 26153 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 26164 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 26175 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 26186 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 26197 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 26208 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 26219 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 26230 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 26241 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 26252 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 26263 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_cntr0 bridge_main0_dbg_m_0_9_am_cntr0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26299 main0_dbg_m register am_cntr0 0xBF20 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 26287 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 26298 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_latnum0 bridge_main0_dbg_m_0_9_am_latnum0 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26338 main0_dbg_m register am_latnum0 0xBF28 R/W 0x0000000000000007 Pcie_noc_bridge_main0_dbg_m_0_9_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 26326 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 26337 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmd1 bridge_main0_dbg_m_0_9_am_ccmd1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26528 main0_dbg_m register am_ccmd1 0xBF30 R/W 0x0000000003fff33f Pcie_noc_bridge_main0_dbg_m_0_9_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 26360 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 26371 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 26382 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 26393 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 26404 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 26415 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 26426 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 26437 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 26448 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 26459 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 26470 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 26481 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 26493 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 26504 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 26516 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 26527 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk1 bridge_main0_dbg_m_0_9_am_ccmdmsk1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26672 main0_dbg_m register am_ccmdmsk1 0xBF38 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 26550 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 26561 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 26572 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 26583 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 26594 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 26605 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 26616 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 26627 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 26638 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 26649 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 26660 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 26671 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_cntr1 bridge_main0_dbg_m_0_9_am_cntr1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26707 main0_dbg_m register am_cntr1 0xBF40 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 26695 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 26706 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_latnum1 bridge_main0_dbg_m_0_9_am_latnum1 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26746 main0_dbg_m register am_latnum1 0xBF48 R/W 0x0000000000000007 Pcie_noc_bridge_main0_dbg_m_0_9_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 26734 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 26745 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_arovrd bridge_main0_dbg_m_0_9_am_arovrd PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26859 main0_dbg_m register am_arovrd 0xBF60 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 26764 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 26777 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 26788 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 26799 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 26812 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 26823 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 26834 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 26847 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 26858 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_dbg_m_0_9_am_awovrd bridge_main0_dbg_m_0_9_am_awovrd PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 26972 main0_dbg_m register am_awovrd 0xBF68 R/W 0x0000000000000000 Pcie_noc_bridge_main0_dbg_m_0_9_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 26877 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 26890 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 26901 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 26912 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 26925 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 26936 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 26947 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 26960 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 26971 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27088 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0xC000 R/W 0x0000000080000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 27012 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27023 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 27034 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 27046 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 27057 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 27069 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 27080 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27087 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27180 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0xC008 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 27105 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27116 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 27127 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 27138 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 27150 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 27161 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 27172 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27179 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27296 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0xC020 R/W 0x0000008000200000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 27220 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27231 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 27242 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 27254 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 27265 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 27277 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 27288 BASE_ADDRESS_0_33 Base address 39 6 0x200008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27295 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27388 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0xC028 R/W 0x000000ffffe00000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 27313 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27324 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 27335 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 27346 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 27358 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 27369 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 27380 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27387 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27504 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0xC040 R/W 0x0000008000400000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 27428 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27439 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 27450 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 27462 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 27473 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 27485 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 27496 BASE_ADDRESS_0_33 Base address 39 6 0x200010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27503 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27596 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0xC048 R/W 0x000000ffffc00000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 27521 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27532 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 27543 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 27554 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 27566 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 27577 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 27588 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27595 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27712 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0xC060 R/W 0x0000008000800000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 27636 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27647 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 27658 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 27670 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 27681 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 27693 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 27704 BASE_ADDRESS_0_33 Base address 39 6 0x200020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27711 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27804 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0xC068 R/W 0x000000ffff800000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 27729 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27740 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 27751 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 27762 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 27774 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 27785 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 27796 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27803 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 27920 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0xC080 R/W 0x0000008001000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 27844 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27855 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 27866 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 27878 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 27889 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 27901 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 27912 BASE_ADDRESS_0_33 Base address 39 6 0x200040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 27919 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28012 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0xC088 R/W 0x000000ffff000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 27937 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 27948 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 27959 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 27970 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 27982 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 27993 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 28004 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28011 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28128 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0xC0A0 R/W 0x0000008002000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 28052 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28063 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 28074 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 28086 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 28097 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 28109 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 28120 BASE_ADDRESS_0_33 Base address 39 6 0x200080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28127 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28220 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0xC0A8 R/W 0x000000fffe000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 28145 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28156 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 28167 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 28178 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 28190 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 28201 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 28212 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28219 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28336 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0xC0C0 R/W 0x0000008004000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 28260 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28271 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 28282 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 28294 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 28305 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 28317 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 28328 BASE_ADDRESS_0_33 Base address 39 6 0x200100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28335 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28428 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0xC0C8 R/W 0x000000fffc000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 28353 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28364 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 28375 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 28386 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 28398 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 28409 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 28420 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28427 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28544 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0xC0E0 R/W 0x0000008008000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 28468 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28479 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 28490 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 28502 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 28513 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 28525 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 28536 BASE_ADDRESS_0_33 Base address 39 6 0x200200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28543 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28636 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0xC0E8 R/W 0x000000fff8000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 28561 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28572 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 28583 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 28594 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 28606 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 28617 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 28628 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28635 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28752 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0xC100 R/W 0x0000008010000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 28676 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28687 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 28698 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 28710 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 28721 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 28733 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 28744 BASE_ADDRESS_0_33 Base address 39 6 0x200400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28751 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28844 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0xC108 R/W 0x000000fff0000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 28769 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28780 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 28791 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 28802 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 28814 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 28825 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 28836 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28843 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 28960 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0xC120 R/W 0x0000008020000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 28884 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28895 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 28906 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 28918 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 28929 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 28941 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 28952 BASE_ADDRESS_0_33 Base address 39 6 0x200800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 28959 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29052 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0xC128 R/W 0x000000ffe0000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 28977 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 28988 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 28999 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 29010 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 29022 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 29033 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 29044 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29051 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29168 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0xC140 R/W 0x0000008040000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 29092 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29103 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 29114 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 29126 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 29137 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 29149 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 29160 BASE_ADDRESS_0_33 Base address 39 6 0x201000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29167 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29260 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0xC148 R/W 0x000000ffc0000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 29185 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29196 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 29207 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 29218 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 29230 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 29241 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 29252 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29259 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29376 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0xC160 R/W 0x0000008080000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 29300 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29311 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 29322 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 29334 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 29345 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 29357 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 29368 BASE_ADDRESS_0_33 Base address 39 6 0x202000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29375 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29468 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0xC168 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 29393 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29404 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 29415 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 29426 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 29438 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 29449 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 29460 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29467 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29584 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0xC180 R/W 0x0000008100000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 29508 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29519 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 29530 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 29542 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 29553 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 29565 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 29576 BASE_ADDRESS_0_33 Base address 39 6 0x204000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29583 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29676 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0xC188 R/W 0x000000ff00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 29601 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29612 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 29623 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 29634 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 29646 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 29657 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 29668 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29675 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29792 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0xC1A0 R/W 0x0000008200000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 29716 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29727 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 29738 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 29750 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 29761 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 29773 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 29784 BASE_ADDRESS_0_33 Base address 39 6 0x208000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29791 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 29884 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0xC1A8 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 29809 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29820 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 29831 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 29842 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 29854 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 29865 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 29876 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29883 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30000 main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0xC1C0 R/W 0x0000008400000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 29924 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 29935 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 29946 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 29958 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 29969 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 29981 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 29992 BASE_ADDRESS_0_33 Base address 39 6 0x210000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 29999 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30092 main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0xC1C8 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 30017 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30028 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 30039 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 30050 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 30062 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 30073 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 30084 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30091 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30208 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0xC1E0 R/W 0x0000000002000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 30132 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30143 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 30154 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 30166 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 30177 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 30189 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 30200 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30207 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30300 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0xC1E8 R/W 0x000000ffffff0000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 30225 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30236 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 30247 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 30258 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 30270 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 30281 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 30292 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30299 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30416 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0xC200 R/W 0x0000000020007000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 30340 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30351 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 30362 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 30374 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 30385 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 30397 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 30408 BASE_ADDRESS_0_33 Base address 39 6 0x0008001c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30415 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30508 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0xC208 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 30433 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30444 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 30455 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 30466 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 30478 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 30489 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 30500 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30507 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30624 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0xC220 R/W 0x0000000030001000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 30548 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30559 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 30570 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 30582 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 30593 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 30605 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 30616 BASE_ADDRESS_0_33 Base address 39 6 0x000c00040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30623 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30716 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0xC228 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 30641 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30652 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 30663 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 30674 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 30686 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 30697 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 30708 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30715 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30832 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0xC240 R/W 0x0000000030003000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 30756 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30767 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 30778 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 30790 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 30801 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 30813 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 30824 BASE_ADDRESS_0_33 Base address 39 6 0x000c000c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30831 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 30924 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0xC248 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 30849 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30860 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 30871 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 30882 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 30894 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 30905 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 30916 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 30923 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31040 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0xC260 R/W 0x0000000030008000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 30964 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 30975 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 30986 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 30998 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 31009 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 31021 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 31032 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31039 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31132 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0xC268 R/W 0x000000ffffffe000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 31057 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31068 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 31079 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 31090 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 31102 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 31113 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 31124 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31131 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31248 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0xC280 R/W 0x0000000100000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 31172 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31183 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 31194 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 31206 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 31217 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 31229 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 31240 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31247 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31340 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0xC288 R/W 0x000000ff00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 31265 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31276 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 31287 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 31298 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 31310 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 31321 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 31332 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31339 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31456 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0xC2A0 R/W 0x000000c000200010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 31380 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31391 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 31402 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 31414 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 31425 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 31437 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 31448 BASE_ADDRESS_0_33 Base address 39 6 0x300008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31455 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31548 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0xC2A8 R/W 0x000000ffffe00000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 31473 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31484 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 31495 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 31506 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 31518 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 31529 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 31540 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31547 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31664 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0xC2C0 R/W 0x000000c000400010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 31588 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31599 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 31610 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 31622 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 31633 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 31645 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 31656 BASE_ADDRESS_0_33 Base address 39 6 0x300010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31663 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31756 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0xC2C8 R/W 0x000000ffffc00000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 31681 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31692 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 31703 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 31714 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 31726 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 31737 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 31748 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31755 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31872 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0xC2E0 R/W 0x000000c000800010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 31796 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31807 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 31818 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 31830 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 31841 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 31853 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 31864 BASE_ADDRESS_0_33 Base address 39 6 0x300020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31871 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 31964 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0xC2E8 R/W 0x000000ffff800000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 31889 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 31900 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 31911 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 31922 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 31934 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 31945 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 31956 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 31963 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32080 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0xC300 R/W 0x000000c001000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 32004 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32015 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 32026 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 32038 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 32049 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 32061 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 32072 BASE_ADDRESS_0_33 Base address 39 6 0x300040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32079 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32172 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0xC308 R/W 0x000000ffff000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 32097 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32108 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 32119 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 32130 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 32142 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 32153 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 32164 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32171 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32288 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0xC320 R/W 0x000000c002000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 32212 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32223 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 32234 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 32246 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 32257 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 32269 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 32280 BASE_ADDRESS_0_33 Base address 39 6 0x300080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32287 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32380 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0xC328 R/W 0x000000fffe000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 32305 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32316 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 32327 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 32338 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 32350 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 32361 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 32372 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32379 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32496 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0xC340 R/W 0x000000c004000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 32420 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32431 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 32442 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 32454 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 32465 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 32477 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 32488 BASE_ADDRESS_0_33 Base address 39 6 0x300100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32495 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32588 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0xC348 R/W 0x000000fffc000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 32513 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32524 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 32535 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 32546 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 32558 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 32569 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 32580 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32587 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32704 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0xC360 R/W 0x000000c008000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 32628 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32639 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 32650 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 32662 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 32673 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 32685 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 32696 BASE_ADDRESS_0_33 Base address 39 6 0x300200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32703 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32796 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0xC368 R/W 0x000000fff8000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 32721 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32732 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 32743 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 32754 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 32766 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 32777 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 32788 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32795 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 32912 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0xC380 R/W 0x000000c010000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 32836 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32847 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 32858 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 32870 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 32881 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 32893 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 32904 BASE_ADDRESS_0_33 Base address 39 6 0x300400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 32911 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33004 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0xC388 R/W 0x000000fff0000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 32929 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 32940 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 32951 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 32962 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 32974 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 32985 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 32996 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33003 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33120 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0xC3A0 R/W 0x000000c020000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 33044 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33055 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 33066 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 33078 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 33089 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 33101 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 33112 BASE_ADDRESS_0_33 Base address 39 6 0x300800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33119 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33212 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0xC3A8 R/W 0x000000ffe0000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 33137 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33148 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 33159 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 33170 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 33182 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 33193 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 33204 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33211 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33328 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0xC3C0 R/W 0x000000c040000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 33252 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33263 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 33274 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 33286 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SET ns_noc_io_pcie_soc_ip.csr 33297 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 33309 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 33320 BASE_ADDRESS_0_33 Base address 39 6 0x301000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33327 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33420 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0xC3C8 R/W 0x000000ffc0000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 33345 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33356 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 33367 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 33378 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SET ns_noc_io_pcie_soc_ip.csr 33390 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 33401 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 33412 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33419 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33536 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0xC3E0 R/W 0x000000c080000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 33460 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33471 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 33482 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 33494 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SET ns_noc_io_pcie_soc_ip.csr 33505 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 33517 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 33528 BASE_ADDRESS_0_33 Base address 39 6 0x302000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33535 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33628 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0xC3E8 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 33553 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33564 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 33575 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 33586 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SET ns_noc_io_pcie_soc_ip.csr 33598 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 33609 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 33620 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33627 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33744 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0xC400 R/W 0x000000c100000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 33668 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33679 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 33690 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 33702 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SET ns_noc_io_pcie_soc_ip.csr 33713 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 33725 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 33736 BASE_ADDRESS_0_33 Base address 39 6 0x304000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33743 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33836 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0xC408 R/W 0x000000ff00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 33761 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33772 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 33783 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 33794 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SET ns_noc_io_pcie_soc_ip.csr 33806 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 33817 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 33828 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33835 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 33952 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0xC420 R/W 0x000000c200000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 33876 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33887 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 33898 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 33910 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SET ns_noc_io_pcie_soc_ip.csr 33921 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 33933 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 33944 BASE_ADDRESS_0_33 Base address 39 6 0x308000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 33951 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34044 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0xC428 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 33969 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 33980 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 33991 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 34002 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SET ns_noc_io_pcie_soc_ip.csr 34014 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 34025 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 34036 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34043 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34160 main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0xC440 R/W 0x000000c400000010 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 34084 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34095 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 34106 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 34118 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SET ns_noc_io_pcie_soc_ip.csr 34129 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 34141 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 34152 BASE_ADDRESS_0_33 Base address 39 6 0x310000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34159 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34252 main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0xC448 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 34177 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34188 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 34199 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 34210 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SET ns_noc_io_pcie_soc_ip.csr 34222 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 34233 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 34244 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34251 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34368 main0_esr_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0xC460 R/W 0x0000004000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 34292 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34303 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 34314 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 34326 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 34337 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 34349 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 34360 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34367 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34460 main0_esr_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0xC468 R/W 0x000000e000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 34385 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34396 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 34407 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 34418 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 34430 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 34441 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 34452 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34459 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34576 main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0xC480 R/W 0x0000006000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 34500 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34511 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 34522 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 34534 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 34545 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 34557 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 34568 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34575 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34668 main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0xC488 R/W 0x000000f000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 34593 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34604 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 34615 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 34626 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 34638 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 34649 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 34660 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34667 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34784 main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0xC4A0 R/W 0x0000007000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 34708 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34719 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 34730 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 34742 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 34753 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 34765 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 34776 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34783 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34876 main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0xC4A8 R/W 0x000000f800000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 34801 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34812 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 34823 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 34834 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 34846 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 34857 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 34868 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34875 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 34992 main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0xC4C0 R/W 0x0000007800000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 34916 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 34927 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 34938 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 34950 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 34961 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 34973 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 34984 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 34991 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35084 main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0xC4C8 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 35009 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 35020 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 35031 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 35042 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 35054 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 35065 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 35076 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 35083 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35200 main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0xC4E0 R/W 0x0000007c00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 35124 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 35135 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 35146 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 35158 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 35169 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 35181 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 35192 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 35199 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35292 main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0xC4E8 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 35217 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 35228 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 35239 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 35250 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 35262 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 35273 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 35284 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 35291 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35408 main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0xC500 R/W 0x0000007e00000000 Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 35332 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 35343 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 35354 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 35366 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 35377 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 35389 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 35400 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 35407 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35500 main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0xC508 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 35425 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 35436 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 35447 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 35458 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 35470 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 35481 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 35492 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 35499 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_p_0 bridge_main0_esr_m_1_5_p_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35565 main0_esr_m register p_0 0xF000 R/W 0x00000003 Pcie_noc_bridge_main0_esr_m_1_5_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 35528 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 35540 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 35552 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 35564 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_p_1 bridge_main0_esr_m_1_5_p_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35631 main0_esr_m register p_1 0xF008 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 35594 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 35606 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 35618 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 35630 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_p_2 bridge_main0_esr_m_1_5_p_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35697 main0_esr_m register p_2 0xF010 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 35660 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 35672 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 35684 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 35696 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_p_3 bridge_main0_esr_m_1_5_p_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35763 main0_esr_m register p_3 0xF018 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 35726 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 35738 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 35750 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 35762 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_txe bridge_main0_esr_m_1_5_txe PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35909 main0_esr_m register txe 0xF040 R/W 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 35790 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 35802 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 35817 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 35830 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 35844 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 35858 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 35872 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 35886 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 35897 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 35908 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_txem bridge_main0_esr_m_1_5_txem PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 35988 main0_esr_m register txem 0xF048 R/W 0x00000008 Pcie_noc_bridge_main0_esr_m_1_5_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 35932 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 35943 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 35954 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 35965 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 35976 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 35987 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_esr_m_1_5_btus_0 bridge_main0_esr_m_1_5_btus_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 36356 main0_esr_m register btus_0 0xF058 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 36014 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 36025 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 36036 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 36047 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 36058 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 36069 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 36080 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 36091 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 36102 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 36113 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 36124 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 36135 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 36146 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 36157 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 36168 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 36179 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 36190 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 36201 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 36212 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 36223 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 36234 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 36245 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 36256 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 36267 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 36278 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 36289 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 36300 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 36311 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 36322 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 36333 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 36344 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 36355 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_main0_esr_m_1_5_btus_1 bridge_main0_esr_m_1_5_btus_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 36724 main0_esr_m register btus_1 0xF060 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 36382 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 36393 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 36404 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 36415 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 36426 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 36437 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 36448 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 36459 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 36470 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 36481 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 36492 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 36503 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 36514 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 36525 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 36536 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 36547 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 36558 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 36569 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 36580 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 36591 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 36602 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 36613 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 36624 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 36635 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 36646 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 36657 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 36668 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 36679 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 36690 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 36701 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 36712 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 36723 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_main0_esr_m_1_5_btrl_0 bridge_main0_esr_m_1_5_btrl_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 36800 main0_esr_m register btrl_0 0xF080 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 36748 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 36759 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 36774 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 36788 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 36799 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_esr_m_1_5_btrl_1 bridge_main0_esr_m_1_5_btrl_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 36876 main0_esr_m register btrl_1 0xF088 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 36824 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 36835 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 36850 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 36864 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 36875 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_esr_m_1_5_btrl_2 bridge_main0_esr_m_1_5_btrl_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 36952 main0_esr_m register btrl_2 0xF090 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 36900 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 36911 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 36926 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 36940 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 36951 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_esr_m_1_5_btrl_3 bridge_main0_esr_m_1_5_btrl_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 37028 main0_esr_m register btrl_3 0xF098 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 36976 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 36987 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 37002 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 37016 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 37027 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_esr_m_1_5_btperr bridge_main0_esr_m_1_5_btperr PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 37230 main0_esr_m register btperr 0xF0A8 R/W 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 37053 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 37064 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 37075 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 37086 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 37097 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 37108 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 37119 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 37130 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 37141 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 37152 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 37163 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 37174 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 37185 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 37196 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 37207 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 37218 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 37229 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_esr_m_1_5_btperrm bridge_main0_esr_m_1_5_btperrm PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 37430 main0_esr_m register btperrm 0xF0B0 R/W 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 37253 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 37264 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 37275 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 37286 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 37297 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 37308 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 37319 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 37330 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 37341 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 37352 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 37363 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 37374 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 37385 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 37396 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 37407 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 37418 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 37429 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_esr_m_1_5_rxe bridge_main0_esr_m_1_5_rxe PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 37538 main0_esr_m register rxe 0xF120 R/W 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 37458 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 37469 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 37480 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 37491 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 37503 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 37514 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 37526 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 37537 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_esr_m_1_5_rxem bridge_main0_esr_m_1_5_rxem PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 37610 main0_esr_m register rxem 0xF128 R/W 0x00000050 Pcie_noc_bridge_main0_esr_m_1_5_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 37559 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 37573 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 37584 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 37598 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 37609 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_esr_m_1_5_brs_0 bridge_main0_esr_m_1_5_brs_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 37884 main0_esr_m register brs_0 0xF130 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 37634 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 37645 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 37656 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 37667 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 37678 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 37688 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 37699 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 37710 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 37721 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 37732 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 37743 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 37753 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 37764 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 37775 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 37786 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 37797 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 37808 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 37818 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 37829 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 37840 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 37851 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 37862 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 37873 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 37883 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_esr_m_1_5_brs_1 bridge_main0_esr_m_1_5_brs_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38158 main0_esr_m register brs_1 0xF138 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 37908 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 37919 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 37930 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 37941 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 37952 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 37962 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 37973 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 37984 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 37995 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 38006 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 38017 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 38027 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 38038 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 38049 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 38060 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 38071 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 38082 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 38092 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 38103 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 38114 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 38125 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 38136 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 38147 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 38157 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_esr_m_1_5_brus bridge_main0_esr_m_1_5_brus PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38227 main0_esr_m register brus 0xF1B0 R 0x00000000 Pcie_noc_bridge_main0_esr_m_1_5_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 38183 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 38194 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 38205 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 38216 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 38226 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_main0_esr_m_1_5_brperr0 bridge_main0_esr_m_1_5_brperr0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38455 main0_esr_m register brperr0 0xF1D0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 38265 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 38276 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 38287 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 38299 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 38310 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 38321 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 38332 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 38343 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 38354 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 38366 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 38377 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 38388 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 38399 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 38410 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 38421 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 38432 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 38443 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 38454 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_brperr1 bridge_main0_esr_m_1_5_brperr1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38571 main0_esr_m register brperr1 0xF1D8 R 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 38493 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 38504 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 38515 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 38526 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 38537 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 38548 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 38559 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 38570 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_brperrm0 bridge_main0_esr_m_1_5_brperrm0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38792 main0_esr_m register brperrm0 0xF1E0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 38598 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 38610 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 38621 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 38633 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 38645 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 38656 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 38667 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 38679 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 38690 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 38702 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 38714 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 38725 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 38736 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 38747 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 38758 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 38769 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 38780 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 38791 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_brperrm1 bridge_main0_esr_m_1_5_brperrm1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38897 main0_esr_m register brperrm1 0xF1E8 R 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 38819 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 38830 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 38841 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 38852 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 38863 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 38874 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 38885 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 38896 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_am_tocfg bridge_main0_esr_m_1_5_am_tocfg PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 38971 main0_esr_m register am_tocfg 0xFC00 R/W 0x000000000000001f Pcie_noc_bridge_main0_esr_m_1_5_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 38934 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 38945 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 38959 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 38970 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_osslv bridge_main0_esr_m_1_5_am_osslv PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39006 main0_esr_m register am_osslv 0xFC08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 38994 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 39005 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_cgc bridge_main0_esr_m_1_5_am_cgc PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39043 main0_esr_m register am_cgc 0xFC10 R/W 0x0000000000000064 Pcie_noc_bridge_main0_esr_m_1_5_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 39031 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 39042 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_cgo bridge_main0_esr_m_1_5_am_cgo PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39078 main0_esr_m register am_cgo 0xFC18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 39066 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 39077 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_cfg bridge_main0_esr_m_1_5_am_cfg PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39115 main0_esr_m register am_cfg 0xFC20 R/W 0x0000000000000001 Pcie_noc_bridge_main0_esr_m_1_5_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 39103 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 39114 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_sts bridge_main0_esr_m_1_5_am_sts PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39243 main0_esr_m register am_sts 0xFD00 R 0x000000000000000c Pcie_noc_bridge_main0_esr_m_1_5_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 39148 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 39162 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 39174 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 39186 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 39197 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 39208 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 39220 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 39232 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 39242 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_bridge_id bridge_main0_esr_m_1_5_am_bridge_id PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39273 main0_esr_m register am_bridge_id 0xFD08 R 0x0000000000000001 Pcie_noc_bridge_main0_esr_m_1_5_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 39262 ID Unique bridge ID 15 0 0x0001 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 39272 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_err bridge_main0_esr_m_1_5_am_err PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39769 main0_esr_m register am_err 0xFE00 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 39295 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 39307 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 39319 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 39331 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 39343 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 39355 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 39368 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 39381 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 39392 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 39403 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 39414 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 39425 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 39436 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 39447 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 39458 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 39469 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 39480 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 39492 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 39503 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 39514 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 39525 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 39536 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 39548 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 39560 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 39571 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 39583 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 39594 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 39605 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 39616 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 39627 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 39638 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 39649 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 39661 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 39673 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 39685 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 39697 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 39709 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 39721 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 39733 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 39745 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 39757 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 39768 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_am_toslvid bridge_main0_esr_m_1_5_am_toslvid PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39814 main0_esr_m register am_toslvid 0xFE08 R 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 39792 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 39803 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 39813 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_era bridge_main0_esr_m_1_5_am_era PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39836 main0_esr_m register am_era 0xFE10 R 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 39835 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_ewa bridge_main0_esr_m_1_5_am_ewa PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 39858 main0_esr_m register am_ewa 0xFE18 R 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 39857 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_intm bridge_main0_esr_m_1_5_am_intm PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40342 main0_esr_m register am_intm 0xFE40 R/W 0x00007e07004f004f Pcie_noc_bridge_main0_esr_m_1_5_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 39880 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 39891 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 39902 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 39913 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 39924 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 39935 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 39946 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 39957 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 39968 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 39979 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 39990 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 40001 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 40012 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 40023 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 40034 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 40045 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 40056 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 40067 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 40078 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 40089 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 40100 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 40111 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 40122 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 40133 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 40144 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 40156 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 40167 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 40178 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 40189 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 40200 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 40211 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 40222 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 40234 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 40246 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 40258 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 40270 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 40282 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 40294 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 40306 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 40318 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 40330 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 40341 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_esr_m_1_5_am_caddr bridge_main0_esr_m_1_5_am_caddr PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40364 main0_esr_m register am_caddr 0xFF00 R/W 0xffffffffffffffff Pcie_noc_bridge_main0_esr_m_1_5_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 40363 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_main0_esr_m_1_5_am_caddrmsk bridge_main0_esr_m_1_5_am_caddrmsk PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40387 main0_esr_m register am_caddrmsk 0xFF08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 40386 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_main0_esr_m_1_5_am_ccmd0 bridge_main0_esr_m_1_5_am_ccmd0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40577 main0_esr_m register am_ccmd0 0xFF10 R/W 0x0000000003fff33f Pcie_noc_bridge_main0_esr_m_1_5_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 40409 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 40420 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 40431 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 40442 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 40453 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 40464 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 40475 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 40486 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 40497 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 40508 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 40519 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 40530 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 40542 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 40553 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 40565 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 40576 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk0 bridge_main0_esr_m_1_5_am_ccmdmsk0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40721 main0_esr_m register am_ccmdmsk0 0xFF18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 40599 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 40610 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 40621 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 40632 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 40643 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 40654 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 40665 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 40676 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 40687 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 40698 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 40709 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 40720 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_cntr0 bridge_main0_esr_m_1_5_am_cntr0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40756 main0_esr_m register am_cntr0 0xFF20 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 40744 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 40755 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_latnum0 bridge_main0_esr_m_1_5_am_latnum0 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40795 main0_esr_m register am_latnum0 0xFF28 R/W 0x0000000000000007 Pcie_noc_bridge_main0_esr_m_1_5_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 40783 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 40794 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_ccmd1 bridge_main0_esr_m_1_5_am_ccmd1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 40985 main0_esr_m register am_ccmd1 0xFF30 R/W 0x0000000003fff33f Pcie_noc_bridge_main0_esr_m_1_5_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 40817 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 40828 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 40839 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 40850 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 40861 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 40872 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 40883 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 40894 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 40905 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 40916 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 40927 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 40938 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 40950 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 40961 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 40973 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 40984 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk1 bridge_main0_esr_m_1_5_am_ccmdmsk1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41129 main0_esr_m register am_ccmdmsk1 0xFF38 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 41007 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 41018 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 41029 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 41040 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 41051 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 41062 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 41073 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 41084 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 41095 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 41106 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 41117 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 41128 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_cntr1 bridge_main0_esr_m_1_5_am_cntr1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41164 main0_esr_m register am_cntr1 0xFF40 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 41152 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 41163 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_latnum1 bridge_main0_esr_m_1_5_am_latnum1 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41203 main0_esr_m register am_latnum1 0xFF48 R/W 0x0000000000000007 Pcie_noc_bridge_main0_esr_m_1_5_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 41191 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 41202 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_arovrd bridge_main0_esr_m_1_5_am_arovrd PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41316 main0_esr_m register am_arovrd 0xFF60 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 41221 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 41234 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 41245 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 41256 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 41269 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 41280 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 41291 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 41304 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 41315 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_esr_m_1_5_am_awovrd bridge_main0_esr_m_1_5_am_awovrd PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41429 main0_esr_m register am_awovrd 0xFF68 R/W 0x0000000000000000 Pcie_noc_bridge_main0_esr_m_1_5_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 41334 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 41347 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 41358 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 41369 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 41382 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 41393 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 41404 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 41417 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 41428 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41545 main0_mesh_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x10000 R/W 0x0000000058200010 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 41469 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 41480 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 41491 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 41503 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 41514 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 41526 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 41537 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 41544 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41637 main0_mesh_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x10008 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 41562 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 41573 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 41584 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 41595 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 41607 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 41618 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 41629 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 41636 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41753 main0_mesh_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x10020 R/W 0x0000007f80000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 41677 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 41688 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 41699 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 41711 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 41722 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 41734 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 41745 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 41752 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41845 main0_mesh_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x10028 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 41770 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 41781 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 41792 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 41803 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 41815 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 41826 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 41837 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 41844 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 41886 main0_mesh_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x10030 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 41863 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 41874 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 41885 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42002 main0_mesh_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x10040 R/W 0x0000007f80001000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 41926 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 41937 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 41948 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 41960 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 41971 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 41983 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 41994 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42001 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42094 main0_mesh_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x10048 R/W 0x000000fffffff000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 42019 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42030 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 42041 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 42052 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 42064 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 42075 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 42086 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42093 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42135 main0_mesh_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x10050 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 42112 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 42123 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 42134 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42251 main0_mesh_m register am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x10060 R/W 0x0000007e80000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42175 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42186 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42197 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 42209 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 42220 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 42232 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 42243 BASE_ADDRESS_0_33 Base address 39 6 0x1fa000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42250 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42343 main0_mesh_m register am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x10068 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42268 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42279 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42290 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 42301 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 42313 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 42324 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 42335 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42342 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42384 main0_mesh_m register am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x10070 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 42361 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 42372 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 42383 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42500 main0_mesh_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x10080 R/W 0x0000004000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42424 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42435 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42446 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 42458 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 42469 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 42481 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 42492 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42499 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42592 main0_mesh_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x10088 R/W 0x000000e000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42517 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42528 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42539 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 42550 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 42562 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 42573 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 42584 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42591 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42708 main0_mesh_m register am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x100A0 R/W 0x0000007f00000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42632 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42643 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42654 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 42666 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 42677 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 42689 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 42700 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42707 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42800 main0_mesh_m register am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x100A8 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42725 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42736 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42747 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 42758 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 42770 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 42781 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 42792 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42799 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42841 main0_mesh_m register am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x100B0 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 42818 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 42829 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 42840 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 42957 main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x100C0 R/W 0x0000006000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42881 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42892 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42903 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 42915 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 42926 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 42938 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 42949 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 42956 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43049 main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x100C8 R/W 0x000000f000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 42974 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 42985 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 42996 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 43007 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 43019 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 43030 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 43041 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43048 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43165 main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x100E0 R/W 0x0000007000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 43089 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43100 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 43111 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 43123 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 43134 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 43146 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 43157 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43164 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43257 main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x100E8 R/W 0x000000f800000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 43182 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43193 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 43204 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 43215 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 43227 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 43238 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 43249 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43256 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43373 main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x10100 R/W 0x0000007800000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 43297 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43308 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 43319 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 43331 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 43342 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 43354 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 43365 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43372 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43465 main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x10108 R/W 0x000000fc00000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 43390 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43401 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 43412 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 43423 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 43435 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 43446 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 43457 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43464 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43581 main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x10120 R/W 0x0000007c00000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 43505 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43516 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 43527 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 43539 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 43550 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 43562 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 43573 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43580 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43673 main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x10128 R/W 0x000000fe00000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 43598 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43609 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 43620 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 43631 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 43643 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 43654 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 43665 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43672 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43789 main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x10140 R/W 0x0000007e00000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 43713 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43724 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 43735 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 43747 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 43758 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 43770 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 43781 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43788 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43881 main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x10148 R/W 0x000000ff80000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 43806 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 43817 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 43828 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 43839 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 43851 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 43862 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 43873 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 43880 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_p_0 bridge_main0_mesh_m_2_5_p_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 43946 main0_mesh_m register p_0 0x13000 R/W 0x00000003 Pcie_noc_bridge_main0_mesh_m_2_5_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 43909 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 43921 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 43933 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 43945 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_p_1 bridge_main0_mesh_m_2_5_p_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 44012 main0_mesh_m register p_1 0x13008 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 43975 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 43987 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 43999 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 44011 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_p_2 bridge_main0_mesh_m_2_5_p_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 44078 main0_mesh_m register p_2 0x13010 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 44041 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 44053 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 44065 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 44077 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_p_3 bridge_main0_mesh_m_2_5_p_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 44144 main0_mesh_m register p_3 0x13018 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 44107 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 44119 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 44131 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 44143 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_txe bridge_main0_mesh_m_2_5_txe PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 44290 main0_mesh_m register txe 0x13040 R/W 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 44171 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 44183 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 44198 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 44211 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 44225 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 44239 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 44253 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 44267 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 44278 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 44289 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_txem bridge_main0_mesh_m_2_5_txem PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 44369 main0_mesh_m register txem 0x13048 R/W 0x00000008 Pcie_noc_bridge_main0_mesh_m_2_5_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 44313 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 44324 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 44335 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 44346 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 44357 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 44368 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_mesh_m_2_5_btus_0 bridge_main0_mesh_m_2_5_btus_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 44737 main0_mesh_m register btus_0 0x13058 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 44395 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 44406 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 44417 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 44428 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 44439 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 44450 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 44461 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 44472 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 44483 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 44494 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 44505 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 44516 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 44527 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 44538 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 44549 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 44560 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 44571 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 44582 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 44593 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 44604 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 44615 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 44626 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 44637 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 44648 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 44659 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 44670 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 44681 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 44692 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 44703 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 44714 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 44725 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 44736 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_main0_mesh_m_2_5_btus_1 bridge_main0_mesh_m_2_5_btus_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45105 main0_mesh_m register btus_1 0x13060 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 44763 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 44774 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 44785 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 44796 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 44807 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 44818 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 44829 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 44840 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 44851 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 44862 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 44873 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 44884 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 44895 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 44906 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 44917 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 44928 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 44939 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 44950 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 44961 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 44972 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 44983 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 44994 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 45005 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 45016 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 45027 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 45038 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 45049 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 45060 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 45071 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 45082 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 45093 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 45104 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_main0_mesh_m_2_5_btrl_0 bridge_main0_mesh_m_2_5_btrl_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45181 main0_mesh_m register btrl_0 0x13080 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 45129 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 45140 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 45155 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 45169 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 45180 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_mesh_m_2_5_btrl_1 bridge_main0_mesh_m_2_5_btrl_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45257 main0_mesh_m register btrl_1 0x13088 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 45205 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 45216 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 45231 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 45245 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 45256 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_mesh_m_2_5_btrl_2 bridge_main0_mesh_m_2_5_btrl_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45333 main0_mesh_m register btrl_2 0x13090 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 45281 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 45292 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 45307 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 45321 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 45332 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_mesh_m_2_5_btrl_3 bridge_main0_mesh_m_2_5_btrl_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45409 main0_mesh_m register btrl_3 0x13098 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 45357 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 45368 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 45383 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 45397 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 45408 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_mesh_m_2_5_btperr bridge_main0_mesh_m_2_5_btperr PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45611 main0_mesh_m register btperr 0x130A8 R/W 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 45434 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 45445 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 45456 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 45467 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 45478 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 45489 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 45500 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 45511 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 45522 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 45533 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 45544 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 45555 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 45566 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 45577 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 45588 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 45599 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 45610 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_mesh_m_2_5_btperrm bridge_main0_mesh_m_2_5_btperrm PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45811 main0_mesh_m register btperrm 0x130B0 R/W 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 45634 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 45645 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 45656 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 45667 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 45678 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 45689 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 45700 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 45711 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 45722 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 45733 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 45744 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 45755 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 45766 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 45777 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 45788 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 45799 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 45810 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_mesh_m_2_5_rxe bridge_main0_mesh_m_2_5_rxe PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45919 main0_mesh_m register rxe 0x13120 R/W 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 45839 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 45850 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 45861 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 45872 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 45884 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 45895 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 45907 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 45918 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_mesh_m_2_5_rxem bridge_main0_mesh_m_2_5_rxem PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 45991 main0_mesh_m register rxem 0x13128 R/W 0x00000050 Pcie_noc_bridge_main0_mesh_m_2_5_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 45940 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 45954 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 45965 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 45979 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 45990 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_mesh_m_2_5_brs_0 bridge_main0_mesh_m_2_5_brs_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 46265 main0_mesh_m register brs_0 0x13130 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 46015 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 46026 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 46037 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 46048 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 46059 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 46069 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 46080 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 46091 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 46102 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 46113 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 46124 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 46134 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 46145 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 46156 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 46167 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 46178 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 46189 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 46199 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 46210 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 46221 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 46232 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 46243 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 46254 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 46264 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_mesh_m_2_5_brs_1 bridge_main0_mesh_m_2_5_brs_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 46539 main0_mesh_m register brs_1 0x13138 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 46289 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 46300 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 46311 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 46322 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 46333 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 46343 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 46354 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 46365 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 46376 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 46387 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 46398 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 46408 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 46419 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 46430 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 46441 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 46452 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 46463 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 46473 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 46484 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 46495 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 46506 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 46517 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 46528 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 46538 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_mesh_m_2_5_brus bridge_main0_mesh_m_2_5_brus PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 46608 main0_mesh_m register brus 0x131B0 R 0x00000000 Pcie_noc_bridge_main0_mesh_m_2_5_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 46564 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 46575 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 46586 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 46597 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 46607 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_main0_mesh_m_2_5_brperr0 bridge_main0_mesh_m_2_5_brperr0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 46836 main0_mesh_m register brperr0 0x131D0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 46646 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 46657 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 46668 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 46680 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 46691 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 46702 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 46713 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 46724 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 46735 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 46747 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 46758 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 46769 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 46780 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 46791 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 46802 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 46813 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 46824 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 46835 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_brperr1 bridge_main0_mesh_m_2_5_brperr1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 46952 main0_mesh_m register brperr1 0x131D8 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 46874 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 46885 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 46896 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 46907 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 46918 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 46929 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 46940 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 46951 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_brperrm0 bridge_main0_mesh_m_2_5_brperrm0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47173 main0_mesh_m register brperrm0 0x131E0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 46979 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 46991 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 47002 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 47014 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 47026 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 47037 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 47048 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 47060 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 47071 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 47083 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 47095 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 47106 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 47117 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 47128 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 47139 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 47150 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 47161 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 47172 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_brperrm1 bridge_main0_mesh_m_2_5_brperrm1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47278 main0_mesh_m register brperrm1 0x131E8 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 47200 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 47211 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 47222 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 47233 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 47244 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 47255 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 47266 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 47277 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_am_tocfg bridge_main0_mesh_m_2_5_am_tocfg PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47352 main0_mesh_m register am_tocfg 0x13C00 R/W 0x000000000000001f Pcie_noc_bridge_main0_mesh_m_2_5_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 47315 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 47326 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 47340 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 47351 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_osslv bridge_main0_mesh_m_2_5_am_osslv PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47387 main0_mesh_m register am_osslv 0x13C08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 47375 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 47386 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_cgc bridge_main0_mesh_m_2_5_am_cgc PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47424 main0_mesh_m register am_cgc 0x13C10 R/W 0x0000000000000064 Pcie_noc_bridge_main0_mesh_m_2_5_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 47412 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 47423 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_cgo bridge_main0_mesh_m_2_5_am_cgo PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47459 main0_mesh_m register am_cgo 0x13C18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 47447 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 47458 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_cfg bridge_main0_mesh_m_2_5_am_cfg PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47496 main0_mesh_m register am_cfg 0x13C20 R/W 0x0000000000000001 Pcie_noc_bridge_main0_mesh_m_2_5_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 47484 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 47495 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_sts bridge_main0_mesh_m_2_5_am_sts PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47624 main0_mesh_m register am_sts 0x13D00 R 0x000000000000000c Pcie_noc_bridge_main0_mesh_m_2_5_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 47529 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 47543 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 47555 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 47567 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 47578 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 47589 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 47601 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 47613 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 47623 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_bridge_id bridge_main0_mesh_m_2_5_am_bridge_id PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 47654 main0_mesh_m register am_bridge_id 0x13D08 R 0x0000000000000002 Pcie_noc_bridge_main0_mesh_m_2_5_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 47643 ID Unique bridge ID 15 0 0x0002 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 47653 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_err bridge_main0_mesh_m_2_5_am_err PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48150 main0_mesh_m register am_err 0x13E00 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 47676 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 47688 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 47700 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 47712 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 47724 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 47736 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 47749 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 47762 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 47773 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 47784 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 47795 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 47806 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 47817 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 47828 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 47839 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 47850 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 47861 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 47873 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 47884 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 47895 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 47906 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 47917 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 47929 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 47941 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 47952 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 47964 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 47975 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 47986 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 47997 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 48008 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 48019 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 48030 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 48042 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 48054 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 48066 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 48078 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 48090 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 48102 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 48114 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 48126 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 48138 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 48149 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_am_toslvid bridge_main0_mesh_m_2_5_am_toslvid PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48195 main0_mesh_m register am_toslvid 0x13E08 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 48173 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 48184 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 48194 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_era bridge_main0_mesh_m_2_5_am_era PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48217 main0_mesh_m register am_era 0x13E10 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 48216 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_ewa bridge_main0_mesh_m_2_5_am_ewa PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48239 main0_mesh_m register am_ewa 0x13E18 R 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 48238 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_intm bridge_main0_mesh_m_2_5_am_intm PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48723 main0_mesh_m register am_intm 0x13E40 R/W 0x00007e07004f004f Pcie_noc_bridge_main0_mesh_m_2_5_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 48261 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 48272 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 48283 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 48294 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 48305 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 48316 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 48327 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 48338 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 48349 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 48360 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 48371 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 48382 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 48393 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 48404 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 48415 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 48426 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 48437 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 48448 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 48459 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 48470 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 48481 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 48492 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 48503 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 48514 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 48525 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 48537 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 48548 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 48559 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 48570 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 48581 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 48592 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 48603 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 48615 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 48627 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 48639 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 48651 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 48663 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 48675 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 48687 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 48699 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 48711 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 48722 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_mesh_m_2_5_am_caddr bridge_main0_mesh_m_2_5_am_caddr PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48745 main0_mesh_m register am_caddr 0x13F00 R/W 0xffffffffffffffff Pcie_noc_bridge_main0_mesh_m_2_5_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 48744 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_main0_mesh_m_2_5_am_caddrmsk bridge_main0_mesh_m_2_5_am_caddrmsk PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48768 main0_mesh_m register am_caddrmsk 0x13F08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 48767 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmd0 bridge_main0_mesh_m_2_5_am_ccmd0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 48958 main0_mesh_m register am_ccmd0 0x13F10 R/W 0x0000000003fff33f Pcie_noc_bridge_main0_mesh_m_2_5_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 48790 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 48801 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 48812 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 48823 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 48834 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 48845 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 48856 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 48867 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 48878 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 48889 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 48900 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 48911 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 48923 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 48934 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 48946 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 48957 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmdmsk0 bridge_main0_mesh_m_2_5_am_ccmdmsk0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49102 main0_mesh_m register am_ccmdmsk0 0x13F18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 48980 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 48991 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 49002 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 49013 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 49024 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 49035 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 49046 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 49057 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 49068 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 49079 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 49090 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 49101 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_cntr0 bridge_main0_mesh_m_2_5_am_cntr0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49137 main0_mesh_m register am_cntr0 0x13F20 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 49125 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 49136 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_latnum0 bridge_main0_mesh_m_2_5_am_latnum0 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49176 main0_mesh_m register am_latnum0 0x13F28 R/W 0x0000000000000007 Pcie_noc_bridge_main0_mesh_m_2_5_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 49164 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 49175 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmd1 bridge_main0_mesh_m_2_5_am_ccmd1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49366 main0_mesh_m register am_ccmd1 0x13F30 R/W 0x0000000003fff33f Pcie_noc_bridge_main0_mesh_m_2_5_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 49198 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 49209 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 49220 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 49231 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 49242 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 49253 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 49264 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 49275 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 49286 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 49297 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 49308 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 49319 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 49331 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 49342 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 49354 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 49365 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_ccmdmsk1 bridge_main0_mesh_m_2_5_am_ccmdmsk1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49510 main0_mesh_m register am_ccmdmsk1 0x13F38 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 49388 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 49399 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 49410 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 49421 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 49432 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 49443 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 49454 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 49465 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 49476 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 49487 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 49498 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 49509 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_cntr1 bridge_main0_mesh_m_2_5_am_cntr1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49545 main0_mesh_m register am_cntr1 0x13F40 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 49533 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 49544 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_latnum1 bridge_main0_mesh_m_2_5_am_latnum1 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49584 main0_mesh_m register am_latnum1 0x13F48 R/W 0x0000000000000007 Pcie_noc_bridge_main0_mesh_m_2_5_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 49572 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 49583 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_arovrd bridge_main0_mesh_m_2_5_am_arovrd PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49697 main0_mesh_m register am_arovrd 0x13F60 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 49602 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 49615 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 49626 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 49637 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 49650 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 49661 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 49672 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 49685 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 49696 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_mesh_m_2_5_am_awovrd bridge_main0_mesh_m_2_5_am_awovrd PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49810 main0_mesh_m register am_awovrd 0x13F68 R/W 0x0000000000000000 Pcie_noc_bridge_main0_mesh_m_2_5_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 49715 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 49728 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 49739 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 49750 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 49763 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 49774 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 49785 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 49798 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 49809 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_cgc bridge_main0_tol3_s_7_5_as_cgc PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49847 main0_tol3_s register as_cgc 0x15C10 R/W 0x0000000000000064 Pcie_noc_bridge_main0_tol3_s_7_5_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 49835 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 49846 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_cgo bridge_main0_tol3_s_7_5_as_cgo PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49882 main0_tol3_s register as_cgo 0x15C18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 49870 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 49881 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_sts bridge_main0_tol3_s_7_5_as_sts PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49956 main0_tol3_s register as_sts 0x15D00 R 0x000000000000000c Pcie_noc_bridge_main0_tol3_s_7_5_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 49905 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 49921 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 49933 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 49945 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 49955 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_bridge_id bridge_main0_tol3_s_7_5_as_bridge_id PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 49986 main0_tol3_s register as_bridge_id 0x15D08 R 0x0000000000000007 Pcie_noc_bridge_main0_tol3_s_7_5_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 49975 ID Unique bridge ID 15 0 0x0007 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 49985 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_err bridge_main0_tol3_s_7_5_as_err PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 50339 main0_tol3_s register as_err 0x15E00 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 50007 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 50019 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 50032 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 50046 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 50058 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 50069 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 50081 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 50093 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 50106 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 50118 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 50129 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 50141 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 50152 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 50163 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 50174 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 50185 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 50196 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 50207 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 50219 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 50231 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 50243 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 50255 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 50267 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 50279 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 50291 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 50303 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 50315 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 50327 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 50338 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_intm bridge_main0_tol3_s_7_5_as_intm PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 50679 main0_tol3_s register as_intm 0x15E40 R/W 0x0000007d000b0013 Pcie_noc_bridge_main0_tol3_s_7_5_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 50360 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 50371 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 50382 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 50393 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 50404 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 50415 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 50426 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 50437 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 50448 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 50459 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 50470 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 50481 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 50492 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 50503 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 50514 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 50525 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 50536 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 50547 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 50559 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 50571 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 50583 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 50595 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 50607 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 50619 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 50631 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 50643 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 50655 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 50667 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 50678 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_ccmd bridge_main0_tol3_s_7_5_as_ccmd PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 50754 main0_tol3_s register as_ccmd 0x15F00 R/W 0x0000000003000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 50697 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 50708 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 50719 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 50730 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 50742 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 50753 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_ccmdmsk bridge_main0_tol3_s_7_5_as_ccmdmsk PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 50806 main0_tol3_s register as_ccmdmsk 0x15F08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 50772 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 50783 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 50794 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 50805 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_cntr bridge_main0_tol3_s_7_5_as_cntr PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 50836 main0_tol3_s register as_cntr 0x15F10 R 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 50825 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 50835 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_arovrd bridge_main0_tol3_s_7_5_as_arovrd PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 50949 main0_tol3_s register as_arovrd 0x15F18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 50854 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 50867 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 50878 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 50889 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 50902 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 50913 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 50924 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 50937 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 50948 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_as_awovrd bridge_main0_tol3_s_7_5_as_awovrd PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51062 main0_tol3_s register as_awovrd 0x15F20 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 50967 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 50980 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 50991 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 51002 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 51015 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 51026 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 51037 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 51050 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 51061 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_tol3_s_7_5_p_0 bridge_main0_tol3_s_7_5_p_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51127 main0_tol3_s register p_0 0x17000 R/W 0x00000003 Pcie_noc_bridge_main0_tol3_s_7_5_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 51090 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 51102 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 51114 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 51126 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_p_1 bridge_main0_tol3_s_7_5_p_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51193 main0_tol3_s register p_1 0x17008 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 51156 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 51168 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 51180 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 51192 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_p_2 bridge_main0_tol3_s_7_5_p_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51259 main0_tol3_s register p_2 0x17010 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 51222 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 51234 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 51246 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 51258 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_p_3 bridge_main0_tol3_s_7_5_p_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51325 main0_tol3_s register p_3 0x17018 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 51288 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 51300 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 51312 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 51324 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_txe bridge_main0_tol3_s_7_5_txe PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51471 main0_tol3_s register txe 0x17040 R/W 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 51352 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 51364 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 51379 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 51392 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 51406 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 51420 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 51434 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 51448 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 51459 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 51470 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_tol3_s_7_5_txem bridge_main0_tol3_s_7_5_txem PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51550 main0_tol3_s register txem 0x17048 R/W 0x00000008 Pcie_noc_bridge_main0_tol3_s_7_5_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 51494 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 51505 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 51516 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 51527 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 51538 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 51549 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_tol3_s_7_5_btus_0 bridge_main0_tol3_s_7_5_btus_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 51918 main0_tol3_s register btus_0 0x17058 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 51576 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 51587 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 51598 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 51609 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 51620 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 51631 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 51642 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 51653 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 51664 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 51675 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 51686 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 51697 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 51708 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 51719 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 51730 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 51741 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 51752 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 51763 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 51774 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 51785 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 51796 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 51807 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 51818 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 51829 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 51840 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 51851 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 51862 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 51873 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 51884 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 51895 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 51906 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 51917 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_main0_tol3_s_7_5_btus_1 bridge_main0_tol3_s_7_5_btus_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52286 main0_tol3_s register btus_1 0x17060 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 51944 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 51955 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 51966 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 51977 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 51988 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 51999 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 52010 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 52021 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 52032 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 52043 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 52054 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 52065 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 52076 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 52087 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 52098 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 52109 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 52120 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 52131 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 52142 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 52153 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 52164 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 52175 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 52186 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 52197 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 52208 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 52219 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 52230 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 52241 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 52252 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 52263 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 52274 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 52285 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_main0_tol3_s_7_5_btrl_0 bridge_main0_tol3_s_7_5_btrl_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52362 main0_tol3_s register btrl_0 0x17080 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 52310 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 52321 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 52336 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 52350 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 52361 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tol3_s_7_5_btrl_1 bridge_main0_tol3_s_7_5_btrl_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52438 main0_tol3_s register btrl_1 0x17088 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 52386 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 52397 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 52412 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 52426 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 52437 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tol3_s_7_5_btrl_2 bridge_main0_tol3_s_7_5_btrl_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52514 main0_tol3_s register btrl_2 0x17090 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 52462 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 52473 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 52488 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 52502 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 52513 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tol3_s_7_5_btrl_3 bridge_main0_tol3_s_7_5_btrl_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52590 main0_tol3_s register btrl_3 0x17098 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 52538 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 52549 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 52564 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 52578 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 52589 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tol3_s_7_5_btperr bridge_main0_tol3_s_7_5_btperr PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52792 main0_tol3_s register btperr 0x170A8 R/W 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 52615 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 52626 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 52637 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 52648 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 52659 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 52670 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 52681 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 52692 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 52703 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 52714 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 52725 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 52736 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 52747 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 52758 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 52769 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 52780 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 52791 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_tol3_s_7_5_btperrm bridge_main0_tol3_s_7_5_btperrm PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 52992 main0_tol3_s register btperrm 0x170B0 R/W 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 52815 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 52826 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 52837 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 52848 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 52859 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 52870 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 52881 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 52892 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 52903 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 52914 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 52925 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 52936 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 52947 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 52958 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 52969 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 52980 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 52991 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_tol3_s_7_5_rxe bridge_main0_tol3_s_7_5_rxe PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 53100 main0_tol3_s register rxe 0x17120 R/W 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 53020 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 53031 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 53042 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 53053 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 53065 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 53076 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 53088 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 53099 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_tol3_s_7_5_rxem bridge_main0_tol3_s_7_5_rxem PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 53172 main0_tol3_s register rxem 0x17128 R/W 0x00000050 Pcie_noc_bridge_main0_tol3_s_7_5_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 53121 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 53135 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 53146 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 53160 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 53171 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_tol3_s_7_5_brs_0 bridge_main0_tol3_s_7_5_brs_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 53446 main0_tol3_s register brs_0 0x17130 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 53196 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 53207 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 53218 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 53229 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 53240 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 53250 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 53261 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 53272 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 53283 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 53294 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 53305 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 53315 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 53326 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 53337 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 53348 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 53359 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 53370 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 53380 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 53391 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 53402 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 53413 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 53424 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 53435 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 53445 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_tol3_s_7_5_brs_1 bridge_main0_tol3_s_7_5_brs_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 53720 main0_tol3_s register brs_1 0x17138 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 53470 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 53481 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 53492 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 53503 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 53514 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 53524 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 53535 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 53546 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 53557 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 53568 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 53579 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 53589 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 53600 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 53611 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 53622 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 53633 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 53644 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 53654 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 53665 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 53676 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 53687 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 53698 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 53709 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 53719 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_tol3_s_7_5_brus bridge_main0_tol3_s_7_5_brus PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 53789 main0_tol3_s register brus 0x171B0 R 0x00000000 Pcie_noc_bridge_main0_tol3_s_7_5_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 53745 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 53756 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 53767 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 53778 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 53788 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_main0_tol3_s_7_5_brperr0 bridge_main0_tol3_s_7_5_brperr0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54017 main0_tol3_s register brperr0 0x171D0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 53827 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 53838 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 53849 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 53861 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 53872 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 53883 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 53894 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 53905 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 53916 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 53928 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 53939 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 53950 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 53961 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 53972 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 53983 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 53994 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 54005 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 54016 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_brperr1 bridge_main0_tol3_s_7_5_brperr1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54133 main0_tol3_s register brperr1 0x171D8 R 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 54055 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 54066 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 54077 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 54088 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 54099 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 54110 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 54121 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 54132 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_brperrm0 bridge_main0_tol3_s_7_5_brperrm0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54354 main0_tol3_s register brperrm0 0x171E0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 54160 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 54172 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 54183 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 54195 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 54207 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 54218 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 54229 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 54241 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 54252 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 54264 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 54276 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 54287 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 54298 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 54309 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 54320 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 54331 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 54342 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 54353 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tol3_s_7_5_brperrm1 bridge_main0_tol3_s_7_5_brperrm1 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54459 main0_tol3_s register brperrm1 0x171E8 R 0x0000000000000000 Pcie_noc_bridge_main0_tol3_s_7_5_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 54381 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 54392 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 54403 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 54414 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 54425 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 54436 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 54447 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 54458 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_as_cgc bridge_main0_tosys_s_8_5_as_cgc PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54496 main0_tosys_s register as_cgc 0x19C10 R/W 0x0000000000000064 Pcie_noc_bridge_main0_tosys_s_8_5_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 54484 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 54495 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_cgo bridge_main0_tosys_s_8_5_as_cgo PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54531 main0_tosys_s register as_cgo 0x19C18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 54519 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 54530 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_sts bridge_main0_tosys_s_8_5_as_sts PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54605 main0_tosys_s register as_sts 0x19D00 R 0x000000000000000c Pcie_noc_bridge_main0_tosys_s_8_5_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 54554 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 54570 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 54582 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 54594 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 54604 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_bridge_id bridge_main0_tosys_s_8_5_as_bridge_id PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54635 main0_tosys_s register as_bridge_id 0x19D08 R 0x0000000000000008 Pcie_noc_bridge_main0_tosys_s_8_5_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 54624 ID Unique bridge ID 15 0 0x0008 R UNSD_63_16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 54634 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_err bridge_main0_tosys_s_8_5_as_err PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 54988 main0_tosys_s register as_err 0x19E00 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 54656 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 54668 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 54681 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 54695 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 54707 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 54718 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 54730 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 54742 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 54755 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 54767 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 54778 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 54790 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 54801 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 54812 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 54823 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 54834 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 54845 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 54856 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 54868 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 54880 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 54892 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 54904 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 54916 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 54928 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 54940 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 54952 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 54964 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 54976 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 54987 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_intm bridge_main0_tosys_s_8_5_as_intm PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55328 main0_tosys_s register as_intm 0x19E40 R/W 0x0000007d000b0013 Pcie_noc_bridge_main0_tosys_s_8_5_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 55009 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 55020 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 55031 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 55042 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 55053 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 55064 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 55075 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 55086 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 55097 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 55108 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 55119 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 55130 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 55141 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 55152 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 55163 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 55174 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 55185 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 55196 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 55208 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 55220 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 55232 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 55244 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 55256 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 55268 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 55280 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 55292 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 55304 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 55316 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 55327 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_ccmd bridge_main0_tosys_s_8_5_as_ccmd PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55403 main0_tosys_s register as_ccmd 0x19F00 R/W 0x0000000003000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 55346 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 55357 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 55368 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 55379 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 55391 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 55402 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_ccmdmsk bridge_main0_tosys_s_8_5_as_ccmdmsk PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55455 main0_tosys_s register as_ccmdmsk 0x19F08 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 55421 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 55432 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 55443 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 55454 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_cntr bridge_main0_tosys_s_8_5_as_cntr PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55485 main0_tosys_s register as_cntr 0x19F10 R 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 55474 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 55484 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_arovrd bridge_main0_tosys_s_8_5_as_arovrd PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55598 main0_tosys_s register as_arovrd 0x19F18 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 55503 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 55516 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 55527 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 55538 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 55551 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 55562 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 55573 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 55586 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 55597 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_as_awovrd bridge_main0_tosys_s_8_5_as_awovrd PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55711 main0_tosys_s register as_awovrd 0x19F20 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 55616 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 55629 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 55640 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 55651 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 55664 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 55675 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 55686 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 55699 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 55710 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_main0_tosys_s_8_5_p_0 bridge_main0_tosys_s_8_5_p_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55776 main0_tosys_s register p_0 0x1B000 R/W 0x00000003 Pcie_noc_bridge_main0_tosys_s_8_5_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 55739 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 55751 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 55763 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 55775 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_p_1 bridge_main0_tosys_s_8_5_p_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55842 main0_tosys_s register p_1 0x1B008 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 55805 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 55817 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 55829 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 55841 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_p_2 bridge_main0_tosys_s_8_5_p_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55908 main0_tosys_s register p_2 0x1B010 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 55871 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 55883 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 55895 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 55907 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_p_3 bridge_main0_tosys_s_8_5_p_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 55974 main0_tosys_s register p_3 0x1B018 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 55937 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 55949 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 55961 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 55973 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_txe bridge_main0_tosys_s_8_5_txe PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 56120 main0_tosys_s register txe 0x1B040 R/W 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 56001 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 56013 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 56028 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 56041 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 56055 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 56069 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 56083 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 56097 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 56108 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 56119 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_tosys_s_8_5_txem bridge_main0_tosys_s_8_5_txem PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 56199 main0_tosys_s register txem 0x1B048 R/W 0x00000008 Pcie_noc_bridge_main0_tosys_s_8_5_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 56143 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 56154 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 56165 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 56176 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 56187 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 56198 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_main0_tosys_s_8_5_btus_0 bridge_main0_tosys_s_8_5_btus_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 56567 main0_tosys_s register btus_0 0x1B058 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 56225 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 56236 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 56247 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 56258 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 56269 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 56280 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 56291 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 56302 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 56313 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 56324 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 56335 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 56346 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 56357 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 56368 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 56379 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 56390 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 56401 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 56412 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 56423 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 56434 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 56445 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 56456 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 56467 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 56478 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 56489 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 56500 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 56511 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 56522 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 56533 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 56544 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 56555 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 56566 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_main0_tosys_s_8_5_btus_1 bridge_main0_tosys_s_8_5_btus_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 56935 main0_tosys_s register btus_1 0x1B060 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 56593 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 56604 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 56615 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 56626 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 56637 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 56648 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 56659 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 56670 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 56681 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 56692 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 56703 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 56714 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 56725 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 56736 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 56747 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 56758 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 56769 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 56780 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 56791 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 56802 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 56813 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 56824 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 56835 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 56846 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 56857 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 56868 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 56879 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 56890 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 56901 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 56912 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 56923 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 56934 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_main0_tosys_s_8_5_btrl_0 bridge_main0_tosys_s_8_5_btrl_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57011 main0_tosys_s register btrl_0 0x1B080 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 56959 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 56970 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 56985 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 56999 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 57010 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tosys_s_8_5_btrl_1 bridge_main0_tosys_s_8_5_btrl_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57087 main0_tosys_s register btrl_1 0x1B088 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 57035 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 57046 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 57061 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 57075 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 57086 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tosys_s_8_5_btrl_2 bridge_main0_tosys_s_8_5_btrl_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57163 main0_tosys_s register btrl_2 0x1B090 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 57111 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 57122 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 57137 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 57151 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 57162 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tosys_s_8_5_btrl_3 bridge_main0_tosys_s_8_5_btrl_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57239 main0_tosys_s register btrl_3 0x1B098 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 57187 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 57198 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 57213 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 57227 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 57238 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_main0_tosys_s_8_5_btperr bridge_main0_tosys_s_8_5_btperr PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57441 main0_tosys_s register btperr 0x1B0A8 R/W 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 57264 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 57275 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 57286 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 57297 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 57308 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 57319 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 57330 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 57341 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 57352 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 57363 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 57374 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 57385 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 57396 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 57407 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 57418 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 57429 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 57440 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_tosys_s_8_5_btperrm bridge_main0_tosys_s_8_5_btperrm PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57641 main0_tosys_s register btperrm 0x1B0B0 R/W 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 57464 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 57475 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 57486 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 57497 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 57508 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 57519 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 57530 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 57541 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 57552 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 57563 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 57574 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 57585 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 57596 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 57607 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 57618 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 57629 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 57640 UNSD 31 16 0x0000 R register pcie_noc.bridge_main0_tosys_s_8_5_rxe bridge_main0_tosys_s_8_5_rxe PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57749 main0_tosys_s register rxe 0x1B120 R/W 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 57669 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 57680 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 57691 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 57702 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 57714 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 57725 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 57737 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 57748 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_tosys_s_8_5_rxem bridge_main0_tosys_s_8_5_rxem PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 57821 main0_tosys_s register rxem 0x1B128 R/W 0x00000050 Pcie_noc_bridge_main0_tosys_s_8_5_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 57770 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 57784 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 57795 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 57809 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 57820 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_main0_tosys_s_8_5_brs_0 bridge_main0_tosys_s_8_5_brs_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 58095 main0_tosys_s register brs_0 0x1B130 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 57845 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 57856 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 57867 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 57878 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 57889 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 57899 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 57910 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 57921 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 57932 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 57943 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 57954 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 57964 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 57975 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 57986 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 57997 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 58008 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 58019 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 58029 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 58040 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 58051 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 58062 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 58073 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 58084 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 58094 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_tosys_s_8_5_brs_1 bridge_main0_tosys_s_8_5_brs_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 58369 main0_tosys_s register brs_1 0x1B138 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 58119 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 58130 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 58141 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 58152 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 58163 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 58173 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 58184 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 58195 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 58206 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 58217 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 58228 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 58238 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 58249 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 58260 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 58271 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 58282 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 58293 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 58303 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 58314 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 58325 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 58336 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 58347 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 58358 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 58368 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_main0_tosys_s_8_5_brus bridge_main0_tosys_s_8_5_brus PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 58438 main0_tosys_s register brus 0x1B1B0 R 0x00000000 Pcie_noc_bridge_main0_tosys_s_8_5_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 58394 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 58405 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 58416 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 58427 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 58437 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_main0_tosys_s_8_5_brperr0 bridge_main0_tosys_s_8_5_brperr0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 58666 main0_tosys_s register brperr0 0x1B1D0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 58476 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 58487 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 58498 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 58510 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 58521 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 58532 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 58543 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 58554 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 58565 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 58577 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 58588 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 58599 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 58610 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 58621 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 58632 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 58643 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 58654 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 58665 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_brperr1 bridge_main0_tosys_s_8_5_brperr1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 58782 main0_tosys_s register brperr1 0x1B1D8 R 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 58704 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 58715 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 58726 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 58737 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 58748 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 58759 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 58770 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 58781 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_brperrm0 bridge_main0_tosys_s_8_5_brperrm0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59003 main0_tosys_s register brperrm0 0x1B1E0 R/W 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 58809 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 58821 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 58832 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 58844 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 58856 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 58867 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 58878 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 58890 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 58901 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 58913 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 58925 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 58936 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 58947 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 58958 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 58969 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 58980 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 58991 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 59002 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_main0_tosys_s_8_5_brperrm1 bridge_main0_tosys_s_8_5_brperrm1 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59108 main0_tosys_s register brperrm1 0x1B1E8 R 0x0000000000000000 Pcie_noc_bridge_main0_tosys_s_8_5_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 59030 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 59041 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 59052 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 59063 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 59074 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 59085 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 59096 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 59107 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59224 p0_p0_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x1C000 R/W 0x0000000058200010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 59148 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59159 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 59170 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 59182 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 59193 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 59205 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 59216 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59223 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59316 p0_p0_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x1C008 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 59241 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59252 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 59263 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 59274 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 59286 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 59297 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 59308 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59315 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59432 p0_p0_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x1C020 R/W 0x0000007f80000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 59356 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59367 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 59378 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 59390 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 59401 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 59413 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 59424 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59431 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59524 p0_p0_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x1C028 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 59449 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59460 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 59471 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 59482 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 59494 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 59505 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 59516 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59523 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59565 p0_p0_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x1C030 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 59542 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 59553 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 59564 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59681 p0_p0_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x1C040 R/W 0x0000007f80001010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 59605 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59616 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 59627 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 59639 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 59650 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 59662 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 59673 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59680 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59773 p0_p0_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x1C048 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 59698 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59709 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 59720 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 59731 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 59743 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 59754 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 59765 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59772 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59814 p0_p0_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x1C050 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 59791 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 59802 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 59813 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 59930 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x1C060 R/W 0x0000000080000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 59854 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59865 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 59876 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 59888 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 59899 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 59911 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 59922 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 59929 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60022 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x1C068 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 59947 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 59958 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 59969 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 59980 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 59992 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 60003 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 60014 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60021 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60138 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x1C080 R/W 0x0000008000200010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 60062 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60073 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 60084 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 60096 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 60107 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 60119 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 60130 BASE_ADDRESS_0_33 Base address 39 6 0x200008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60137 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60230 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x1C088 R/W 0x000000ffffe00000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 60155 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60166 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 60177 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 60188 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 60200 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 60211 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 60222 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60229 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60346 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x1C0A0 R/W 0x0000008000400010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 60270 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60281 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 60292 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 60304 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 60315 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 60327 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 60338 BASE_ADDRESS_0_33 Base address 39 6 0x200010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60345 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60438 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x1C0A8 R/W 0x000000ffffc00000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 60363 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60374 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 60385 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 60396 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 60408 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 60419 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 60430 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60437 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60554 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x1C0C0 R/W 0x0000008000800010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 60478 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60489 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 60500 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 60512 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 60523 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 60535 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 60546 BASE_ADDRESS_0_33 Base address 39 6 0x200020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60553 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60646 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x1C0C8 R/W 0x000000ffff800000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 60571 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60582 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 60593 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 60604 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 60616 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 60627 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 60638 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60645 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60762 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x1C0E0 R/W 0x0000008001000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 60686 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60697 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 60708 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 60720 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 60731 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 60743 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 60754 BASE_ADDRESS_0_33 Base address 39 6 0x200040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60761 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60854 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x1C0E8 R/W 0x000000ffff000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 60779 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60790 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 60801 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 60812 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 60824 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 60835 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 60846 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60853 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 60970 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x1C100 R/W 0x0000008002000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 60894 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60905 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 60916 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 60928 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 60939 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 60951 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 60962 BASE_ADDRESS_0_33 Base address 39 6 0x200080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 60969 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61062 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x1C108 R/W 0x000000fffe000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 60987 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 60998 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 61009 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 61020 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 61032 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 61043 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 61054 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61061 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61178 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x1C120 R/W 0x0000008004000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 61102 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61113 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 61124 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 61136 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 61147 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 61159 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 61170 BASE_ADDRESS_0_33 Base address 39 6 0x200100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61177 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61270 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x1C128 R/W 0x000000fffc000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 61195 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61206 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 61217 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 61228 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 61240 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 61251 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 61262 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61269 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61386 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x1C140 R/W 0x0000008008000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 61310 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61321 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 61332 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 61344 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 61355 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 61367 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 61378 BASE_ADDRESS_0_33 Base address 39 6 0x200200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61385 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61478 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x1C148 R/W 0x000000fff8000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 61403 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61414 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 61425 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 61436 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 61448 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 61459 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 61470 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61477 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61594 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x1C160 R/W 0x0000008010000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 61518 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61529 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 61540 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 61552 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 61563 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 61575 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 61586 BASE_ADDRESS_0_33 Base address 39 6 0x200400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61593 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61686 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x1C168 R/W 0x000000fff0000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 61611 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61622 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 61633 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 61644 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 61656 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 61667 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 61678 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61685 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61802 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0x1C180 R/W 0x0000008020000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 61726 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61737 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 61748 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 61760 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 61771 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 61783 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 61794 BASE_ADDRESS_0_33 Base address 39 6 0x200800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61801 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 61894 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0x1C188 R/W 0x000000ffe0000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 61819 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61830 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 61841 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 61852 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 61864 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 61875 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 61886 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 61893 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62010 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0x1C1A0 R/W 0x0000008040000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 61934 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 61945 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 61956 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 61968 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 61979 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 61991 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 62002 BASE_ADDRESS_0_33 Base address 39 6 0x201000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62009 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62102 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0x1C1A8 R/W 0x000000ffc0000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 62027 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62038 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 62049 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 62060 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 62072 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 62083 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 62094 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62101 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62218 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0x1C1C0 R/W 0x0000008080000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 62142 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62153 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 62164 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 62176 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 62187 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 62199 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 62210 BASE_ADDRESS_0_33 Base address 39 6 0x202000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62217 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62310 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0x1C1C8 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 62235 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62246 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 62257 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 62268 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 62280 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 62291 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 62302 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62309 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62426 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0x1C1E0 R/W 0x0000008100000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 62350 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62361 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 62372 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 62384 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 62395 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 62407 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 62418 BASE_ADDRESS_0_33 Base address 39 6 0x204000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62425 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62518 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0x1C1E8 R/W 0x000000ff00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 62443 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62454 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 62465 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 62476 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 62488 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 62499 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 62510 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62517 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62634 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0x1C200 R/W 0x0000008200000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 62558 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62569 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 62580 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 62592 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 62603 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 62615 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 62626 BASE_ADDRESS_0_33 Base address 39 6 0x208000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62633 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62726 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0x1C208 R/W 0x000000fe00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 62651 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62662 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 62673 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 62684 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 62696 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 62707 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 62718 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62725 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62842 p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0x1C220 R/W 0x0000008400000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 62766 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62777 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 62788 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 62800 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 62811 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 62823 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 62834 BASE_ADDRESS_0_33 Base address 39 6 0x210000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62841 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 62934 p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0x1C228 R/W 0x000000fc00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 62859 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62870 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 62881 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 62892 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 62904 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 62915 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 62926 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 62933 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63050 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0x1C240 R/W 0x0000000002000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 62974 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 62985 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 62996 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 63008 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 63019 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 63031 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 63042 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63049 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63142 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0x1C248 R/W 0x000000ffffff0000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 63067 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63078 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 63089 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 63100 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 63112 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 63123 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 63134 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63141 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63258 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0x1C260 R/W 0x0000000020007000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 63182 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63193 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 63204 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 63216 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 63227 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 63239 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 63250 BASE_ADDRESS_0_33 Base address 39 6 0x0008001c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63257 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63350 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0x1C268 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 63275 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63286 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 63297 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 63308 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 63320 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 63331 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 63342 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63349 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63466 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0x1C280 R/W 0x0000000030001000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 63390 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63401 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 63412 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 63424 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 63435 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 63447 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 63458 BASE_ADDRESS_0_33 Base address 39 6 0x000c00040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63465 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63558 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0x1C288 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 63483 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63494 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 63505 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 63516 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 63528 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 63539 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 63550 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63557 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63674 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0x1C2A0 R/W 0x0000000030003000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 63598 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63609 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 63620 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 63632 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 63643 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 63655 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 63666 BASE_ADDRESS_0_33 Base address 39 6 0x000c000c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63673 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63766 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0x1C2A8 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 63691 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63702 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 63713 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 63724 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 63736 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 63747 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 63758 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63765 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63882 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0x1C2C0 R/W 0x0000000030008000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 63806 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63817 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 63828 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 63840 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 63851 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 63863 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 63874 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63881 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 63974 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0x1C2C8 R/W 0x000000ffffffe000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 63899 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 63910 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 63921 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 63932 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 63944 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 63955 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 63966 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 63973 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64090 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0x1C2E0 R/W 0x0000000100000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 64014 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64025 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 64036 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 64048 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 64059 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 64071 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 64082 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64089 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64182 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0x1C2E8 R/W 0x000000ff00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 64107 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64118 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 64129 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 64140 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 64152 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 64163 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 64174 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64181 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64298 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0x1C300 R/W 0x000000c000200010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 64222 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64233 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 64244 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 64256 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 64267 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 64279 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 64290 BASE_ADDRESS_0_33 Base address 39 6 0x300008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64297 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64390 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0x1C308 R/W 0x000000ffffe00000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 64315 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64326 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 64337 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 64348 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 64360 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 64371 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 64382 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64389 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64506 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0x1C320 R/W 0x000000c000400010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 64430 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64441 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 64452 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 64464 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 64475 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 64487 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 64498 BASE_ADDRESS_0_33 Base address 39 6 0x300010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64505 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64598 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0x1C328 R/W 0x000000ffffc00000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 64523 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64534 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 64545 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 64556 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 64568 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 64579 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 64590 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64597 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64714 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0x1C340 R/W 0x000000c000800010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 64638 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64649 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 64660 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 64672 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 64683 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 64695 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 64706 BASE_ADDRESS_0_33 Base address 39 6 0x300020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64713 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64806 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0x1C348 R/W 0x000000ffff800000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 64731 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64742 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 64753 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 64764 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 64776 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 64787 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 64798 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64805 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 64922 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0x1C360 R/W 0x000000c001000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 64846 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64857 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 64868 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 64880 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 64891 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 64903 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 64914 BASE_ADDRESS_0_33 Base address 39 6 0x300040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 64921 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65014 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0x1C368 R/W 0x000000ffff000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 64939 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 64950 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 64961 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 64972 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 64984 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 64995 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 65006 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65013 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65130 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0x1C380 R/W 0x000000c002000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 65054 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65065 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 65076 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 65088 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 65099 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 65111 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 65122 BASE_ADDRESS_0_33 Base address 39 6 0x300080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65129 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65222 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0x1C388 R/W 0x000000fffe000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 65147 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65158 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 65169 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 65180 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 65192 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 65203 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 65214 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65221 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65338 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0x1C3A0 R/W 0x000000c004000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 65262 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65273 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 65284 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 65296 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 65307 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 65319 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 65330 BASE_ADDRESS_0_33 Base address 39 6 0x300100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65337 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65430 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0x1C3A8 R/W 0x000000fffc000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 65355 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65366 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 65377 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 65388 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 65400 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 65411 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 65422 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65429 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65546 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0x1C3C0 R/W 0x000000c008000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 65470 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65481 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 65492 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 65504 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 65515 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 65527 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 65538 BASE_ADDRESS_0_33 Base address 39 6 0x300200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65545 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65638 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0x1C3C8 R/W 0x000000fff8000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 65563 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65574 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 65585 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 65596 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 65608 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 65619 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 65630 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65637 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65754 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x1C3E0 R/W 0x000000c010000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 65678 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65689 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 65700 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 65712 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 65723 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 65735 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 65746 BASE_ADDRESS_0_33 Base address 39 6 0x300400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65753 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65846 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x1C3E8 R/W 0x000000fff0000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 65771 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65782 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 65793 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 65804 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 65816 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 65827 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 65838 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65845 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 65962 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x1C400 R/W 0x000000c020000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 65886 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65897 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 65908 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 65920 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 65931 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 65943 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 65954 BASE_ADDRESS_0_33 Base address 39 6 0x300800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 65961 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66054 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x1C408 R/W 0x000000ffe0000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 65979 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 65990 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 66001 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 66012 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 66024 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 66035 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 66046 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66053 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66170 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x1C420 R/W 0x000000c040000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 66094 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66105 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 66116 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 66128 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SET ns_noc_io_pcie_soc_ip.csr 66139 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 66151 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 66162 BASE_ADDRESS_0_33 Base address 39 6 0x301000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66169 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66262 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x1C428 R/W 0x000000ffc0000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 66187 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66198 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 66209 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 66220 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SET ns_noc_io_pcie_soc_ip.csr 66232 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 66243 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 66254 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66261 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66378 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x1C440 R/W 0x000000c080000010 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 66302 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66313 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 66324 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 66336 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SET ns_noc_io_pcie_soc_ip.csr 66347 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 66359 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 66370 BASE_ADDRESS_0_33 Base address 39 6 0x302000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66377 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66470 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x1C448 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 66395 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66406 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 66417 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 66428 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SET ns_noc_io_pcie_soc_ip.csr 66440 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 66451 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 66462 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66469 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66586 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x1C460 R/W 0x000000c100000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 66510 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66521 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 66532 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 66544 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SET ns_noc_io_pcie_soc_ip.csr 66555 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 66567 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 66578 BASE_ADDRESS_0_33 Base address 39 6 0x304000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66585 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66678 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x1C468 R/W 0x000000ff00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 66603 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66614 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 66625 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 66636 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SET ns_noc_io_pcie_soc_ip.csr 66648 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 66659 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 66670 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66677 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66794 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x1C480 R/W 0x000000c200000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 66718 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66729 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 66740 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 66752 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SET ns_noc_io_pcie_soc_ip.csr 66763 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 66775 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 66786 BASE_ADDRESS_0_33 Base address 39 6 0x308000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66793 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 66886 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x1C488 R/W 0x000000fe00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 66811 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66822 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 66833 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 66844 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SET ns_noc_io_pcie_soc_ip.csr 66856 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 66867 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 66878 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 66885 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67002 p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x1C4A0 R/W 0x000000c400000000 Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 66926 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 66937 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 66948 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 66960 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SET ns_noc_io_pcie_soc_ip.csr 66971 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 66983 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 66994 BASE_ADDRESS_0_33 Base address 39 6 0x310000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 67001 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67094 p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x1C4A8 R/W 0x000000fc00000000 Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 67019 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 67030 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 67041 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 67052 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SET ns_noc_io_pcie_soc_ip.csr 67064 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 67075 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 67086 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 67093 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_p_0 bridge_p0_p0_m_3_6_p_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67159 p0_p0_m register p_0 0x1F000 R/W 0x00000003 Pcie_noc_bridge_p0_p0_m_3_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 67122 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 67134 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 67146 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 67158 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_p_1 bridge_p0_p0_m_3_6_p_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67225 p0_p0_m register p_1 0x1F008 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 67188 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 67200 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 67212 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 67224 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_p_2 bridge_p0_p0_m_3_6_p_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67291 p0_p0_m register p_2 0x1F010 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 67254 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 67266 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 67278 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 67290 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_p_3 bridge_p0_p0_m_3_6_p_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67357 p0_p0_m register p_3 0x1F018 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 67320 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 67332 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 67344 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 67356 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_txe bridge_p0_p0_m_3_6_txe PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67503 p0_p0_m register txe 0x1F040 R/W 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 67384 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 67396 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 67411 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 67424 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 67438 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 67452 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 67466 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 67480 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 67491 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 67502 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_txem bridge_p0_p0_m_3_6_txem PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67582 p0_p0_m register txem 0x1F048 R/W 0x00000008 Pcie_noc_bridge_p0_p0_m_3_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 67526 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 67537 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 67548 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 67559 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 67570 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 67581 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p0_m_3_6_btus_0 bridge_p0_p0_m_3_6_btus_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 67950 p0_p0_m register btus_0 0x1F058 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 67608 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 67619 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 67630 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 67641 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 67652 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 67663 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 67674 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 67685 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 67696 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 67707 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 67718 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 67729 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 67740 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 67751 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 67762 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 67773 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 67784 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 67795 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 67806 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 67817 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 67828 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 67839 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 67850 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 67861 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 67872 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 67883 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 67894 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 67905 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 67916 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 67927 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 67938 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 67949 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_p0_m_3_6_btus_1 bridge_p0_p0_m_3_6_btus_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 68318 p0_p0_m register btus_1 0x1F060 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 67976 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 67987 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 67998 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 68009 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 68020 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 68031 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 68042 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 68053 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 68064 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 68075 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 68086 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 68097 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 68108 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 68119 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 68130 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 68141 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 68152 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 68163 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 68174 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 68185 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 68196 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 68207 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 68218 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 68229 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 68240 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 68251 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 68262 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 68273 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 68284 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 68295 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 68306 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 68317 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_p0_m_3_6_btrl_0 bridge_p0_p0_m_3_6_btrl_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 68394 p0_p0_m register btrl_0 0x1F080 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 68342 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 68353 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 68368 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 68382 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 68393 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_m_3_6_btrl_1 bridge_p0_p0_m_3_6_btrl_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 68470 p0_p0_m register btrl_1 0x1F088 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 68418 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 68429 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 68444 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 68458 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 68469 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_m_3_6_btrl_2 bridge_p0_p0_m_3_6_btrl_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 68546 p0_p0_m register btrl_2 0x1F090 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 68494 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 68505 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 68520 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 68534 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 68545 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_m_3_6_btrl_3 bridge_p0_p0_m_3_6_btrl_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 68622 p0_p0_m register btrl_3 0x1F098 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 68570 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 68581 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 68596 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 68610 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 68621 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_m_3_6_btperr bridge_p0_p0_m_3_6_btperr PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 68824 p0_p0_m register btperr 0x1F0A8 R/W 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 68647 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 68658 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 68669 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 68680 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 68691 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 68702 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 68713 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 68724 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 68735 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 68746 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 68757 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 68768 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 68779 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 68790 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 68801 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 68812 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 68823 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p0_m_3_6_btperrm bridge_p0_p0_m_3_6_btperrm PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 69024 p0_p0_m register btperrm 0x1F0B0 R/W 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 68847 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 68858 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 68869 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 68880 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 68891 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 68902 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 68913 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 68924 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 68935 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 68946 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 68957 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 68968 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 68979 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 68990 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 69001 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 69012 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 69023 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p0_m_3_6_rxe bridge_p0_p0_m_3_6_rxe PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 69132 p0_p0_m register rxe 0x1F120 R/W 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 69052 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 69063 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 69074 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 69085 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 69097 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 69108 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 69120 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 69131 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p0_m_3_6_rxem bridge_p0_p0_m_3_6_rxem PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 69204 p0_p0_m register rxem 0x1F128 R/W 0x00000050 Pcie_noc_bridge_p0_p0_m_3_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 69153 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 69167 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 69178 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 69192 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 69203 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p0_m_3_6_brs_0 bridge_p0_p0_m_3_6_brs_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 69478 p0_p0_m register brs_0 0x1F130 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 69228 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 69239 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 69250 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 69261 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 69272 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 69282 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 69293 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 69304 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 69315 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 69326 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 69337 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 69347 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 69358 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 69369 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 69380 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 69391 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 69402 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 69412 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 69423 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 69434 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 69445 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 69456 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 69467 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 69477 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p0_m_3_6_brs_1 bridge_p0_p0_m_3_6_brs_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 69752 p0_p0_m register brs_1 0x1F138 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 69502 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 69513 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 69524 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 69535 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 69546 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 69556 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 69567 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 69578 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 69589 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 69600 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 69611 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 69621 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 69632 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 69643 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 69654 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 69665 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 69676 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 69686 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 69697 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 69708 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 69719 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 69730 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 69741 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 69751 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p0_m_3_6_brus bridge_p0_p0_m_3_6_brus PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 69821 p0_p0_m register brus 0x1F1B0 R 0x00000000 Pcie_noc_bridge_p0_p0_m_3_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 69777 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 69788 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 69799 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 69810 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 69820 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_p0_m_3_6_brperr0 bridge_p0_p0_m_3_6_brperr0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70049 p0_p0_m register brperr0 0x1F1D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 69859 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 69870 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 69881 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 69893 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 69904 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 69915 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 69926 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 69937 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 69948 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 69960 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 69971 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 69982 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 69993 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 70004 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 70015 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 70026 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 70037 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 70048 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_brperr1 bridge_p0_p0_m_3_6_brperr1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70165 p0_p0_m register brperr1 0x1F1D8 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 70087 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 70098 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 70109 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 70120 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 70131 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 70142 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 70153 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 70164 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_brperrm0 bridge_p0_p0_m_3_6_brperrm0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70386 p0_p0_m register brperrm0 0x1F1E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 70192 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 70204 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 70215 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 70227 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 70239 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 70250 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 70261 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 70273 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 70284 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 70296 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 70308 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 70319 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 70330 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 70341 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 70352 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 70363 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 70374 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 70385 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_brperrm1 bridge_p0_p0_m_3_6_brperrm1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70491 p0_p0_m register brperrm1 0x1F1E8 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 70413 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 70424 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 70435 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 70446 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 70457 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 70468 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 70479 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 70490 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_am_tocfg bridge_p0_p0_m_3_6_am_tocfg PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70565 p0_p0_m register am_tocfg 0x1FC00 R/W 0x000000000000001f Pcie_noc_bridge_p0_p0_m_3_6_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 70528 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 70539 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 70553 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 70564 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_osslv bridge_p0_p0_m_3_6_am_osslv PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70600 p0_p0_m register am_osslv 0x1FC08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 70588 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 70599 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_cgc bridge_p0_p0_m_3_6_am_cgc PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70637 p0_p0_m register am_cgc 0x1FC10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_p0_m_3_6_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 70625 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 70636 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_cgo bridge_p0_p0_m_3_6_am_cgo PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70672 p0_p0_m register am_cgo 0x1FC18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 70660 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 70671 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_cfg bridge_p0_p0_m_3_6_am_cfg PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70709 p0_p0_m register am_cfg 0x1FC20 R/W 0x0000000000000001 Pcie_noc_bridge_p0_p0_m_3_6_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 70697 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 70708 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_sts bridge_p0_p0_m_3_6_am_sts PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70837 p0_p0_m register am_sts 0x1FD00 R 0x000000000000000c Pcie_noc_bridge_p0_p0_m_3_6_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 70742 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 70756 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 70768 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 70780 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 70791 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 70802 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 70814 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 70826 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 70836 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_bridge_id bridge_p0_p0_m_3_6_am_bridge_id PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 70867 p0_p0_m register am_bridge_id 0x1FD08 R 0x0000000000000003 Pcie_noc_bridge_p0_p0_m_3_6_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 70856 ID Unique bridge ID 15 0 0x0003 R UNSD_63_16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 70866 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_err bridge_p0_p0_m_3_6_am_err PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71363 p0_p0_m register am_err 0x1FE00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 70889 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 70901 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 70913 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 70925 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 70937 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 70949 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 70962 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 70975 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 70986 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 70997 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 71008 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 71019 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 71030 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 71041 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 71052 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 71063 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 71074 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 71086 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 71097 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 71108 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 71119 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 71130 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 71142 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 71154 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 71165 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 71177 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 71188 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 71199 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 71210 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 71221 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 71232 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 71243 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 71255 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 71267 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 71279 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 71291 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 71303 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 71315 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 71327 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 71339 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 71351 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 71362 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_am_toslvid bridge_p0_p0_m_3_6_am_toslvid PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71408 p0_p0_m register am_toslvid 0x1FE08 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 71386 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 71397 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 71407 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_era bridge_p0_p0_m_3_6_am_era PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71430 p0_p0_m register am_era 0x1FE10 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 71429 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_ewa bridge_p0_p0_m_3_6_am_ewa PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71452 p0_p0_m register am_ewa 0x1FE18 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 71451 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_intm bridge_p0_p0_m_3_6_am_intm PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71936 p0_p0_m register am_intm 0x1FE40 R/W 0x00007e07004f004f Pcie_noc_bridge_p0_p0_m_3_6_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 71474 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 71485 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 71496 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 71507 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 71518 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 71529 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 71540 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 71551 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 71562 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 71573 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 71584 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 71595 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 71606 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 71617 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 71628 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 71639 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 71650 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 71661 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 71672 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 71683 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 71694 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 71705 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 71716 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 71727 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 71738 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 71750 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 71761 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 71772 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 71783 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 71794 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 71805 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 71816 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 71828 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 71840 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 71852 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 71864 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 71876 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 71888 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 71900 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 71912 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 71924 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 71935 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_m_3_6_am_caddr bridge_p0_p0_m_3_6_am_caddr PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71958 p0_p0_m register am_caddr 0x1FF00 R/W 0xffffffffffffffff Pcie_noc_bridge_p0_p0_m_3_6_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 71957 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_p0_p0_m_3_6_am_caddrmsk bridge_p0_p0_m_3_6_am_caddrmsk PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 71981 p0_p0_m register am_caddrmsk 0x1FF08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 71980 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_p0_p0_m_3_6_am_ccmd0 bridge_p0_p0_m_3_6_am_ccmd0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72171 p0_p0_m register am_ccmd0 0x1FF10 R/W 0x0000000003fff33f Pcie_noc_bridge_p0_p0_m_3_6_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 72003 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 72014 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 72025 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 72036 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 72047 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 72058 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 72069 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 72080 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 72091 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 72102 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 72113 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 72124 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 72136 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 72147 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 72159 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 72170 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk0 bridge_p0_p0_m_3_6_am_ccmdmsk0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72315 p0_p0_m register am_ccmdmsk0 0x1FF18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 72193 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 72204 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 72215 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 72226 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 72237 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 72248 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 72259 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 72270 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 72281 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 72292 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 72303 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 72314 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_cntr0 bridge_p0_p0_m_3_6_am_cntr0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72350 p0_p0_m register am_cntr0 0x1FF20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 72338 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 72349 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_latnum0 bridge_p0_p0_m_3_6_am_latnum0 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72389 p0_p0_m register am_latnum0 0x1FF28 R/W 0x0000000000000007 Pcie_noc_bridge_p0_p0_m_3_6_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 72377 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 72388 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_ccmd1 bridge_p0_p0_m_3_6_am_ccmd1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72579 p0_p0_m register am_ccmd1 0x1FF30 R/W 0x0000000003fff33f Pcie_noc_bridge_p0_p0_m_3_6_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 72411 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 72422 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 72433 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 72444 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 72455 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 72466 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 72477 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 72488 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 72499 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 72510 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 72521 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 72532 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 72544 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 72555 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 72567 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 72578 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk1 bridge_p0_p0_m_3_6_am_ccmdmsk1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72723 p0_p0_m register am_ccmdmsk1 0x1FF38 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 72601 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 72612 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 72623 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 72634 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 72645 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 72656 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 72667 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 72678 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 72689 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 72700 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 72711 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 72722 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_cntr1 bridge_p0_p0_m_3_6_am_cntr1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72758 p0_p0_m register am_cntr1 0x1FF40 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 72746 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 72757 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_latnum1 bridge_p0_p0_m_3_6_am_latnum1 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72797 p0_p0_m register am_latnum1 0x1FF48 R/W 0x0000000000000007 Pcie_noc_bridge_p0_p0_m_3_6_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 72785 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 72796 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_arovrd bridge_p0_p0_m_3_6_am_arovrd PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 72910 p0_p0_m register am_arovrd 0x1FF60 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 72815 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 72828 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 72839 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 72850 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 72863 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 72874 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 72885 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 72898 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 72909 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p0_m_3_6_am_awovrd bridge_p0_p0_m_3_6_am_awovrd PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73023 p0_p0_m register am_awovrd 0x1FF68 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_m_3_6_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 72928 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 72941 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 72952 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 72963 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 72976 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 72987 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 72998 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 73011 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 73022 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgc bridge_p0_p0_reg_s_9_6_as_cgc PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73060 p0_p0_reg_s register as_cgc 0x21C10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 73048 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 73059 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgo bridge_p0_p0_reg_s_9_6_as_cgo PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73095 p0_p0_reg_s register as_cgo 0x21C18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 73083 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 73094 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_sts bridge_p0_p0_reg_s_9_6_as_sts PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73169 p0_p0_reg_s register as_sts 0x21D00 R 0x000000000000000c Pcie_noc_bridge_p0_p0_reg_s_9_6_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 73118 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 73134 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 73146 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 73158 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 73168 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_id bridge_p0_p0_reg_s_9_6_as_bridge_id PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73199 p0_p0_reg_s register as_bridge_id 0x21D08 R 0x0000000000000009 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 73188 ID Unique bridge ID 15 0 0x0009 R UNSD_63_16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 73198 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_err bridge_p0_p0_reg_s_9_6_as_err PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73552 p0_p0_reg_s register as_err 0x21E00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 73220 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 73232 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 73245 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 73259 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 73271 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 73282 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 73294 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 73306 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 73319 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 73331 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 73342 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 73354 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 73365 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 73376 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 73387 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 73398 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 73409 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 73420 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 73432 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 73444 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 73456 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 73468 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 73480 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 73492 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 73504 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 73516 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 73528 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 73540 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 73551 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_intm bridge_p0_p0_reg_s_9_6_as_intm PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73892 p0_p0_reg_s register as_intm 0x21E40 R/W 0x0000007d000b0013 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 73573 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 73584 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 73595 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 73606 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 73617 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 73628 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 73639 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 73650 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 73661 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 73672 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 73683 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 73694 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 73705 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 73716 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 73727 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 73738 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 73749 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 73760 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 73772 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 73784 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 73796 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 73808 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 73820 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 73832 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 73844 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 73856 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 73868 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 73880 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 73891 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmd bridge_p0_p0_reg_s_9_6_as_ccmd PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 73967 p0_p0_reg_s register as_ccmd 0x21F00 R/W 0x0000000003000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 73910 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 73921 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 73932 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 73943 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 73955 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 73966 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmsk bridge_p0_p0_reg_s_9_6_as_ccmdmsk PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74019 p0_p0_reg_s register as_ccmdmsk 0x21F08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 73985 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 73996 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 74007 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 74018 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_cntr bridge_p0_p0_reg_s_9_6_as_cntr PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74049 p0_p0_reg_s register as_cntr 0x21F10 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 74038 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 74048 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrd bridge_p0_p0_reg_s_9_6_as_arovrd PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74162 p0_p0_reg_s register as_arovrd 0x21F18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 74067 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 74080 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 74091 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 74102 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 74115 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 74126 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 74137 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 74150 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 74161 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrd bridge_p0_p0_reg_s_9_6_as_awovrd PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74275 p0_p0_reg_s register as_awovrd 0x21F20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 74180 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 74193 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 74204 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 74215 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 74228 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 74239 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 74250 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 74263 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 74274 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_p_0 bridge_p0_p0_reg_s_9_6_p_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74340 p0_p0_reg_s register p_0 0x23000 R/W 0x00000003 Pcie_noc_bridge_p0_p0_reg_s_9_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 74303 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 74315 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 74327 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 74339 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_p_1 bridge_p0_p0_reg_s_9_6_p_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74406 p0_p0_reg_s register p_1 0x23008 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 74369 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 74381 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 74393 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 74405 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_p_2 bridge_p0_p0_reg_s_9_6_p_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74472 p0_p0_reg_s register p_2 0x23010 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 74435 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 74447 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 74459 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 74471 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_p_3 bridge_p0_p0_reg_s_9_6_p_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74538 p0_p0_reg_s register p_3 0x23018 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 74501 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 74513 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 74525 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 74537 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_txe bridge_p0_p0_reg_s_9_6_txe PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74684 p0_p0_reg_s register txe 0x23040 R/W 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 74565 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 74577 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 74592 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 74605 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 74619 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 74633 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 74647 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 74661 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 74672 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 74683 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_txem bridge_p0_p0_reg_s_9_6_txem PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 74763 p0_p0_reg_s register txem 0x23048 R/W 0x00000008 Pcie_noc_bridge_p0_p0_reg_s_9_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 74707 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 74718 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 74729 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 74740 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 74751 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 74762 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btus_0 bridge_p0_p0_reg_s_9_6_btus_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 75131 p0_p0_reg_s register btus_0 0x23058 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 74789 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 74800 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 74811 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 74822 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 74833 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 74844 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 74855 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 74866 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 74877 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 74888 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 74899 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 74910 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 74921 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 74932 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 74943 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 74954 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 74965 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 74976 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 74987 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 74998 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 75009 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 75020 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 75031 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 75042 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 75053 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 75064 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 75075 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 75086 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 75097 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 75108 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 75119 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 75130 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btus_1 bridge_p0_p0_reg_s_9_6_btus_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 75499 p0_p0_reg_s register btus_1 0x23060 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 75157 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 75168 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 75179 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 75190 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 75201 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 75212 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 75223 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 75234 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 75245 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 75256 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 75267 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 75278 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 75289 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 75300 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 75311 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 75322 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 75333 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 75344 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 75355 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 75366 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 75377 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 75388 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 75399 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 75410 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 75421 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 75432 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 75443 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 75454 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 75465 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 75476 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 75487 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 75498 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_0 bridge_p0_p0_reg_s_9_6_btrl_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 75575 p0_p0_reg_s register btrl_0 0x23080 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 75523 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 75534 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 75549 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 75563 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 75574 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_1 bridge_p0_p0_reg_s_9_6_btrl_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 75651 p0_p0_reg_s register btrl_1 0x23088 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 75599 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 75610 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 75625 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 75639 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 75650 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_2 bridge_p0_p0_reg_s_9_6_btrl_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 75727 p0_p0_reg_s register btrl_2 0x23090 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 75675 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 75686 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 75701 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 75715 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 75726 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btrl_3 bridge_p0_p0_reg_s_9_6_btrl_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 75803 p0_p0_reg_s register btrl_3 0x23098 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 75751 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 75762 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 75777 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 75791 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 75802 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btperr bridge_p0_p0_reg_s_9_6_btperr PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 76005 p0_p0_reg_s register btperr 0x230A8 R/W 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 75828 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 75839 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 75850 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 75861 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 75872 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 75883 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 75894 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 75905 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 75916 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 75927 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 75938 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 75949 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 75960 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 75971 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 75982 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 75993 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 76004 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_btperrm bridge_p0_p0_reg_s_9_6_btperrm PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 76205 p0_p0_reg_s register btperrm 0x230B0 R/W 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 76028 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 76039 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 76050 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 76061 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 76072 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 76083 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 76094 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 76105 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 76116 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 76127 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 76138 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 76149 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 76160 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 76171 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 76182 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 76193 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 76204 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_rxe bridge_p0_p0_reg_s_9_6_rxe PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 76313 p0_p0_reg_s register rxe 0x23120 R/W 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 76233 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 76244 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 76255 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 76266 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 76278 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 76289 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 76301 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 76312 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_rxem bridge_p0_p0_reg_s_9_6_rxem PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 76385 p0_p0_reg_s register rxem 0x23128 R/W 0x00000050 Pcie_noc_bridge_p0_p0_reg_s_9_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 76334 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 76348 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 76359 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 76373 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 76384 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brs_0 bridge_p0_p0_reg_s_9_6_brs_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 76659 p0_p0_reg_s register brs_0 0x23130 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 76409 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 76420 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 76431 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 76442 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 76453 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 76463 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 76474 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 76485 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 76496 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 76507 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 76518 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 76528 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 76539 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 76550 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 76561 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 76572 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 76583 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 76593 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 76604 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 76615 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 76626 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 76637 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 76648 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 76658 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brs_1 bridge_p0_p0_reg_s_9_6_brs_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 76933 p0_p0_reg_s register brs_1 0x23138 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 76683 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 76694 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 76705 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 76716 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 76727 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 76737 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 76748 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 76759 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 76770 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 76781 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 76792 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 76802 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 76813 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 76824 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 76835 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 76846 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 76857 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 76867 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 76878 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 76889 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 76900 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 76911 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 76922 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 76932 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brus bridge_p0_p0_reg_s_9_6_brus PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77002 p0_p0_reg_s register brus 0x231B0 R 0x00000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 76958 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 76969 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 76980 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 76991 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 77001 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brperr0 bridge_p0_p0_reg_s_9_6_brperr0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77230 p0_p0_reg_s register brperr0 0x231D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 77040 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 77051 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 77062 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 77074 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 77085 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 77096 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 77107 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 77118 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 77129 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 77141 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 77152 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 77163 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 77174 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 77185 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 77196 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 77207 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 77218 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 77229 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brperr1 bridge_p0_p0_reg_s_9_6_brperr1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77346 p0_p0_reg_s register brperr1 0x231D8 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 77268 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 77279 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 77290 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 77301 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 77312 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 77323 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 77334 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 77345 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm0 bridge_p0_p0_reg_s_9_6_brperrm0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77567 p0_p0_reg_s register brperrm0 0x231E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 77373 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 77385 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 77396 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 77408 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 77420 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 77431 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 77442 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 77454 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 77465 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 77477 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 77489 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 77500 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 77511 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 77522 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 77533 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 77544 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 77555 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 77566 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_reg_s_9_6_brperrm1 bridge_p0_p0_reg_s_9_6_brperrm1 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77672 p0_p0_reg_s register brperrm1 0x231E8 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_reg_s_9_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 77594 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 77605 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 77616 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 77627 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 77638 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 77649 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 77660 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 77671 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_as_cgc bridge_p0_p0_s_10_7_as_cgc PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77709 p0_p0_s register as_cgc 0x25C10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_p0_s_10_7_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 77697 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 77708 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_cgo bridge_p0_p0_s_10_7_as_cgo PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77744 p0_p0_s register as_cgo 0x25C18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 77732 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 77743 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_sts bridge_p0_p0_s_10_7_as_sts PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77818 p0_p0_s register as_sts 0x25D00 R 0x000000000000000c Pcie_noc_bridge_p0_p0_s_10_7_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 77767 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 77783 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 77795 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 77807 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 77817 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_bridge_id bridge_p0_p0_s_10_7_as_bridge_id PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 77848 p0_p0_s register as_bridge_id 0x25D08 R 0x000000000000000a Pcie_noc_bridge_p0_p0_s_10_7_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 77837 ID Unique bridge ID 15 0 0x000a R UNSD_63_16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 77847 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_err bridge_p0_p0_s_10_7_as_err PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78201 p0_p0_s register as_err 0x25E00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 77869 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 77881 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 77894 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 77908 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 77920 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 77931 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 77943 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 77955 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 77968 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 77980 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 77991 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 78003 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 78014 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 78025 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 78036 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 78047 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 78058 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 78069 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 78081 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 78093 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 78105 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 78117 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 78129 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 78141 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 78153 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 78165 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 78177 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 78189 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 78200 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p0_s_10_7_as_intm bridge_p0_p0_s_10_7_as_intm PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78541 p0_p0_s register as_intm 0x25E40 R/W 0x0000007d000b0013 Pcie_noc_bridge_p0_p0_s_10_7_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 78222 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 78233 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 78244 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 78255 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 78266 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 78277 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 78288 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 78299 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 78310 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 78321 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 78332 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 78343 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 78354 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 78365 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 78376 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 78387 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 78398 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 78409 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 78421 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 78433 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 78445 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 78457 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 78469 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 78481 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 78493 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 78505 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 78517 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 78529 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 78540 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p0_s_10_7_as_ccmd bridge_p0_p0_s_10_7_as_ccmd PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78616 p0_p0_s register as_ccmd 0x25F00 R/W 0x0000000003000000 Pcie_noc_bridge_p0_p0_s_10_7_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 78559 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 78570 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 78581 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 78592 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 78604 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 78615 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_ccmdmsk bridge_p0_p0_s_10_7_as_ccmdmsk PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78668 p0_p0_s register as_ccmdmsk 0x25F08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 78634 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 78645 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 78656 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 78667 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_cntr bridge_p0_p0_s_10_7_as_cntr PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78698 p0_p0_s register as_cntr 0x25F10 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 78687 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 78697 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_arovrd bridge_p0_p0_s_10_7_as_arovrd PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78811 p0_p0_s register as_arovrd 0x25F18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 78716 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 78729 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 78740 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 78751 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 78764 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 78775 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 78786 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 78799 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 78810 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p0_s_10_7_as_awovrd bridge_p0_p0_s_10_7_as_awovrd PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78924 p0_p0_s register as_awovrd 0x25F20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 78829 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 78842 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 78853 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 78864 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 78877 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 78888 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 78899 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 78912 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 78923 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p0_s_10_7_p_0 bridge_p0_p0_s_10_7_p_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 78989 p0_p0_s register p_0 0x27000 R/W 0x00000003 Pcie_noc_bridge_p0_p0_s_10_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 78952 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 78964 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 78976 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 78988 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_p_1 bridge_p0_p0_s_10_7_p_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 79055 p0_p0_s register p_1 0x27008 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 79018 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 79030 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 79042 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 79054 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_p_2 bridge_p0_p0_s_10_7_p_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 79121 p0_p0_s register p_2 0x27010 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 79084 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 79096 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 79108 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 79120 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_p_3 bridge_p0_p0_s_10_7_p_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 79187 p0_p0_s register p_3 0x27018 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 79150 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 79162 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 79174 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 79186 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_txe bridge_p0_p0_s_10_7_txe PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 79333 p0_p0_s register txe 0x27040 R/W 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 79214 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 79226 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 79241 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 79254 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 79268 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 79282 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 79296 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 79310 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 79321 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 79332 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p0_s_10_7_txem bridge_p0_p0_s_10_7_txem PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 79412 p0_p0_s register txem 0x27048 R/W 0x00000008 Pcie_noc_bridge_p0_p0_s_10_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 79356 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 79367 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 79378 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 79389 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 79400 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 79411 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p0_s_10_7_btus_0 bridge_p0_p0_s_10_7_btus_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 79780 p0_p0_s register btus_0 0x27058 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 79438 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 79449 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 79460 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 79471 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 79482 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 79493 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 79504 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 79515 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 79526 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 79537 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 79548 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 79559 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 79570 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 79581 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 79592 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 79603 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 79614 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 79625 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 79636 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 79647 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 79658 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 79669 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 79680 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 79691 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 79702 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 79713 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 79724 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 79735 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 79746 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 79757 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 79768 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 79779 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_p0_s_10_7_btus_1 bridge_p0_p0_s_10_7_btus_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80148 p0_p0_s register btus_1 0x27060 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 79806 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 79817 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 79828 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 79839 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 79850 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 79861 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 79872 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 79883 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 79894 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 79905 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 79916 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 79927 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 79938 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 79949 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 79960 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 79971 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 79982 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 79993 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 80004 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 80015 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 80026 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 80037 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 80048 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 80059 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 80070 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 80081 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 80092 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 80103 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 80114 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 80125 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 80136 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 80147 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_p0_s_10_7_btrl_0 bridge_p0_p0_s_10_7_btrl_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80224 p0_p0_s register btrl_0 0x27080 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 80172 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 80183 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 80198 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 80212 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 80223 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_s_10_7_btrl_1 bridge_p0_p0_s_10_7_btrl_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80300 p0_p0_s register btrl_1 0x27088 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 80248 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 80259 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 80274 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 80288 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 80299 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_s_10_7_btrl_2 bridge_p0_p0_s_10_7_btrl_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80376 p0_p0_s register btrl_2 0x27090 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 80324 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 80335 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 80350 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 80364 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 80375 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_s_10_7_btrl_3 bridge_p0_p0_s_10_7_btrl_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80452 p0_p0_s register btrl_3 0x27098 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 80400 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 80411 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 80426 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 80440 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 80451 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p0_s_10_7_btperr bridge_p0_p0_s_10_7_btperr PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80654 p0_p0_s register btperr 0x270A8 R/W 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 80477 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 80488 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 80499 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 80510 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 80521 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 80532 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 80543 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 80554 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 80565 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 80576 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 80587 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 80598 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 80609 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 80620 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 80631 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 80642 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 80653 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p0_s_10_7_btperrm bridge_p0_p0_s_10_7_btperrm PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80854 p0_p0_s register btperrm 0x270B0 R/W 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 80677 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 80688 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 80699 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 80710 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 80721 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 80732 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 80743 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 80754 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 80765 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 80776 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 80787 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 80798 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 80809 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 80820 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 80831 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 80842 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 80853 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p0_s_10_7_rxe bridge_p0_p0_s_10_7_rxe PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 80962 p0_p0_s register rxe 0x27120 R/W 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 80882 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 80893 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 80904 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 80915 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 80927 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 80938 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 80950 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 80961 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p0_s_10_7_rxem bridge_p0_p0_s_10_7_rxem PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 81034 p0_p0_s register rxem 0x27128 R/W 0x00000050 Pcie_noc_bridge_p0_p0_s_10_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 80983 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 80997 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 81008 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 81022 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 81033 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p0_s_10_7_brs_0 bridge_p0_p0_s_10_7_brs_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 81308 p0_p0_s register brs_0 0x27130 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 81058 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 81069 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 81080 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 81091 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 81102 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 81112 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 81123 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 81134 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 81145 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 81156 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 81167 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 81177 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 81188 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 81199 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 81210 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 81221 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 81232 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 81242 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 81253 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 81264 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 81275 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 81286 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 81297 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 81307 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p0_s_10_7_brs_1 bridge_p0_p0_s_10_7_brs_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 81582 p0_p0_s register brs_1 0x27138 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 81332 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 81343 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 81354 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 81365 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 81376 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 81386 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 81397 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 81408 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 81419 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 81430 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 81441 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 81451 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 81462 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 81473 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 81484 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 81495 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 81506 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 81516 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 81527 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 81538 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 81549 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 81560 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 81571 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 81581 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p0_s_10_7_brus bridge_p0_p0_s_10_7_brus PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 81651 p0_p0_s register brus 0x271B0 R 0x00000000 Pcie_noc_bridge_p0_p0_s_10_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 81607 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 81618 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 81629 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 81640 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 81650 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_p0_s_10_7_brperr0 bridge_p0_p0_s_10_7_brperr0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 81879 p0_p0_s register brperr0 0x271D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 81689 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 81700 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 81711 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 81723 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 81734 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 81745 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 81756 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 81767 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 81778 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 81790 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 81801 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 81812 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 81823 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 81834 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 81845 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 81856 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 81867 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 81878 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_brperr1 bridge_p0_p0_s_10_7_brperr1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 81995 p0_p0_s register brperr1 0x271D8 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 81917 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 81928 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 81939 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 81950 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 81961 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 81972 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 81983 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 81994 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_brperrm0 bridge_p0_p0_s_10_7_brperrm0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82216 p0_p0_s register brperrm0 0x271E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 82022 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 82034 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 82045 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 82057 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 82069 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 82080 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 82091 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 82103 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 82114 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 82126 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 82138 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 82149 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 82160 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 82171 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 82182 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 82193 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 82204 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 82215 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p0_s_10_7_brperrm1 bridge_p0_p0_s_10_7_brperrm1 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82321 p0_p0_s register brperrm1 0x271E8 R 0x0000000000000000 Pcie_noc_bridge_p0_p0_s_10_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 82243 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 82254 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 82265 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 82276 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 82287 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 82298 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 82309 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 82320 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82437 p0_p1_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x28000 R/W 0x0000000058200010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 82361 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 82372 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 82383 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 82395 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 82406 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 82418 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 82429 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 82436 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82529 p0_p1_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x28008 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 82454 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 82465 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 82476 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 82487 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 82499 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 82510 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 82521 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 82528 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82645 p0_p1_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x28020 R/W 0x0000007f80000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 82569 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 82580 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 82591 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 82603 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 82614 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 82626 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 82637 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 82644 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82737 p0_p1_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x28028 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 82662 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 82673 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 82684 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 82695 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 82707 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 82718 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 82729 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 82736 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82778 p0_p1_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x28030 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 82755 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 82766 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 82777 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82894 p0_p1_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x28040 R/W 0x0000007f80001010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 82818 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 82829 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 82840 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 82852 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 82863 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 82875 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 82886 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 82893 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 82986 p0_p1_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x28048 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 82911 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 82922 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 82933 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 82944 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 82956 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 82967 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 82978 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 82985 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83027 p0_p1_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x28050 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 83004 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 83015 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 83026 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83143 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x28060 R/W 0x0000000080000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 83067 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83078 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 83089 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 83101 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 83112 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 83124 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 83135 BASE_ADDRESS_0_33 Base address 39 6 0x002000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83142 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83235 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 0x28068 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 83160 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83171 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 83182 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 83193 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 83205 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 83216 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 83227 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83234 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83351 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x28080 R/W 0x0000008000200010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 83275 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83286 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 83297 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 83309 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 83320 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 83332 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 83343 BASE_ADDRESS_0_33 Base address 39 6 0x200008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83350 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83443 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 0x28088 R/W 0x000000ffffe00000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 83368 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83379 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 83390 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 83401 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 83413 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 83424 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 83435 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83442 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83559 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x280A0 R/W 0x0000008000400010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 83483 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83494 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 83505 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 83517 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 83528 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 83540 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 83551 BASE_ADDRESS_0_33 Base address 39 6 0x200010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83558 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83651 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 0x280A8 R/W 0x000000ffffc00000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 83576 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83587 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 83598 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 83609 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 83621 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 83632 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 83643 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83650 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83767 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x280C0 R/W 0x0000008000800010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 83691 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83702 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 83713 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 83725 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 83736 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 83748 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 83759 BASE_ADDRESS_0_33 Base address 39 6 0x200020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83766 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83859 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 0x280C8 R/W 0x000000ffff800000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 83784 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83795 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 83806 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 83817 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 83829 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 83840 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 83851 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83858 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 83975 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x280E0 R/W 0x0000008001000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 83899 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 83910 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 83921 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 83933 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 83944 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 83956 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 83967 BASE_ADDRESS_0_33 Base address 39 6 0x200040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 83974 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84067 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 0x280E8 R/W 0x000000ffff000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 83992 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84003 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 84014 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 84025 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 84037 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 84048 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 84059 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84066 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84183 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x28100 R/W 0x0000008002000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 84107 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84118 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 84129 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 84141 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 84152 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 84164 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 84175 BASE_ADDRESS_0_33 Base address 39 6 0x200080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84182 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84275 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 0x28108 R/W 0x000000fffe000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 84200 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84211 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 84222 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 84233 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 84245 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 84256 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 84267 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84274 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84391 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x28120 R/W 0x0000008004000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 84315 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84326 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 84337 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 84349 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 84360 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 84372 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 84383 BASE_ADDRESS_0_33 Base address 39 6 0x200100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84390 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84483 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 0x28128 R/W 0x000000fffc000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 84408 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84419 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 84430 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 84441 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 84453 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 84464 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 84475 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84482 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84599 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x28140 R/W 0x0000008008000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 84523 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84534 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 84545 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 84557 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 84568 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 84580 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 84591 BASE_ADDRESS_0_33 Base address 39 6 0x200200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84598 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84691 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 0x28148 R/W 0x000000fff8000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 84616 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84627 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 84638 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 84649 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 84661 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 84672 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 84683 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84690 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84807 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x28160 R/W 0x0000008010000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 84731 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84742 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 84753 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 84765 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 84776 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 84788 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 84799 BASE_ADDRESS_0_33 Base address 39 6 0x200400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84806 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 84899 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 0x28168 R/W 0x000000fff0000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 84824 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84835 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 84846 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 84857 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 84869 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 84880 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 84891 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 84898 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85015 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0x28180 R/W 0x0000008020000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 84939 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 84950 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 84961 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 84973 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 84984 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 84996 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 85007 BASE_ADDRESS_0_33 Base address 39 6 0x200800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85014 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85107 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 0x28188 R/W 0x000000ffe0000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 85032 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85043 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 85054 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 85065 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 85077 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 85088 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 85099 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85106 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85223 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0x281A0 R/W 0x0000008040000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 85147 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85158 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 85169 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 85181 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 85192 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 85204 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 85215 BASE_ADDRESS_0_33 Base address 39 6 0x201000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85222 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85315 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 0x281A8 R/W 0x000000ffc0000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 85240 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85251 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 85262 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 85273 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 85285 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 85296 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 85307 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85314 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85431 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0x281C0 R/W 0x0000008080000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 85355 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85366 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 85377 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 85389 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 85400 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 85412 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 85423 BASE_ADDRESS_0_33 Base address 39 6 0x202000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85430 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85523 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 0x281C8 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 85448 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85459 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 85470 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 85481 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 85493 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 85504 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 85515 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85522 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85639 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0x281E0 R/W 0x0000008100000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 85563 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85574 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 85585 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 85597 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 85608 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 85620 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 85631 BASE_ADDRESS_0_33 Base address 39 6 0x204000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85638 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85731 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 0x281E8 R/W 0x000000ff00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 85656 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85667 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 85678 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 85689 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 85701 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 85712 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 85723 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85730 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85847 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0x28200 R/W 0x0000008200000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 85771 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85782 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 85793 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 85805 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 85816 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 85828 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 85839 BASE_ADDRESS_0_33 Base address 39 6 0x208000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85846 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 85939 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 0x28208 R/W 0x000000fe00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 85864 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85875 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 85886 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 85897 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 85909 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 85920 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 85931 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 85938 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86055 p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0x28220 R/W 0x0000008400000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 85979 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 85990 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 86001 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 86013 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 86024 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 86036 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 86047 BASE_ADDRESS_0_33 Base address 39 6 0x210000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86054 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86147 p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 0x28228 R/W 0x000000fc00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 86072 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86083 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 86094 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 86105 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 86117 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 86128 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 86139 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86146 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86263 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0x28240 R/W 0x0000000002000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 86187 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86198 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 86209 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 86221 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 86232 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 86244 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 86255 BASE_ADDRESS_0_33 Base address 39 6 0x000080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86262 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86355 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 0x28248 R/W 0x000000ffffff0000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 86280 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86291 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 86302 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 86313 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 86325 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 86336 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 86347 MASK_0_33 Mask 39 6 0x3fffffc00 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86354 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86471 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0x28260 R/W 0x0000000020007000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 86395 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86406 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 86417 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 86429 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 86440 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 86452 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 86463 BASE_ADDRESS_0_33 Base address 39 6 0x0008001c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86470 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86563 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 0x28268 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 86488 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86499 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 86510 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 86521 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 86533 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 86544 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 86555 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86562 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86679 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0x28280 R/W 0x0000000030001000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 86603 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86614 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 86625 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 86637 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 86648 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 86660 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 86671 BASE_ADDRESS_0_33 Base address 39 6 0x000c00040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86678 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86771 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 0x28288 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 86696 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86707 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 86718 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 86729 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 86741 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 86752 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 86763 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86770 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86887 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0x282A0 R/W 0x0000000030003000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 86811 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86822 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 86833 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 86845 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 86856 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 86868 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 86879 BASE_ADDRESS_0_33 Base address 39 6 0x000c000c0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86886 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 86979 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 0x282A8 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 86904 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 86915 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 86926 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 86937 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 86949 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 86960 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 86971 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 86978 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87095 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0x282C0 R/W 0x0000000030008000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 87019 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87030 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 87041 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 87053 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 87064 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 87076 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 87087 BASE_ADDRESS_0_33 Base address 39 6 0x000c00200 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87094 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87187 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 0x282C8 R/W 0x000000ffffffe000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 87112 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87123 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 87134 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 87145 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 87157 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 87168 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 87179 MASK_0_33 Mask 39 6 0x3ffffff80 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87186 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87303 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0x282E0 R/W 0x0000000100000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 87227 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87238 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 87249 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 87261 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SET ns_noc_io_pcie_soc_ip.csr 87272 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 87284 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 87295 BASE_ADDRESS_0_33 Base address 39 6 0x004000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87302 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87395 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 0x282E8 R/W 0x000000ff00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SET ns_noc_io_pcie_soc_ip.csr 87320 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87331 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SET ns_noc_io_pcie_soc_ip.csr 87342 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 87353 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SET ns_noc_io_pcie_soc_ip.csr 87365 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 87376 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 87387 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87394 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87511 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0x28300 R/W 0x000000c000200010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 87435 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87446 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 87457 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 87469 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SET ns_noc_io_pcie_soc_ip.csr 87480 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 87492 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 87503 BASE_ADDRESS_0_33 Base address 39 6 0x300008000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87510 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87603 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 0x28308 R/W 0x000000ffffe00000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SET ns_noc_io_pcie_soc_ip.csr 87528 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87539 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SET ns_noc_io_pcie_soc_ip.csr 87550 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 87561 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SET ns_noc_io_pcie_soc_ip.csr 87573 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 87584 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 87595 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87602 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87719 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0x28320 R/W 0x000000c000400010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 87643 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87654 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 87665 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 87677 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SET ns_noc_io_pcie_soc_ip.csr 87688 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 87700 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 87711 BASE_ADDRESS_0_33 Base address 39 6 0x300010000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87718 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87811 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 0x28328 R/W 0x000000ffffc00000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SET ns_noc_io_pcie_soc_ip.csr 87736 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87747 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SET ns_noc_io_pcie_soc_ip.csr 87758 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 87769 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SET ns_noc_io_pcie_soc_ip.csr 87781 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 87792 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 87803 MASK_0_33 Mask 39 6 0x3ffff0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87810 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 87927 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0x28340 R/W 0x000000c000800010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 87851 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87862 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 87873 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 87885 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SET ns_noc_io_pcie_soc_ip.csr 87896 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 87908 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 87919 BASE_ADDRESS_0_33 Base address 39 6 0x300020000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 87926 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88019 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 0x28348 R/W 0x000000ffff800000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SET ns_noc_io_pcie_soc_ip.csr 87944 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SET ns_noc_io_pcie_soc_ip.csr 87955 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SET ns_noc_io_pcie_soc_ip.csr 87966 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 87977 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SET ns_noc_io_pcie_soc_ip.csr 87989 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 88000 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 88011 MASK_0_33 Mask 39 6 0x3fffe0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88018 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88135 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0x28360 R/W 0x000000c001000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 88059 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88070 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 88081 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 88093 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SET ns_noc_io_pcie_soc_ip.csr 88104 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 88116 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 88127 BASE_ADDRESS_0_33 Base address 39 6 0x300040000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88134 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88227 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 0x28368 R/W 0x000000ffff000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SET ns_noc_io_pcie_soc_ip.csr 88152 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88163 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SET ns_noc_io_pcie_soc_ip.csr 88174 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 88185 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SET ns_noc_io_pcie_soc_ip.csr 88197 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 88208 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 88219 MASK_0_33 Mask 39 6 0x3fffc0000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88226 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88343 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0x28380 R/W 0x000000c002000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 88267 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88278 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 88289 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 88301 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SET ns_noc_io_pcie_soc_ip.csr 88312 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 88324 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 88335 BASE_ADDRESS_0_33 Base address 39 6 0x300080000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88342 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88435 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 0x28388 R/W 0x000000fffe000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SET ns_noc_io_pcie_soc_ip.csr 88360 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88371 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SET ns_noc_io_pcie_soc_ip.csr 88382 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 88393 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SET ns_noc_io_pcie_soc_ip.csr 88405 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 88416 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 88427 MASK_0_33 Mask 39 6 0x3fff80000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88434 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88551 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0x283A0 R/W 0x000000c004000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 88475 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88486 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 88497 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 88509 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SET ns_noc_io_pcie_soc_ip.csr 88520 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 88532 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 88543 BASE_ADDRESS_0_33 Base address 39 6 0x300100000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88550 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88643 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 0x283A8 R/W 0x000000fffc000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SET ns_noc_io_pcie_soc_ip.csr 88568 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88579 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SET ns_noc_io_pcie_soc_ip.csr 88590 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 88601 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SET ns_noc_io_pcie_soc_ip.csr 88613 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 88624 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 88635 MASK_0_33 Mask 39 6 0x3fff00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88642 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88759 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0x283C0 R/W 0x000000c008000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 88683 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88694 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 88705 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 88717 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SET ns_noc_io_pcie_soc_ip.csr 88728 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 88740 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 88751 BASE_ADDRESS_0_33 Base address 39 6 0x300200000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88758 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88851 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 0x283C8 R/W 0x000000fff8000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SET ns_noc_io_pcie_soc_ip.csr 88776 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88787 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SET ns_noc_io_pcie_soc_ip.csr 88798 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 88809 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SET ns_noc_io_pcie_soc_ip.csr 88821 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 88832 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 88843 MASK_0_33 Mask 39 6 0x3ffe00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88850 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 88967 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x283E0 R/W 0x000000c010000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 88891 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88902 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 88913 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 88925 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SET ns_noc_io_pcie_soc_ip.csr 88936 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 88948 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 88959 BASE_ADDRESS_0_33 Base address 39 6 0x300400000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 88966 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89059 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 0x283E8 R/W 0x000000fff0000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SET ns_noc_io_pcie_soc_ip.csr 88984 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SET ns_noc_io_pcie_soc_ip.csr 88995 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SET ns_noc_io_pcie_soc_ip.csr 89006 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 89017 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SET ns_noc_io_pcie_soc_ip.csr 89029 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 89040 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 89051 MASK_0_33 Mask 39 6 0x3ffc00000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89058 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89175 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x28400 R/W 0x000000c020000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 89099 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89110 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 89121 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 89133 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SET ns_noc_io_pcie_soc_ip.csr 89144 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 89156 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 89167 BASE_ADDRESS_0_33 Base address 39 6 0x300800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89174 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89267 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 0x28408 R/W 0x000000ffe0000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SET ns_noc_io_pcie_soc_ip.csr 89192 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89203 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SET ns_noc_io_pcie_soc_ip.csr 89214 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 89225 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SET ns_noc_io_pcie_soc_ip.csr 89237 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 89248 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 89259 MASK_0_33 Mask 39 6 0x3ff800000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89266 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89383 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x28420 R/W 0x000000c040000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 89307 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89318 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 89329 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 89341 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SET ns_noc_io_pcie_soc_ip.csr 89352 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 89364 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 89375 BASE_ADDRESS_0_33 Base address 39 6 0x301000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89382 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89475 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 0x28428 R/W 0x000000ffc0000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SET ns_noc_io_pcie_soc_ip.csr 89400 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89411 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SET ns_noc_io_pcie_soc_ip.csr 89422 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 89433 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SET ns_noc_io_pcie_soc_ip.csr 89445 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 89456 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 89467 MASK_0_33 Mask 39 6 0x3ff000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89474 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89591 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x28440 R/W 0x000000c080000010 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 89515 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89526 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 89537 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 89549 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SET ns_noc_io_pcie_soc_ip.csr 89560 DI 1'b1: Address range disabled 4 4 0x1 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 89572 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 89583 BASE_ADDRESS_0_33 Base address 39 6 0x302000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89590 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89683 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 0x28448 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SET ns_noc_io_pcie_soc_ip.csr 89608 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89619 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SET ns_noc_io_pcie_soc_ip.csr 89630 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 89641 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SET ns_noc_io_pcie_soc_ip.csr 89653 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 89664 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 89675 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89682 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89799 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x28460 R/W 0x000000c100000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 89723 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89734 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 89745 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 89757 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SET ns_noc_io_pcie_soc_ip.csr 89768 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 89780 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 89791 BASE_ADDRESS_0_33 Base address 39 6 0x304000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89798 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 89891 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 0x28468 R/W 0x000000ff00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SET ns_noc_io_pcie_soc_ip.csr 89816 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89827 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SET ns_noc_io_pcie_soc_ip.csr 89838 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 89849 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SET ns_noc_io_pcie_soc_ip.csr 89861 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 89872 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 89883 MASK_0_33 Mask 39 6 0x3fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 89890 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90007 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x28480 R/W 0x000000c200000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 89931 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 89942 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 89953 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 89965 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SET ns_noc_io_pcie_soc_ip.csr 89976 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 89988 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 89999 BASE_ADDRESS_0_33 Base address 39 6 0x308000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 90006 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90099 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 0x28488 R/W 0x000000fe00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SET ns_noc_io_pcie_soc_ip.csr 90024 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SET ns_noc_io_pcie_soc_ip.csr 90035 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SET ns_noc_io_pcie_soc_ip.csr 90046 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 90057 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SET ns_noc_io_pcie_soc_ip.csr 90069 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 90080 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 90091 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 90098 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90215 p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x284A0 R/W 0x000000c400000000 Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 90139 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 90150 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 90161 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 90173 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SET ns_noc_io_pcie_soc_ip.csr 90184 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 90196 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 90207 BASE_ADDRESS_0_33 Base address 39 6 0x310000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 90214 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90307 p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 0x284A8 R/W 0x000000fc00000000 Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SET ns_noc_io_pcie_soc_ip.csr 90232 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SET ns_noc_io_pcie_soc_ip.csr 90243 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SET ns_noc_io_pcie_soc_ip.csr 90254 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 90265 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SET ns_noc_io_pcie_soc_ip.csr 90277 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 90288 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 90299 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 90306 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_p_0 bridge_p0_p1_m_4_6_p_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90372 p0_p1_m register p_0 0x2B000 R/W 0x00000003 Pcie_noc_bridge_p0_p1_m_4_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 90335 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 90347 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 90359 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 90371 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_p_1 bridge_p0_p1_m_4_6_p_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90438 p0_p1_m register p_1 0x2B008 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 90401 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 90413 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 90425 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 90437 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_p_2 bridge_p0_p1_m_4_6_p_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90504 p0_p1_m register p_2 0x2B010 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 90467 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 90479 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 90491 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 90503 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_p_3 bridge_p0_p1_m_4_6_p_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90570 p0_p1_m register p_3 0x2B018 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 90533 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 90545 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 90557 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 90569 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_txe bridge_p0_p1_m_4_6_txe PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90716 p0_p1_m register txe 0x2B040 R/W 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 90597 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 90609 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 90624 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 90637 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 90651 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 90665 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 90679 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 90693 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 90704 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 90715 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_txem bridge_p0_p1_m_4_6_txem PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 90795 p0_p1_m register txem 0x2B048 R/W 0x00000008 Pcie_noc_bridge_p0_p1_m_4_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 90739 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 90750 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 90761 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 90772 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 90783 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 90794 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p1_m_4_6_btus_0 bridge_p0_p1_m_4_6_btus_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 91163 p0_p1_m register btus_0 0x2B058 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 90821 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 90832 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 90843 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 90854 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 90865 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 90876 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 90887 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 90898 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 90909 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 90920 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 90931 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 90942 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 90953 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 90964 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 90975 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 90986 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 90997 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 91008 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 91019 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 91030 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 91041 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 91052 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 91063 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 91074 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 91085 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 91096 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 91107 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 91118 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 91129 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 91140 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 91151 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 91162 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_p1_m_4_6_btus_1 bridge_p0_p1_m_4_6_btus_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 91531 p0_p1_m register btus_1 0x2B060 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 91189 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 91200 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 91211 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 91222 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 91233 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 91244 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 91255 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 91266 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 91277 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 91288 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 91299 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 91310 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 91321 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 91332 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 91343 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 91354 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 91365 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 91376 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 91387 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 91398 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 91409 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 91420 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 91431 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 91442 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 91453 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 91464 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 91475 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 91486 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 91497 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 91508 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 91519 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 91530 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_p1_m_4_6_btrl_0 bridge_p0_p1_m_4_6_btrl_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 91607 p0_p1_m register btrl_0 0x2B080 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 91555 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 91566 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 91581 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 91595 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 91606 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_m_4_6_btrl_1 bridge_p0_p1_m_4_6_btrl_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 91683 p0_p1_m register btrl_1 0x2B088 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 91631 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 91642 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 91657 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 91671 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 91682 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_m_4_6_btrl_2 bridge_p0_p1_m_4_6_btrl_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 91759 p0_p1_m register btrl_2 0x2B090 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 91707 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 91718 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 91733 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 91747 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 91758 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_m_4_6_btrl_3 bridge_p0_p1_m_4_6_btrl_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 91835 p0_p1_m register btrl_3 0x2B098 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 91783 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 91794 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 91809 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 91823 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 91834 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_m_4_6_btperr bridge_p0_p1_m_4_6_btperr PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 92037 p0_p1_m register btperr 0x2B0A8 R/W 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 91860 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 91871 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 91882 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 91893 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 91904 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 91915 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 91926 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 91937 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 91948 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 91959 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 91970 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 91981 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 91992 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 92003 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 92014 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 92025 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 92036 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p1_m_4_6_btperrm bridge_p0_p1_m_4_6_btperrm PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 92237 p0_p1_m register btperrm 0x2B0B0 R/W 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 92060 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 92071 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 92082 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 92093 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 92104 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 92115 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 92126 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 92137 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 92148 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 92159 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 92170 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 92181 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 92192 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 92203 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 92214 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 92225 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 92236 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p1_m_4_6_rxe bridge_p0_p1_m_4_6_rxe PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 92345 p0_p1_m register rxe 0x2B120 R/W 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 92265 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 92276 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 92287 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 92298 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 92310 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 92321 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 92333 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 92344 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p1_m_4_6_rxem bridge_p0_p1_m_4_6_rxem PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 92417 p0_p1_m register rxem 0x2B128 R/W 0x00000050 Pcie_noc_bridge_p0_p1_m_4_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 92366 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 92380 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 92391 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 92405 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 92416 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p1_m_4_6_brs_0 bridge_p0_p1_m_4_6_brs_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 92691 p0_p1_m register brs_0 0x2B130 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 92441 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 92452 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 92463 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 92474 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 92485 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 92495 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 92506 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 92517 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 92528 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 92539 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 92550 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 92560 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 92571 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 92582 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 92593 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 92604 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 92615 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 92625 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 92636 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 92647 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 92658 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 92669 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 92680 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 92690 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p1_m_4_6_brs_1 bridge_p0_p1_m_4_6_brs_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 92965 p0_p1_m register brs_1 0x2B138 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 92715 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 92726 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 92737 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 92748 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 92759 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 92769 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 92780 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 92791 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 92802 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 92813 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 92824 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 92834 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 92845 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 92856 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 92867 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 92878 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 92889 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 92899 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 92910 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 92921 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 92932 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 92943 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 92954 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 92964 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p1_m_4_6_brus bridge_p0_p1_m_4_6_brus PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93034 p0_p1_m register brus 0x2B1B0 R 0x00000000 Pcie_noc_bridge_p0_p1_m_4_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 92990 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 93001 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 93012 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 93023 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 93033 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_p1_m_4_6_brperr0 bridge_p0_p1_m_4_6_brperr0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93262 p0_p1_m register brperr0 0x2B1D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 93072 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 93083 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 93094 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 93106 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 93117 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 93128 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 93139 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 93150 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 93161 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 93173 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 93184 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 93195 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 93206 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 93217 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 93228 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 93239 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 93250 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 93261 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_brperr1 bridge_p0_p1_m_4_6_brperr1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93378 p0_p1_m register brperr1 0x2B1D8 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 93300 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 93311 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 93322 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 93333 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 93344 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 93355 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 93366 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 93377 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_brperrm0 bridge_p0_p1_m_4_6_brperrm0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93599 p0_p1_m register brperrm0 0x2B1E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 93405 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 93417 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 93428 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 93440 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 93452 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 93463 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 93474 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 93486 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 93497 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 93509 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 93521 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 93532 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 93543 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 93554 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 93565 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 93576 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 93587 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 93598 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_brperrm1 bridge_p0_p1_m_4_6_brperrm1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93704 p0_p1_m register brperrm1 0x2B1E8 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 93626 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 93637 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 93648 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 93659 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 93670 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 93681 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 93692 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 93703 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_am_tocfg bridge_p0_p1_m_4_6_am_tocfg PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93778 p0_p1_m register am_tocfg 0x2BC00 R/W 0x000000000000001f Pcie_noc_bridge_p0_p1_m_4_6_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 93741 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 93752 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 93766 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 93777 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_osslv bridge_p0_p1_m_4_6_am_osslv PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93813 p0_p1_m register am_osslv 0x2BC08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 93801 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 93812 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_cgc bridge_p0_p1_m_4_6_am_cgc PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93850 p0_p1_m register am_cgc 0x2BC10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_p1_m_4_6_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 93838 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 93849 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_cgo bridge_p0_p1_m_4_6_am_cgo PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93885 p0_p1_m register am_cgo 0x2BC18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 93873 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 93884 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_cfg bridge_p0_p1_m_4_6_am_cfg PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 93922 p0_p1_m register am_cfg 0x2BC20 R/W 0x0000000000000001 Pcie_noc_bridge_p0_p1_m_4_6_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 93910 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 93921 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_sts bridge_p0_p1_m_4_6_am_sts PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 94050 p0_p1_m register am_sts 0x2BD00 R 0x000000000000000c Pcie_noc_bridge_p0_p1_m_4_6_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 93955 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 93969 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 93981 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 93993 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 94004 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 94015 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 94027 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 94039 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 94049 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_bridge_id bridge_p0_p1_m_4_6_am_bridge_id PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 94080 p0_p1_m register am_bridge_id 0x2BD08 R 0x0000000000000004 Pcie_noc_bridge_p0_p1_m_4_6_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 94069 ID Unique bridge ID 15 0 0x0004 R UNSD_63_16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 94079 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_err bridge_p0_p1_m_4_6_am_err PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 94576 p0_p1_m register am_err 0x2BE00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 94102 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 94114 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 94126 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 94138 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 94150 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 94162 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 94175 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 94188 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 94199 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 94210 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 94221 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 94232 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 94243 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 94254 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 94265 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 94276 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 94287 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 94299 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 94310 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 94321 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 94332 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 94343 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 94355 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 94367 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 94378 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 94390 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 94401 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 94412 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 94423 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 94434 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 94445 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 94456 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 94468 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 94480 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 94492 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 94504 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 94516 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 94528 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 94540 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 94552 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 94564 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 94575 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_am_toslvid bridge_p0_p1_m_4_6_am_toslvid PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 94621 p0_p1_m register am_toslvid 0x2BE08 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 94599 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 94610 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 94620 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_era bridge_p0_p1_m_4_6_am_era PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 94643 p0_p1_m register am_era 0x2BE10 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 94642 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_ewa bridge_p0_p1_m_4_6_am_ewa PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 94665 p0_p1_m register am_ewa 0x2BE18 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 94664 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_intm bridge_p0_p1_m_4_6_am_intm PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95149 p0_p1_m register am_intm 0x2BE40 R/W 0x00007e07004f004f Pcie_noc_bridge_p0_p1_m_4_6_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 94687 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 94698 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 94709 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 94720 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 94731 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 94742 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 94753 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 94764 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 94775 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 94786 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 94797 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 94808 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 94819 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 94830 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 94841 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 94852 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 94863 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 94874 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 94885 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 94896 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 94907 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 94918 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 94929 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 94940 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 94951 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 94963 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 94974 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 94985 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 94996 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 95007 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 95018 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 95029 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 95041 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 95053 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 95065 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 95077 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 95089 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 95101 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 95113 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 95125 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 95137 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 95148 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_m_4_6_am_caddr bridge_p0_p1_m_4_6_am_caddr PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95171 p0_p1_m register am_caddr 0x2BF00 R/W 0xffffffffffffffff Pcie_noc_bridge_p0_p1_m_4_6_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 95170 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_p0_p1_m_4_6_am_caddrmsk bridge_p0_p1_m_4_6_am_caddrmsk PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95194 p0_p1_m register am_caddrmsk 0x2BF08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 95193 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_p0_p1_m_4_6_am_ccmd0 bridge_p0_p1_m_4_6_am_ccmd0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95384 p0_p1_m register am_ccmd0 0x2BF10 R/W 0x0000000003fff33f Pcie_noc_bridge_p0_p1_m_4_6_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 95216 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 95227 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 95238 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 95249 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 95260 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 95271 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 95282 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 95293 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 95304 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 95315 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 95326 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 95337 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 95349 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 95360 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 95372 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 95383 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk0 bridge_p0_p1_m_4_6_am_ccmdmsk0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95528 p0_p1_m register am_ccmdmsk0 0x2BF18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 95406 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 95417 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 95428 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 95439 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 95450 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 95461 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 95472 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 95483 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 95494 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 95505 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 95516 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 95527 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_cntr0 bridge_p0_p1_m_4_6_am_cntr0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95563 p0_p1_m register am_cntr0 0x2BF20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 95551 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 95562 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_latnum0 bridge_p0_p1_m_4_6_am_latnum0 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95602 p0_p1_m register am_latnum0 0x2BF28 R/W 0x0000000000000007 Pcie_noc_bridge_p0_p1_m_4_6_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 95590 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 95601 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_ccmd1 bridge_p0_p1_m_4_6_am_ccmd1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95792 p0_p1_m register am_ccmd1 0x2BF30 R/W 0x0000000003fff33f Pcie_noc_bridge_p0_p1_m_4_6_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 95624 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 95635 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 95646 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 95657 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 95668 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 95679 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 95690 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 95701 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 95712 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 95723 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 95734 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 95745 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 95757 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 95768 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 95780 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 95791 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk1 bridge_p0_p1_m_4_6_am_ccmdmsk1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95936 p0_p1_m register am_ccmdmsk1 0x2BF38 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 95814 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 95825 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 95836 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 95847 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 95858 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 95869 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 95880 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 95891 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 95902 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 95913 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 95924 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 95935 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_cntr1 bridge_p0_p1_m_4_6_am_cntr1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 95971 p0_p1_m register am_cntr1 0x2BF40 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 95959 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 95970 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_latnum1 bridge_p0_p1_m_4_6_am_latnum1 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96010 p0_p1_m register am_latnum1 0x2BF48 R/W 0x0000000000000007 Pcie_noc_bridge_p0_p1_m_4_6_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 95998 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 96009 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_arovrd bridge_p0_p1_m_4_6_am_arovrd PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96123 p0_p1_m register am_arovrd 0x2BF60 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 96028 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 96041 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 96052 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 96063 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 96076 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 96087 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 96098 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 96111 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 96122 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p1_m_4_6_am_awovrd bridge_p0_p1_m_4_6_am_awovrd PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96236 p0_p1_m register am_awovrd 0x2BF68 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_m_4_6_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 96141 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 96154 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 96165 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 96176 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 96189 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 96200 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 96211 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 96224 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 96235 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgc bridge_p0_p1_reg_s_11_6_as_cgc PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96273 p0_p1_reg_s register as_cgc 0x2DC10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 96261 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 96272 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgo bridge_p0_p1_reg_s_11_6_as_cgo PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96308 p0_p1_reg_s register as_cgo 0x2DC18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 96296 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 96307 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_sts bridge_p0_p1_reg_s_11_6_as_sts PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96382 p0_p1_reg_s register as_sts 0x2DD00 R 0x000000000000000c Pcie_noc_bridge_p0_p1_reg_s_11_6_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 96331 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 96347 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 96359 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 96371 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 96381 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_id bridge_p0_p1_reg_s_11_6_as_bridge_id PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96412 p0_p1_reg_s register as_bridge_id 0x2DD08 R 0x000000000000000b Pcie_noc_bridge_p0_p1_reg_s_11_6_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 96401 ID Unique bridge ID 15 0 0x000b R UNSD_63_16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 96411 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_err bridge_p0_p1_reg_s_11_6_as_err PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 96765 p0_p1_reg_s register as_err 0x2DE00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 96433 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 96445 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 96458 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 96472 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 96484 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 96495 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 96507 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 96519 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 96532 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 96544 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 96555 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 96567 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 96578 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 96589 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 96600 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 96611 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 96622 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 96633 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 96645 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 96657 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 96669 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 96681 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 96693 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 96705 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 96717 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 96729 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 96741 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 96753 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 96764 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_intm bridge_p0_p1_reg_s_11_6_as_intm PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97105 p0_p1_reg_s register as_intm 0x2DE40 R/W 0x0000007d000b0013 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 96786 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 96797 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 96808 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 96819 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 96830 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 96841 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 96852 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 96863 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 96874 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 96885 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 96896 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 96907 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 96918 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 96929 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 96940 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 96951 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 96962 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 96973 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 96985 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 96997 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 97009 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 97021 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 97033 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 97045 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 97057 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 97069 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 97081 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 97093 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 97104 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmd bridge_p0_p1_reg_s_11_6_as_ccmd PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97180 p0_p1_reg_s register as_ccmd 0x2DF00 R/W 0x0000000003000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 97123 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 97134 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 97145 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 97156 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 97168 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 97179 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmsk bridge_p0_p1_reg_s_11_6_as_ccmdmsk PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97232 p0_p1_reg_s register as_ccmdmsk 0x2DF08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 97198 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 97209 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 97220 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 97231 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_cntr bridge_p0_p1_reg_s_11_6_as_cntr PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97262 p0_p1_reg_s register as_cntr 0x2DF10 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 97251 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 97261 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrd bridge_p0_p1_reg_s_11_6_as_arovrd PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97375 p0_p1_reg_s register as_arovrd 0x2DF18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 97280 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 97293 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 97304 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 97315 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 97328 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 97339 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 97350 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 97363 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 97374 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrd bridge_p0_p1_reg_s_11_6_as_awovrd PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97488 p0_p1_reg_s register as_awovrd 0x2DF20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 97393 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 97406 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 97417 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 97428 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 97441 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 97452 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 97463 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 97476 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 97487 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_p_0 bridge_p0_p1_reg_s_11_6_p_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97553 p0_p1_reg_s register p_0 0x2F000 R/W 0x00000003 Pcie_noc_bridge_p0_p1_reg_s_11_6_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 97516 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 97528 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 97540 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 97552 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_p_1 bridge_p0_p1_reg_s_11_6_p_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97619 p0_p1_reg_s register p_1 0x2F008 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 97582 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 97594 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 97606 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 97618 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_p_2 bridge_p0_p1_reg_s_11_6_p_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97685 p0_p1_reg_s register p_2 0x2F010 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 97648 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 97660 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 97672 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 97684 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_p_3 bridge_p0_p1_reg_s_11_6_p_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97751 p0_p1_reg_s register p_3 0x2F018 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 97714 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 97726 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 97738 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 97750 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_txe bridge_p0_p1_reg_s_11_6_txe PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97897 p0_p1_reg_s register txe 0x2F040 R/W 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 97778 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 97790 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 97805 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 97818 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 97832 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 97846 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 97860 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 97874 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 97885 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 97896 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_txem bridge_p0_p1_reg_s_11_6_txem PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 97976 p0_p1_reg_s register txem 0x2F048 R/W 0x00000008 Pcie_noc_bridge_p0_p1_reg_s_11_6_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 97920 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 97931 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 97942 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 97953 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 97964 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 97975 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btus_0 bridge_p0_p1_reg_s_11_6_btus_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 98344 p0_p1_reg_s register btus_0 0x2F058 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 98002 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 98013 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 98024 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 98035 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 98046 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 98057 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 98068 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 98079 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 98090 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 98101 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 98112 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 98123 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 98134 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 98145 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 98156 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 98167 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 98178 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 98189 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 98200 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 98211 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 98222 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 98233 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 98244 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 98255 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 98266 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 98277 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 98288 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 98299 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 98310 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 98321 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 98332 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 98343 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btus_1 bridge_p0_p1_reg_s_11_6_btus_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 98712 p0_p1_reg_s register btus_1 0x2F060 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 98370 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 98381 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 98392 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 98403 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 98414 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 98425 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 98436 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 98447 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 98458 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 98469 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 98480 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 98491 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 98502 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 98513 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 98524 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 98535 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 98546 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 98557 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 98568 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 98579 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 98590 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 98601 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 98612 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 98623 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 98634 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 98645 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 98656 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 98667 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 98678 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 98689 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 98700 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 98711 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_0 bridge_p0_p1_reg_s_11_6_btrl_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 98788 p0_p1_reg_s register btrl_0 0x2F080 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 98736 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 98747 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 98762 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 98776 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 98787 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_1 bridge_p0_p1_reg_s_11_6_btrl_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 98864 p0_p1_reg_s register btrl_1 0x2F088 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 98812 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 98823 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 98838 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 98852 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 98863 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_2 bridge_p0_p1_reg_s_11_6_btrl_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 98940 p0_p1_reg_s register btrl_2 0x2F090 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 98888 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 98899 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 98914 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 98928 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 98939 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_3 bridge_p0_p1_reg_s_11_6_btrl_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 99016 p0_p1_reg_s register btrl_3 0x2F098 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 98964 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 98975 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 98990 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 99004 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 99015 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btperr bridge_p0_p1_reg_s_11_6_btperr PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 99218 p0_p1_reg_s register btperr 0x2F0A8 R/W 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 99041 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 99052 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 99063 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 99074 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 99085 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 99096 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 99107 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 99118 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 99129 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 99140 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 99151 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 99162 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 99173 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 99184 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 99195 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 99206 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 99217 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_btperrm bridge_p0_p1_reg_s_11_6_btperrm PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 99418 p0_p1_reg_s register btperrm 0x2F0B0 R/W 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 99241 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 99252 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 99263 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 99274 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 99285 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 99296 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 99307 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 99318 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 99329 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 99340 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 99351 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 99362 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 99373 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 99384 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 99395 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 99406 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 99417 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_rxe bridge_p0_p1_reg_s_11_6_rxe PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 99526 p0_p1_reg_s register rxe 0x2F120 R/W 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 99446 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 99457 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 99468 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 99479 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 99491 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 99502 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 99514 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 99525 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_rxem bridge_p0_p1_reg_s_11_6_rxem PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 99598 p0_p1_reg_s register rxem 0x2F128 R/W 0x00000050 Pcie_noc_bridge_p0_p1_reg_s_11_6_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 99547 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 99561 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 99572 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 99586 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 99597 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brs_0 bridge_p0_p1_reg_s_11_6_brs_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 99872 p0_p1_reg_s register brs_0 0x2F130 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 99622 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 99633 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 99644 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 99655 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 99666 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 99676 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 99687 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 99698 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 99709 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 99720 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 99731 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 99741 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 99752 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 99763 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 99774 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 99785 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 99796 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 99806 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 99817 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 99828 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 99839 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 99850 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 99861 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 99871 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brs_1 bridge_p0_p1_reg_s_11_6_brs_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100146 p0_p1_reg_s register brs_1 0x2F138 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 99896 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 99907 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 99918 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 99929 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 99940 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 99950 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 99961 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 99972 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 99983 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 99994 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 100005 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 100015 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 100026 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 100037 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 100048 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 100059 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 100070 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 100080 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 100091 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 100102 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 100113 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 100124 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 100135 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 100145 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brus bridge_p0_p1_reg_s_11_6_brus PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100215 p0_p1_reg_s register brus 0x2F1B0 R 0x00000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 100171 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 100182 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 100193 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 100204 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 100214 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brperr0 bridge_p0_p1_reg_s_11_6_brperr0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100443 p0_p1_reg_s register brperr0 0x2F1D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 100253 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 100264 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 100275 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 100287 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 100298 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 100309 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 100320 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 100331 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 100342 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 100354 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 100365 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 100376 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 100387 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 100398 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 100409 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 100420 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 100431 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 100442 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brperr1 bridge_p0_p1_reg_s_11_6_brperr1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100559 p0_p1_reg_s register brperr1 0x2F1D8 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 100481 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 100492 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 100503 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 100514 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 100525 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 100536 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 100547 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 100558 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm0 bridge_p0_p1_reg_s_11_6_brperrm0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100780 p0_p1_reg_s register brperrm0 0x2F1E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 100586 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 100598 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 100609 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 100621 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 100633 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 100644 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 100655 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 100667 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 100678 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 100690 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 100702 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 100713 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 100724 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 100735 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 100746 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 100757 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 100768 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 100779 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm1 bridge_p0_p1_reg_s_11_6_brperrm1 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100885 p0_p1_reg_s register brperrm1 0x2F1E8 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_reg_s_11_6_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 100807 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 100818 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 100829 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 100840 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 100851 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 100862 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 100873 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 100884 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_as_cgc bridge_p0_p1_s_12_10_as_cgc PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100922 p0_p1_s register as_cgc 0x31C10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_p1_s_12_10_as_cgc Programmable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 100910 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 100921 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_cgo bridge_p0_p1_s_12_10_as_cgo PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 100957 p0_p1_s register as_cgo 0x31C18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_as_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 100945 FPO 1'b1: Clock gating override enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 100956 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_sts bridge_p0_p1_s_12_10_as_sts PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101031 p0_p1_s register as_sts 0x31D00 R 0x000000000000000c Pcie_noc_bridge_p0_p1_s_12_10_as_sts Slave bridge status bits. false false false false WOF PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 100980 WOF 1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received. 1'b0: Slave device can expect more write commands from NoC 0 0 0x0 R ROF PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 100996 ROF 1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received. 1'b0: Slave bridge can accept more read commands from the NoC 1 1 0x0 R WOE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 101008 WOE 1'b1: There are no write commands outstanding to the attached slave device 2 2 0x1 R ROE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 101020 ROE 1'b1: There are no read commands outstanding to the attached slave device 3 3 0x1 R UNSD_63_4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_SET ns_noc_io_pcie_soc_ip.csr 101030 UNSD_63_4 63 4 0x000000000000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_bridge_id bridge_p0_p1_s_12_10_as_bridge_id PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101061 p0_p1_s register as_bridge_id 0x31D08 R 0x000000000000000c Pcie_noc_bridge_p0_p1_s_12_10_as_bridge_id Unique identifier assigned to the slave bridge. false false false false ID PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 101050 ID Unique bridge ID 15 0 0x000c R UNSD_63_16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 101060 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_err bridge_p0_p1_s_12_10_as_err PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101414 p0_p1_s register as_err 0x31E00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_as_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 101082 E0 1'b1: Read decode error response: Decode error response received from slave device for read command 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 101094 E1 1'b1: Read slave error response: Slave error response received from slave device for read command 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 101107 E2 1'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 101121 E3 1'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 101133 E4 1'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 101144 UNSD_15_5 15 5 0x000 R E16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 101156 E16 1'b1: Write decode error response: Decode error response received from slave device for write command 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 101168 E17 1'b1: Write slave error response: Slave error response received from slave device for write command 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 101181 E18 1'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 101193 E19 1'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge 19 19 0x0 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 101204 UNSD_31_20 31 20 0x000 R E32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 101216 E32 1'b1: [FATAL] Traffic sent to a noc layer which is power gated 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 101227 E33 1'b1: [FATAL] Parity error in config/status registers 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 101238 E34 1'b1: [FATAL] RDATA Parity error 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 101249 E35 1'b1: [FATAL] RRESP Parity error 35 35 0x0 R/W E36 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_SET ns_noc_io_pcie_soc_ip.csr 101260 E36 1'b1: [FATAL] BRESP Parity error 36 36 0x0 R/W E37 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_SET ns_noc_io_pcie_soc_ip.csr 101271 E37 1'b1: [FATAL] AC Parity error 37 37 0x0 R/W E38 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_SET ns_noc_io_pcie_soc_ip.csr 101282 E38 1'b1: [FATAL] ACADDR Parity error 38 38 0x0 R/W E39 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_SET ns_noc_io_pcie_soc_ip.csr 101294 E39 1'b1: [FATAL] R Ch Cmdtbl Parity Err 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 101306 E40 1'b1: [FATAL] B Ch Cmdtbl Parity Err 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 101318 E41 1'b1: [FATAL] Rx Fifo Parity Err 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 101330 E42 1'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 101342 E43 1'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 101354 E44 1'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 101366 E45 1'b1: [FATAL] B Ch Drain Fifo Parity Err 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 101378 E46 1'b1: [FATAL] R Ch Flush Fifo Parity Err 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 101390 E47 1'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 101402 E48 1'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 101413 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p1_s_12_10_as_intm bridge_p0_p1_s_12_10_as_intm PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101754 p0_p1_s register as_intm 0x31E40 R/W 0x0000007d000b0013 Pcie_noc_bridge_p0_p1_s_12_10_as_intm Interrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 101435 M0 Mask interrupts for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 101446 M1 Mask interrupts for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 101457 M2 Mask interrupts for read channel 2 2 0x0 R/W M3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 101468 M3 Mask interrupts for read channel 3 3 0x0 R/W M4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 101479 M4 Mask interrupts for read channel 4 4 0x1 R/W UNSD_15_5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 101490 UNSD_15_5 15 5 0x000 R M16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 101501 M16 Mask interrupts for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 101512 M17 Mask interrupts for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 101523 M18 Mask interrupts for write channel 18 18 0x0 R/W M19 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 101534 M19 Mask interrupts for write channel 19 19 0x1 R/W UNSD_31_20 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_SET ns_noc_io_pcie_soc_ip.csr 101545 UNSD_31_20 31 20 0x000 R M32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 101556 M32 Mask interrupt on traffic to PG layer 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 101567 M33 Mask interrupt on csr parity errors 33 33 0x0 R/W M34 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 101578 M34 RDATA parity interrupt Mask 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 101589 M35 RRESP parity interrupt Mask 35 35 0x1 R/W M36 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_SET ns_noc_io_pcie_soc_ip.csr 101600 M36 BRESP parity interrupt Mask 36 36 0x1 R/W M37 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_SET ns_noc_io_pcie_soc_ip.csr 101611 M37 AC parity interrupt Mask 37 37 0x1 R/W M38 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_SET ns_noc_io_pcie_soc_ip.csr 101622 M38 ACADDR parity interrupt Mask 38 38 0x1 R/W E39 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_SET ns_noc_io_pcie_soc_ip.csr 101634 E39 1'b1: R Ch Cmdtbl Parity Err Intr Mask 39 39 0x0 R E40 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_SET ns_noc_io_pcie_soc_ip.csr 101646 E40 1'b1: B Ch Cmdtbl Parity Err Intr Mask 40 40 0x0 R E41 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_SET ns_noc_io_pcie_soc_ip.csr 101658 E41 1'b1: Rx Fifo Parity Err Intr Mask 41 41 0x0 R E42 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_SET ns_noc_io_pcie_soc_ip.csr 101670 E42 1'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask 42 42 0x0 R E43 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_SET ns_noc_io_pcie_soc_ip.csr 101682 E43 1'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask 43 43 0x0 R E44 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_SET ns_noc_io_pcie_soc_ip.csr 101694 E44 1'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask 44 44 0x0 R E45 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_SET ns_noc_io_pcie_soc_ip.csr 101706 E45 1'b1: B Ch Drain Fifo Parity Err Intr Mask 45 45 0x0 R E46 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_SET ns_noc_io_pcie_soc_ip.csr 101718 E46 1'b1: R Ch Flush Fifo Parity Err Intr Mask 46 46 0x0 R E47 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 101730 E47 1'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 101742 E48 1'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask 48 48 0x0 R UNSD_63_49 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_SET ns_noc_io_pcie_soc_ip.csr 101753 UNSD_63_49 63 49 0x0000 R register pcie_noc.bridge_p0_p1_s_12_10_as_ccmd bridge_p0_p1_s_12_10_as_ccmd PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101829 p0_p1_s register as_ccmd 0x31F00 R/W 0x0000000003000000 Pcie_noc_bridge_p0_p1_s_12_10_as_ccmd Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 101772 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_SET ns_noc_io_pcie_soc_ip.csr 101783 rdy 1'b1: Ready 24 24 0x1 R/W val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_SET ns_noc_io_pcie_soc_ip.csr 101794 val 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 101805 UNSD_27_26 27 26 0x0 R intfid PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_SET ns_noc_io_pcie_soc_ip.csr 101817 intfid 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_63_31 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_SET ns_noc_io_pcie_soc_ip.csr 101828 UNSD_63_31 63 31 0x000000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_ccmdmsk bridge_p0_p1_s_12_10_as_ccmdmsk PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101881 p0_p1_s register as_ccmdmsk 0x31F08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_as_ccmdmsk Not applicable for current release. false false false false UNSD_23_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_SET ns_noc_io_pcie_soc_ip.csr 101847 UNSD_23_0 23 0 0x000000 R rdy PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_SET ns_noc_io_pcie_soc_ip.csr 101858 rdy 1'b1: Ready 24 24 0x0 R/W val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_SET ns_noc_io_pcie_soc_ip.csr 101869 val 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 101880 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_cntr bridge_p0_p1_s_12_10_as_cntr PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 101911 p0_p1_s register as_cntr 0x31F10 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_as_cntr Not applicable for current release. false false false false CNTR PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_SET ns_noc_io_pcie_soc_ip.csr 101900 CNTR Counter 31 0 0x00000000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 101910 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_arovrd bridge_p0_p1_s_12_10_as_arovrd PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102024 p0_p1_s register as_arovrd 0x31F18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_as_arovrd AR Overrides. false false false false arcache_val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 101929 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 101942 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 101953 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 101964 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 101977 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 101988 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 101999 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 102012 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 102023 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p1_s_12_10_as_awovrd bridge_p0_p1_s_12_10_as_awovrd PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102137 p0_p1_s register as_awovrd 0x31F20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_as_awovrd AW Overrides. false false false false awcache_val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 102042 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 102055 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 102066 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 102077 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 102090 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 102101 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 102112 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 102125 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 102136 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_p1_s_12_10_p_0 bridge_p0_p1_s_12_10_p_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102202 p0_p1_s register p_0 0x33000 R/W 0x00000003 Pcie_noc_bridge_p0_p1_s_12_10_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 102165 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 102177 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 102189 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 102201 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_p_1 bridge_p0_p1_s_12_10_p_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102268 p0_p1_s register p_1 0x33008 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 102231 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 102243 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 102255 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 102267 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_p_2 bridge_p0_p1_s_12_10_p_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102334 p0_p1_s register p_2 0x33010 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 102297 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 102309 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 102321 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 102333 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_p_3 bridge_p0_p1_s_12_10_p_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102400 p0_p1_s register p_3 0x33018 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 102363 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 102375 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 102387 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 102399 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_txe bridge_p0_p1_s_12_10_txe PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102546 p0_p1_s register txe 0x33040 R/W 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 102427 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 102439 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 102454 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 102467 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 102481 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 102495 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 102509 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 102523 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 102534 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 102545 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p1_s_12_10_txem bridge_p0_p1_s_12_10_txem PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102625 p0_p1_s register txem 0x33048 R/W 0x00000008 Pcie_noc_bridge_p0_p1_s_12_10_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 102569 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 102580 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 102591 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 102602 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 102613 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 102624 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_p1_s_12_10_btus_0 bridge_p0_p1_s_12_10_btus_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 102993 p0_p1_s register btus_0 0x33058 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 102651 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 102662 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 102673 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 102684 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 102695 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 102706 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 102717 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 102728 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 102739 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 102750 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 102761 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 102772 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 102783 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 102794 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 102805 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 102816 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 102827 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 102838 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 102849 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 102860 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 102871 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 102882 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 102893 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 102904 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 102915 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 102926 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 102937 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 102948 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 102959 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 102970 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 102981 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 102992 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_p1_s_12_10_btus_1 bridge_p0_p1_s_12_10_btus_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 103361 p0_p1_s register btus_1 0x33060 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 103019 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 103030 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 103041 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 103052 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 103063 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 103074 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 103085 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 103096 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 103107 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 103118 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 103129 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 103140 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 103151 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 103162 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 103173 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 103184 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 103195 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 103206 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 103217 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 103228 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 103239 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 103250 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 103261 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 103272 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 103283 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 103294 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 103305 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 103316 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 103327 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 103338 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 103349 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 103360 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_p1_s_12_10_btrl_0 bridge_p0_p1_s_12_10_btrl_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 103437 p0_p1_s register btrl_0 0x33080 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 103385 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 103396 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 103411 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 103425 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 103436 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_s_12_10_btrl_1 bridge_p0_p1_s_12_10_btrl_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 103513 p0_p1_s register btrl_1 0x33088 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 103461 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 103472 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 103487 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 103501 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 103512 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_s_12_10_btrl_2 bridge_p0_p1_s_12_10_btrl_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 103589 p0_p1_s register btrl_2 0x33090 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 103537 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 103548 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 103563 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 103577 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 103588 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_s_12_10_btrl_3 bridge_p0_p1_s_12_10_btrl_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 103665 p0_p1_s register btrl_3 0x33098 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 103613 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 103624 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 103639 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 103653 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 103664 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_p1_s_12_10_btperr bridge_p0_p1_s_12_10_btperr PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 103867 p0_p1_s register btperr 0x330A8 R/W 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 103690 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 103701 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 103712 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 103723 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 103734 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 103745 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 103756 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 103767 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 103778 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 103789 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 103800 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 103811 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 103822 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 103833 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 103844 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 103855 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 103866 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p1_s_12_10_btperrm bridge_p0_p1_s_12_10_btperrm PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 104067 p0_p1_s register btperrm 0x330B0 R/W 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 103890 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 103901 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 103912 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 103923 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 103934 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 103945 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 103956 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 103967 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 103978 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 103989 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 104000 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 104011 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 104022 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 104033 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 104044 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 104055 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 104066 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_p1_s_12_10_rxe bridge_p0_p1_s_12_10_rxe PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 104175 p0_p1_s register rxe 0x33120 R/W 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 104095 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 104106 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 104117 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 104128 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 104140 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 104151 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 104163 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 104174 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p1_s_12_10_rxem bridge_p0_p1_s_12_10_rxem PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 104247 p0_p1_s register rxem 0x33128 R/W 0x00000050 Pcie_noc_bridge_p0_p1_s_12_10_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 104196 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 104210 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 104221 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 104235 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 104246 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_p1_s_12_10_brs_0 bridge_p0_p1_s_12_10_brs_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 104521 p0_p1_s register brs_0 0x33130 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 104271 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 104282 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 104293 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 104304 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 104315 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 104325 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 104336 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 104347 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 104358 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 104369 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 104380 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 104390 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 104401 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 104412 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 104423 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 104434 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 104445 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 104455 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 104466 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 104477 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 104488 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 104499 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 104510 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 104520 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p1_s_12_10_brs_1 bridge_p0_p1_s_12_10_brs_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 104795 p0_p1_s register brs_1 0x33138 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 104545 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 104556 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 104567 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 104578 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 104589 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 104599 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 104610 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 104621 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 104632 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 104643 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 104654 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 104664 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 104675 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 104686 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 104697 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 104708 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 104719 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 104729 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 104740 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 104751 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 104762 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 104773 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 104784 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 104794 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_p1_s_12_10_brus bridge_p0_p1_s_12_10_brus PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 104864 p0_p1_s register brus 0x331B0 R 0x00000000 Pcie_noc_bridge_p0_p1_s_12_10_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 104820 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 104831 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 104842 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 104853 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 104863 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_p1_s_12_10_brperr0 bridge_p0_p1_s_12_10_brperr0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105092 p0_p1_s register brperr0 0x331D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 104902 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 104913 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 104924 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 104936 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 104947 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 104958 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 104969 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 104980 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 104991 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 105003 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 105014 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 105025 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 105036 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 105047 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 105058 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 105069 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 105080 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 105091 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_brperr1 bridge_p0_p1_s_12_10_brperr1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105208 p0_p1_s register brperr1 0x331D8 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 105130 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 105141 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 105152 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 105163 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 105174 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 105185 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 105196 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 105207 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_brperrm0 bridge_p0_p1_s_12_10_brperrm0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105429 p0_p1_s register brperrm0 0x331E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 105235 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 105247 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 105258 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 105270 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 105282 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 105293 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 105304 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 105316 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 105327 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 105339 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 105351 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 105362 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 105373 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 105384 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 105395 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 105406 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 105417 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 105428 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_p1_s_12_10_brperrm1 bridge_p0_p1_s_12_10_brperrm1 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105534 p0_p1_s register brperrm1 0x331E8 R 0x0000000000000000 Pcie_noc_bridge_p0_p1_s_12_10_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 105456 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 105467 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 105478 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 105489 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 105500 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 105511 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 105522 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 105533 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105650 p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x34000 R/W 0x0000000058200000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 105574 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 105585 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 105596 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 105608 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 105619 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 105631 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 105642 BASE_ADDRESS_0_33 Base address 39 6 0x001608000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 105649 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105742 p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 0x34008 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 105667 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 105678 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 105689 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 105700 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 105712 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 105723 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 105734 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 105741 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105858 p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 0x34020 R/W 0x0000000058201000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 105782 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 105793 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 105804 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 105816 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 105827 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 105839 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 105850 BASE_ADDRESS_0_33 Base address 39 6 0x001608040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 105857 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 105950 p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 0x34028 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 105875 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 105886 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 105897 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 105908 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 105920 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 105931 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 105942 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 105949 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106066 p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 0x34040 R/W 0x0000000058400000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 105990 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106001 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 106012 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 106024 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 106035 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 106047 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 106058 BASE_ADDRESS_0_33 Base address 39 6 0x001610000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106065 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106158 p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 0x34048 R/W 0x000000ffffe00000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 106083 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106094 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 106105 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 106116 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 106128 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 106139 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 106150 MASK_0_33 Mask 39 6 0x3ffff8000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106157 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106274 p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x34060 R/W 0x0000007f80000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 106198 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106209 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 106220 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 106232 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 106243 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 106255 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 106266 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106273 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106366 p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x34068 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 106291 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106302 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 106313 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 106324 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 106336 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 106347 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 106358 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106365 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106407 p0_spio_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 0x34070 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 106384 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 106395 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 106406 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106523 p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x34080 R/W 0x0000007f80001000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 106447 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106458 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 106469 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 106481 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 106492 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 106504 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 106515 BASE_ADDRESS_0_33 Base address 39 6 0x1fe000040 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106522 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106615 p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x34088 R/W 0x000000fffffff000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 106540 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106551 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 106562 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 106573 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 106585 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 106596 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 106607 MASK_0_33 Mask 39 6 0x3ffffffc0 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106614 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106656 p0_spio_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 0x34090 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 106633 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 106644 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 106655 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106772 p0_spio_m register am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x340A0 R/W 0x0000007e80000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 106696 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106707 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 106718 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 106730 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 106741 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 106753 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 106764 BASE_ADDRESS_0_33 Base address 39 6 0x1fa000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106771 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106864 p0_spio_m register am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x340A8 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 106789 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106800 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 106811 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 106822 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 106834 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 106845 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 106856 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 106863 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 106905 p0_spio_m register am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 0x340B0 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 106882 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 106893 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 106904 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107021 p0_spio_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x340C0 R/W 0x0000004000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 106945 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 106956 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 106967 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 106979 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 106990 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 107002 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 107013 BASE_ADDRESS_0_33 Base address 39 6 0x100000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107020 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107113 p0_spio_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 0x340C8 R/W 0x000000e000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 107038 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107049 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 107060 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 107071 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 107083 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 107094 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 107105 MASK_0_33 Mask 39 6 0x380000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107112 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107229 p0_spio_m register am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x340E0 R/W 0x0000007f00000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 107153 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107164 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 107175 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 107187 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 107198 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 107210 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 107221 BASE_ADDRESS_0_33 Base address 39 6 0x1fc000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107228 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107321 p0_spio_m register am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x340E8 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 107246 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107257 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 107268 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 107279 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 107291 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 107302 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 107313 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107320 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107362 p0_spio_m register am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 0x340F0 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0 See AM_ADBASE. false false false false UNSD_5_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_SET ns_noc_io_pcie_soc_ip.csr 107339 UNSD_5_0 Unused 5 0 0x00 R SLV_RELOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_SET ns_noc_io_pcie_soc_ip.csr 107350 SLV_RELOC Slave Reloc 39 6 0x000000000 R UNSD PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_SET ns_noc_io_pcie_soc_ip.csr 107361 UNSD Unused 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107478 p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x34100 R/W 0x0000006000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 107402 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107413 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 107424 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 107436 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SET ns_noc_io_pcie_soc_ip.csr 107447 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 107459 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 107470 BASE_ADDRESS_0_33 Base address 39 6 0x180000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107477 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107570 p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 0x34108 R/W 0x000000f000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SET ns_noc_io_pcie_soc_ip.csr 107495 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107506 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SET ns_noc_io_pcie_soc_ip.csr 107517 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 107528 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SET ns_noc_io_pcie_soc_ip.csr 107540 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 107551 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 107562 MASK_0_33 Mask 39 6 0x3c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107569 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107686 p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x34120 R/W 0x0000007000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 107610 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107621 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 107632 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 107644 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SET ns_noc_io_pcie_soc_ip.csr 107655 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 107667 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 107678 BASE_ADDRESS_0_33 Base address 39 6 0x1c0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107685 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107778 p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 0x34128 R/W 0x000000f800000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SET ns_noc_io_pcie_soc_ip.csr 107703 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107714 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SET ns_noc_io_pcie_soc_ip.csr 107725 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 107736 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SET ns_noc_io_pcie_soc_ip.csr 107748 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 107759 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 107770 MASK_0_33 Mask 39 6 0x3e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107777 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107894 p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x34140 R/W 0x0000007800000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 107818 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107829 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 107840 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 107852 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SET ns_noc_io_pcie_soc_ip.csr 107863 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 107875 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 107886 BASE_ADDRESS_0_33 Base address 39 6 0x1e0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107893 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 107986 p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 0x34148 R/W 0x000000fc00000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SET ns_noc_io_pcie_soc_ip.csr 107911 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SET ns_noc_io_pcie_soc_ip.csr 107922 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SET ns_noc_io_pcie_soc_ip.csr 107933 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 107944 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SET ns_noc_io_pcie_soc_ip.csr 107956 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 107967 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 107978 MASK_0_33 Mask 39 6 0x3f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 107985 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108102 p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x34160 R/W 0x0000007c00000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 108026 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 108037 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 108048 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 108060 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SET ns_noc_io_pcie_soc_ip.csr 108071 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 108083 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 108094 BASE_ADDRESS_0_33 Base address 39 6 0x1f0000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 108101 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108194 p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 0x34168 R/W 0x000000fe00000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SET ns_noc_io_pcie_soc_ip.csr 108119 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SET ns_noc_io_pcie_soc_ip.csr 108130 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SET ns_noc_io_pcie_soc_ip.csr 108141 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 108152 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SET ns_noc_io_pcie_soc_ip.csr 108164 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 108175 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 108186 MASK_0_33 Mask 39 6 0x3f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 108193 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108310 p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x34180 R/W 0x0000007e00000000 Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 108234 P 1'b1: Privileged 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 108245 NS 1'b1: Non-secure 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 108256 I 1'b1: Instruction 2 2 0x0 R/W R_Wn PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SET ns_noc_io_pcie_soc_ip.csr 108268 R_Wn 1'b1: Read enabled to range 1'b0: Write enabled to range 3 3 0x0 R/W DI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SET ns_noc_io_pcie_soc_ip.csr 108279 DI 1'b1: Address range disabled 4 4 0x0 R/W LLC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SET ns_noc_io_pcie_soc_ip.csr 108291 LLC LLC disable 5 5 0x0 R BASE_ADDRESS_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SET ns_noc_io_pcie_soc_ip.csr 108302 BASE_ADDRESS_0_33 Base address 39 6 0x1f8000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 108309 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108402 p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 0x34188 R/W 0x000000ff80000000 Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0 See AM_ADBASE. false false false false P PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SET ns_noc_io_pcie_soc_ip.csr 108327 P 1'b1: Privileged field is valid 0 0 0x0 R/W NS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SET ns_noc_io_pcie_soc_ip.csr 108338 NS 1'b1: Non-secure field is valid 1 1 0x0 R/W I PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SET ns_noc_io_pcie_soc_ip.csr 108349 I 1'b1: Instruction field is valid 2 2 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SET ns_noc_io_pcie_soc_ip.csr 108360 VAL 1'b1: R_Wn field is valid 3 3 0x0 R/W TM PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SET ns_noc_io_pcie_soc_ip.csr 108372 TM 1'b1: Enable Trusted Master behavior for secure transactions 4 4 0x0 R/W RSV PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SET ns_noc_io_pcie_soc_ip.csr 108383 RSV Reserved 5 5 0x0 R/W MASK_0_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SET ns_noc_io_pcie_soc_ip.csr 108394 MASK_0_33 Mask 39 6 0x3fe000000 R/W UNSD_34_57 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SET ns_noc_io_pcie_soc_ip.csr 108401 UNSD_34_57 63 40 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_p_0 bridge_p0_spio_m_5_7_p_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108467 p0_spio_m register p_0 0x37000 R/W 0x00000003 Pcie_noc_bridge_p0_spio_m_5_7_p_0 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_SET ns_noc_io_pcie_soc_ip.csr 108430 WT_QOS_0 Weight of QoS profile 0 7 0 0x03 R/W WT_QOS_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_SET ns_noc_io_pcie_soc_ip.csr 108442 WT_QOS_1 Weight of QoS profile 1 15 8 0x00 R WT_QOS_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_SET ns_noc_io_pcie_soc_ip.csr 108454 WT_QOS_2 Weight of QoS profile 2 23 16 0x00 R WT_QOS_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_SET ns_noc_io_pcie_soc_ip.csr 108466 WT_QOS_3 Weight of QoS profile 3 31 24 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_p_1 bridge_p0_spio_m_5_7_p_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108533 p0_spio_m register p_1 0x37008 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_p_1 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_SET ns_noc_io_pcie_soc_ip.csr 108496 WT_QOS_4 Weight of QoS profile 4 7 0 0x00 R WT_QOS_5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_SET ns_noc_io_pcie_soc_ip.csr 108508 WT_QOS_5 Weight of QoS profile 5 15 8 0x00 R WT_QOS_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_SET ns_noc_io_pcie_soc_ip.csr 108520 WT_QOS_6 Weight of QoS profile 6 23 16 0x00 R WT_QOS_7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_SET ns_noc_io_pcie_soc_ip.csr 108532 WT_QOS_7 Weight of QoS profile 7 31 24 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_p_2 bridge_p0_spio_m_5_7_p_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108599 p0_spio_m register p_2 0x37010 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_p_2 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_SET ns_noc_io_pcie_soc_ip.csr 108562 WT_QOS_8 Weight of QoS profile 8 7 0 0x00 R WT_QOS_9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_SET ns_noc_io_pcie_soc_ip.csr 108574 WT_QOS_9 Weight of QoS profile 9 15 8 0x00 R WT_QOS_10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_SET ns_noc_io_pcie_soc_ip.csr 108586 WT_QOS_10 Weight of QoS profile 10 23 16 0x00 R WT_QOS_11 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_SET ns_noc_io_pcie_soc_ip.csr 108598 WT_QOS_11 Weight of QoS profile 11 31 24 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_p_3 bridge_p0_spio_m_5_7_p_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108665 p0_spio_m register p_3 0x37018 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_p_3 This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers. QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available. false false false false WT_QOS_12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_SET ns_noc_io_pcie_soc_ip.csr 108628 WT_QOS_12 Weight of QoS profile 12 7 0 0x00 R WT_QOS_13 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_SET ns_noc_io_pcie_soc_ip.csr 108640 WT_QOS_13 Weight of QoS profile 13 15 8 0x00 R WT_QOS_14 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_SET ns_noc_io_pcie_soc_ip.csr 108652 WT_QOS_14 Weight of QoS profile 14 23 16 0x00 R WT_QOS_15 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_SET ns_noc_io_pcie_soc_ip.csr 108664 WT_QOS_15 Weight of QoS profile 15 31 24 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_txe bridge_p0_spio_m_5_7_txe PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108811 p0_spio_m register txe 0x37040 R/W 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_txe This register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted. false false false false TRANS_WITHOUT_SOP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_SET ns_noc_io_pcie_soc_ip.csr 108692 TRANS_WITHOUT_SOP 1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked. 0 0 0x0 R/W SOP_AFTER_SOP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_SET ns_noc_io_pcie_soc_ip.csr 108704 SOP_AFTER_SOP 1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked. 1 1 0x0 R/W TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 108719 TRANS_ILLEGAL_DEST_QOS 1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge. 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 108732 EVENT_CNTR_OVERFLOW 1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition 3 3 0x0 R/W FIFO_OVERFLOW_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_SET ns_noc_io_pcie_soc_ip.csr 108746 FIFO_OVERFLOW_A Host interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 4 4 0x0 R/W FIFO_OVERFLOW_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_SET ns_noc_io_pcie_soc_ip.csr 108760 FIFO_OVERFLOW_B Host interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 5 5 0x0 R/W FIFO_OVERFLOW_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_SET ns_noc_io_pcie_soc_ip.csr 108774 FIFO_OVERFLOW_C Host interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 6 6 0x0 R/W FIFO_OVERFLOW_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_SET ns_noc_io_pcie_soc_ip.csr 108788 FIFO_OVERFLOW_D Host interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked 7 7 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 108799 PARITY_ERR Register parity error interrupt. 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 108810 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_txem bridge_p0_spio_m_5_7_txem PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 108890 p0_spio_m register txem 0x37048 R/W 0x00000008 Pcie_noc_bridge_p0_spio_m_5_7_txem This register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system. false false false false UNSD_1_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_SET ns_noc_io_pcie_soc_ip.csr 108834 UNSD_1_0 1 0 0x0 R TRANS_ILLEGAL_DEST_QOS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SET ns_noc_io_pcie_soc_ip.csr 108845 TRANS_ILLEGAL_DEST_QOS Interrupt mask for illegal destination QoS 2 2 0x0 R/W EVENT_CNTR_OVERFLOW PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_SET ns_noc_io_pcie_soc_ip.csr 108856 EVENT_CNTR_OVERFLOW Interrupt mask for event counter overflow 3 3 0x1 R/W UNSD_7_4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_SET ns_noc_io_pcie_soc_ip.csr 108867 UNSD_7_4 7 4 0x0 R PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 108878 PARITY_ERR_MASK Interrupt mask for register parity error 8 8 0x0 R/W UNSD_31_9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_SET ns_noc_io_pcie_soc_ip.csr 108889 UNSD_31_9 31 9 0x000000 R register pcie_noc.bridge_p0_spio_m_5_7_btus_0 bridge_p0_spio_m_5_7_btus_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 109258 p0_spio_m register btus_0 0x37058 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btus_0 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L0_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_SET ns_noc_io_pcie_soc_ip.csr 108916 L0_A Interface upsizer status for interface A, Layer 0 0 0 0x0 R L0_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_SET ns_noc_io_pcie_soc_ip.csr 108927 L0_B Interface upsizer status for interface B, Layer 0 1 1 0x0 R L0_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_SET ns_noc_io_pcie_soc_ip.csr 108938 L0_C Interface upsizer status for interface C, Layer 0 2 2 0x0 R L0_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_SET ns_noc_io_pcie_soc_ip.csr 108949 L0_D Interface upsizer status for interface D, Layer 0 3 3 0x0 R L1_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_SET ns_noc_io_pcie_soc_ip.csr 108960 L1_A Interface upsizer status for interface A, Layer 1 4 4 0x0 R L1_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_SET ns_noc_io_pcie_soc_ip.csr 108971 L1_B Interface upsizer status for interface B, Layer 1 5 5 0x0 R L1_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_SET ns_noc_io_pcie_soc_ip.csr 108982 L1_C Interface upsizer status for interface C, Layer 1 6 6 0x0 R L1_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_SET ns_noc_io_pcie_soc_ip.csr 108993 L1_D Interface upsizer status for interface D, Layer 1 7 7 0x0 R L2_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_SET ns_noc_io_pcie_soc_ip.csr 109004 L2_A Interface upsizer status for interface A, Layer 2 8 8 0x0 R L2_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_SET ns_noc_io_pcie_soc_ip.csr 109015 L2_B Interface upsizer status for interface B, Layer 2 9 9 0x0 R L2_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_SET ns_noc_io_pcie_soc_ip.csr 109026 L2_C Interface upsizer status for interface C, Layer 2 10 10 0x0 R L2_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_SET ns_noc_io_pcie_soc_ip.csr 109037 L2_D Interface upsizer status for interface D, Layer 2 11 11 0x0 R L3_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_SET ns_noc_io_pcie_soc_ip.csr 109048 L3_A Interface upsizer status for interface A, Layer 3 12 12 0x0 R L3_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_SET ns_noc_io_pcie_soc_ip.csr 109059 L3_B Interface upsizer status for interface B, Layer 3 13 13 0x0 R L3_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_SET ns_noc_io_pcie_soc_ip.csr 109070 L3_C Interface upsizer status for interface C, Layer 3 14 14 0x0 R L3_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_SET ns_noc_io_pcie_soc_ip.csr 109081 L3_D Interface upsizer status for interface D, Layer 3 15 15 0x0 R L4_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_SET ns_noc_io_pcie_soc_ip.csr 109092 L4_A Interface upsizer status for interface A, Layer 4 16 16 0x0 R L4_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_SET ns_noc_io_pcie_soc_ip.csr 109103 L4_B Interface upsizer status for interface B, Layer 4 17 17 0x0 R L4_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_SET ns_noc_io_pcie_soc_ip.csr 109114 L4_C Interface upsizer status for interface C, Layer 4 18 18 0x0 R L4_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_SET ns_noc_io_pcie_soc_ip.csr 109125 L4_D Interface upsizer status for interface D, Layer 4 19 19 0x0 R L5_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_SET ns_noc_io_pcie_soc_ip.csr 109136 L5_A Interface upsizer status for interface A, Layer 5 20 20 0x0 R L5_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_SET ns_noc_io_pcie_soc_ip.csr 109147 L5_B Interface upsizer status for interface B, Layer 5 21 21 0x0 R L5_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_SET ns_noc_io_pcie_soc_ip.csr 109158 L5_C Interface upsizer status for interface C, Layer 5 22 22 0x0 R L5_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_SET ns_noc_io_pcie_soc_ip.csr 109169 L5_D Interface upsizer status for interface D, Layer 5 23 23 0x0 R L6_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_SET ns_noc_io_pcie_soc_ip.csr 109180 L6_A Interface upsizer status for interface A, Layer 6 24 24 0x0 R L6_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_SET ns_noc_io_pcie_soc_ip.csr 109191 L6_B Interface upsizer status for interface B, Layer 6 25 25 0x0 R L6_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_SET ns_noc_io_pcie_soc_ip.csr 109202 L6_C Interface upsizer status for interface C, Layer 6 26 26 0x0 R L6_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_SET ns_noc_io_pcie_soc_ip.csr 109213 L6_D Interface upsizer status for interface D, Layer 6 27 27 0x0 R L7_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_SET ns_noc_io_pcie_soc_ip.csr 109224 L7_A Interface upsizer status for interface A, Layer 7 28 28 0x0 R L7_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_SET ns_noc_io_pcie_soc_ip.csr 109235 L7_B Interface upsizer status for interface B, Layer 7 29 29 0x0 R L7_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_SET ns_noc_io_pcie_soc_ip.csr 109246 L7_C Interface upsizer status for interface C, Layer 7 30 30 0x0 R L7_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_SET ns_noc_io_pcie_soc_ip.csr 109257 L7_D Interface upsizer status for interface D, Layer 7 31 31 0x0 R register pcie_noc.bridge_p0_spio_m_5_7_btus_1 bridge_p0_spio_m_5_7_btus_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 109626 p0_spio_m register btus_1 0x37060 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btus_1 These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15). false false false false L8_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_SET ns_noc_io_pcie_soc_ip.csr 109284 L8_A Interface upsizer status for interface A, Layer 8 0 0 0x0 R L8_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_SET ns_noc_io_pcie_soc_ip.csr 109295 L8_B Interface upsizer status for interface B, Layer 8 1 1 0x0 R L8_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_SET ns_noc_io_pcie_soc_ip.csr 109306 L8_C Interface upsizer status for interface C, Layer 8 2 2 0x0 R L8_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_SET ns_noc_io_pcie_soc_ip.csr 109317 L8_D Interface upsizer status for interface D, Layer 8 3 3 0x0 R L9_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_SET ns_noc_io_pcie_soc_ip.csr 109328 L9_A Interface upsizer status for interface A, Layer 9 4 4 0x0 R L9_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_SET ns_noc_io_pcie_soc_ip.csr 109339 L9_B Interface upsizer status for interface B, Layer 9 5 5 0x0 R L9_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_SET ns_noc_io_pcie_soc_ip.csr 109350 L9_C Interface upsizer status for interface C, Layer 9 6 6 0x0 R L9_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_SET ns_noc_io_pcie_soc_ip.csr 109361 L9_D Interface upsizer status for interface D, Layer 9 7 7 0x0 R L10_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_SET ns_noc_io_pcie_soc_ip.csr 109372 L10_A Interface upsizer status for interface A, Layer 10 8 8 0x0 R L10_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_SET ns_noc_io_pcie_soc_ip.csr 109383 L10_B Interface upsizer status for interface B, Layer 10 9 9 0x0 R L10_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_SET ns_noc_io_pcie_soc_ip.csr 109394 L10_C Interface upsizer status for interface C, Layer 10 10 10 0x0 R L10_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_SET ns_noc_io_pcie_soc_ip.csr 109405 L10_D Interface upsizer status for interface D, Layer 10 11 11 0x0 R L11_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_SET ns_noc_io_pcie_soc_ip.csr 109416 L11_A Interface upsizer status for interface A, Layer 11 12 12 0x0 R L11_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_SET ns_noc_io_pcie_soc_ip.csr 109427 L11_B Interface upsizer status for interface B, Layer 11 13 13 0x0 R L11_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_SET ns_noc_io_pcie_soc_ip.csr 109438 L11_C Interface upsizer status for interface C, Layer 11 14 14 0x0 R L11_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_SET ns_noc_io_pcie_soc_ip.csr 109449 L11_D Interface upsizer status for interface D, Layer 11 15 15 0x0 R L12_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_SET ns_noc_io_pcie_soc_ip.csr 109460 L12_A Interface upsizer status for interface A, Layer 12 16 16 0x0 R L12_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_SET ns_noc_io_pcie_soc_ip.csr 109471 L12_B Interface upsizer status for interface B, Layer 12 17 17 0x0 R L12_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_SET ns_noc_io_pcie_soc_ip.csr 109482 L12_C Interface upsizer status for interface C, Layer 12 18 18 0x0 R L12_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_SET ns_noc_io_pcie_soc_ip.csr 109493 L12_D Interface upsizer status for interface D, Layer 12 19 19 0x0 R L13_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_SET ns_noc_io_pcie_soc_ip.csr 109504 L13_A Interface upsizer status for interface A, Layer 13 20 20 0x0 R L13_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_SET ns_noc_io_pcie_soc_ip.csr 109515 L13_B Interface upsizer status for interface B, Layer 13 21 21 0x0 R L13_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_SET ns_noc_io_pcie_soc_ip.csr 109526 L13_C Interface upsizer status for interface C, Layer 13 22 22 0x0 R L13_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_SET ns_noc_io_pcie_soc_ip.csr 109537 L13_D Interface upsizer status for interface D, Layer 13 23 23 0x0 R L14_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_SET ns_noc_io_pcie_soc_ip.csr 109548 L14_A Interface upsizer status for interface A, Layer 14 24 24 0x0 R L14_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_SET ns_noc_io_pcie_soc_ip.csr 109559 L14_B Interface upsizer status for interface B, Layer 14 25 25 0x0 R L14_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_SET ns_noc_io_pcie_soc_ip.csr 109570 L14_C Interface upsizer status for interface C, Layer 14 26 26 0x0 R L14_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_SET ns_noc_io_pcie_soc_ip.csr 109581 L14_D Interface upsizer status for interface D, Layer 14 27 27 0x0 R L15_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_SET ns_noc_io_pcie_soc_ip.csr 109592 L15_A Interface upsizer status for interface A, Layer 15 28 28 0x0 R L15_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_SET ns_noc_io_pcie_soc_ip.csr 109603 L15_B Interface upsizer status for interface B, Layer 15 29 29 0x0 R L15_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_SET ns_noc_io_pcie_soc_ip.csr 109614 L15_C Interface upsizer status for interface C, Layer 15 30 30 0x0 R L15_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_SET ns_noc_io_pcie_soc_ip.csr 109625 L15_D Interface upsizer status for interface D, Layer 15 31 31 0x0 R register pcie_noc.bridge_p0_spio_m_5_7_btrl_0 bridge_p0_spio_m_5_7_btrl_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 109702 p0_spio_m register btrl_0 0x37080 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btrl_0 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_SET ns_noc_io_pcie_soc_ip.csr 109650 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 109661 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_SET ns_noc_io_pcie_soc_ip.csr 109676 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_SET ns_noc_io_pcie_soc_ip.csr 109690 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 109701 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_spio_m_5_7_btrl_1 bridge_p0_spio_m_5_7_btrl_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 109778 p0_spio_m register btrl_1 0x37088 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btrl_1 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_SET ns_noc_io_pcie_soc_ip.csr 109726 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 109737 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_SET ns_noc_io_pcie_soc_ip.csr 109752 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_SET ns_noc_io_pcie_soc_ip.csr 109766 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 109777 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_spio_m_5_7_btrl_2 bridge_p0_spio_m_5_7_btrl_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 109854 p0_spio_m register btrl_2 0x37090 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btrl_2 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_SET ns_noc_io_pcie_soc_ip.csr 109802 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 109813 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_SET ns_noc_io_pcie_soc_ip.csr 109828 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_SET ns_noc_io_pcie_soc_ip.csr 109842 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 109853 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_spio_m_5_7_btrl_3 bridge_p0_spio_m_5_7_btrl_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 109930 p0_spio_m register btrl_3 0x37098 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btrl_3 This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC. false false false false WT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_SET ns_noc_io_pcie_soc_ip.csr 109878 WT Starting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1. 11 0 0x000 R RESV_15_12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_SET ns_noc_io_pcie_soc_ip.csr 109889 RESV_15_12 15 12 0x0 R CNT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_SET ns_noc_io_pcie_soc_ip.csr 109904 CNT Max Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1. 19 16 0x0 R EN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_SET ns_noc_io_pcie_soc_ip.csr 109918 EN 1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only. 1'b0: Rate limit logic disable 20 20 0x0 R UNSD_31_21 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_SET ns_noc_io_pcie_soc_ip.csr 109929 UNSD_31_21 31 21 0x000 R register pcie_noc.bridge_p0_spio_m_5_7_btperr bridge_p0_spio_m_5_7_btperr PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 110132 p0_spio_m register btperr 0x370A8 R/W 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btperr Transmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. false false false false L0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_SET ns_noc_io_pcie_soc_ip.csr 109955 L0 1'b1: Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_SET ns_noc_io_pcie_soc_ip.csr 109966 L1 1'b1: Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_SET ns_noc_io_pcie_soc_ip.csr 109977 L2 1'b1: Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_SET ns_noc_io_pcie_soc_ip.csr 109988 L3 1'b1: Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_SET ns_noc_io_pcie_soc_ip.csr 109999 L4 1'b1: Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_SET ns_noc_io_pcie_soc_ip.csr 110010 L5 1'b1: Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_SET ns_noc_io_pcie_soc_ip.csr 110021 L6 1'b1: Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_SET ns_noc_io_pcie_soc_ip.csr 110032 L7 1'b1: Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_SET ns_noc_io_pcie_soc_ip.csr 110043 L8 1'b1: Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_SET ns_noc_io_pcie_soc_ip.csr 110054 L9 1'b1: Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_SET ns_noc_io_pcie_soc_ip.csr 110065 L10 1'b1: Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_SET ns_noc_io_pcie_soc_ip.csr 110076 L11 1'b1: Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_SET ns_noc_io_pcie_soc_ip.csr 110087 L12 1'b1: Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_SET ns_noc_io_pcie_soc_ip.csr 110098 L13 1'b1: Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_SET ns_noc_io_pcie_soc_ip.csr 110109 L14 1'b1: Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_SET ns_noc_io_pcie_soc_ip.csr 110120 L15 1'b1: Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_SET ns_noc_io_pcie_soc_ip.csr 110131 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_spio_m_5_7_btperrm bridge_p0_spio_m_5_7_btperrm PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 110332 p0_spio_m register btperrm 0x370B0 R/W 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_btperrm Mask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. false false false false L0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_SET ns_noc_io_pcie_soc_ip.csr 110155 L0 1'b1: Interrupt Mask Credit parity error on layer 0 0 0 0x0 R/W L1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_SET ns_noc_io_pcie_soc_ip.csr 110166 L1 1'b1: Interrupt Mask Credit parity error on layer 1 1 1 0x0 R/W L2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_SET ns_noc_io_pcie_soc_ip.csr 110177 L2 1'b1: Interrupt Mask Credit parity error on layer 2 2 2 0x0 R/W L3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_SET ns_noc_io_pcie_soc_ip.csr 110188 L3 1'b1: Interrupt Mask Credit parity error on layer 3 3 3 0x0 R/W L4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_SET ns_noc_io_pcie_soc_ip.csr 110199 L4 1'b1: Interrupt Mask Credit parity error on layer 4 4 4 0x0 R/W L5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_SET ns_noc_io_pcie_soc_ip.csr 110210 L5 1'b1: Interrupt Mask Credit parity error on layer 5 5 5 0x0 R/W L6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_SET ns_noc_io_pcie_soc_ip.csr 110221 L6 1'b1: Interrupt Mask Credit parity error on layer 6 6 6 0x0 R/W L7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_SET ns_noc_io_pcie_soc_ip.csr 110232 L7 1'b1: Interrupt Mask Credit parity error on layer 7 7 7 0x0 R/W L8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_SET ns_noc_io_pcie_soc_ip.csr 110243 L8 1'b1: Interrupt Mask Credit parity error on layer 8 8 8 0x0 R/W L9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_SET ns_noc_io_pcie_soc_ip.csr 110254 L9 1'b1: Interrupt Mask Credit parity error on layer 9 9 9 0x0 R/W L10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_SET ns_noc_io_pcie_soc_ip.csr 110265 L10 1'b1: Interrupt Mask Credit parity error on layer 10 10 10 0x0 R/W L11 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_SET ns_noc_io_pcie_soc_ip.csr 110276 L11 1'b1: Interrupt Mask Credit parity error on layer 11 11 11 0x0 R/W L12 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_SET ns_noc_io_pcie_soc_ip.csr 110287 L12 1'b1: Interrupt Mask Credit parity error on layer 12 12 12 0x0 R/W L13 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_SET ns_noc_io_pcie_soc_ip.csr 110298 L13 1'b1: Interrupt Mask Credit parity error on layer 13 13 13 0x0 R/W L14 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_SET ns_noc_io_pcie_soc_ip.csr 110309 L14 1'b1: Interrupt Mask Credit parity error on layer 14 14 14 0x0 R/W L15 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_SET ns_noc_io_pcie_soc_ip.csr 110320 L15 1'b1: Interrupt Mask Credit parity error on layer 15 15 15 0x0 R/W UNSD PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_SET ns_noc_io_pcie_soc_ip.csr 110331 UNSD 31 16 0x0000 R register pcie_noc.bridge_p0_spio_m_5_7_rxe bridge_p0_spio_m_5_7_rxe PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 110440 p0_spio_m register rxe 0x37120 R/W 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_rxe This register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked. false false false false CRC_OFLW_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_SET ns_noc_io_pcie_soc_ip.csr 110360 CRC_OFLW_A Credit counter overflow for interface A 0 0 0x0 R/W CRC_OFLW_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_SET ns_noc_io_pcie_soc_ip.csr 110371 CRC_OFLW_B Credit counter overflow for interface B 1 1 0x0 R/W CRC_OFLW_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_SET ns_noc_io_pcie_soc_ip.csr 110382 CRC_OFLW_C Credit counter overflow for interface C 2 2 0x0 R/W CRC_OFLW_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_SET ns_noc_io_pcie_soc_ip.csr 110393 CRC_OFLW_D Credit counter overflow for interface D 3 3 0x0 R/W EVC_OFLW PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_SET ns_noc_io_pcie_soc_ip.csr 110405 EVC_OFLW Event counter overflow. This event can be masked so that no interrupt is sent on an overflow condition. 4 4 0x0 R/W PARITY_ERR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_SET ns_noc_io_pcie_soc_ip.csr 110416 PARITY_ERR Register parity error interrupt 5 5 0x0 R/W EVC1_OFLW PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_SET ns_noc_io_pcie_soc_ip.csr 110428 EVC1_OFLW Event counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition. 6 6 0x0 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 110439 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_spio_m_5_7_rxem bridge_p0_spio_m_5_7_rxem PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 110512 p0_spio_m register rxem 0x37128 R/W 0x00000050 Pcie_noc_bridge_p0_spio_m_5_7_rxem This register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt. false false false false UNSD_3_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_SET ns_noc_io_pcie_soc_ip.csr 110461 UNSD_3_0 3 0 0x0 R EVC_OFLW_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 110475 EVC_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 4 4 0x1 R/W PARITY_ERR_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_SET ns_noc_io_pcie_soc_ip.csr 110486 PARITY_ERR_MASK Interrupt mask for register parity error. 5 5 0x0 R/W EVC1_OFLW_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_SET ns_noc_io_pcie_soc_ip.csr 110500 EVC1_OFLW_MASK 1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system. 1'b0: The corresponding interrupt event will send an interrupt to the system. 6 6 0x1 R/W UNSD_31_7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_SET ns_noc_io_pcie_soc_ip.csr 110511 UNSD_31_7 31 7 0x0000000 R register pcie_noc.bridge_p0_spio_m_5_7_brs_0 bridge_p0_spio_m_5_7_brs_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 110786 p0_spio_m register brs_0 0x37130 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_brs_0 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 110536 OUTI_0 Head flit output interface for VC 0 Layer 0 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_SET ns_noc_io_pcie_soc_ip.csr 110547 V_0 Head flit (buffer ready) for VC 0 Layer 0 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_SET ns_noc_io_pcie_soc_ip.csr 110558 S_0 Head flit sop for VC 0 Layer 0 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_SET ns_noc_io_pcie_soc_ip.csr 110569 B_0 Head flit barrier state for VC 0 Layer 0 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_SET ns_noc_io_pcie_soc_ip.csr 110580 F_0 Buffer full for VC 0 Layer 0 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 110590 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 110601 OUTI_1 Head flit output interface for VC 1 Layer 0 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_SET ns_noc_io_pcie_soc_ip.csr 110612 V_1 Head flit (buffer ready) for VC 1 Layer 0 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_SET ns_noc_io_pcie_soc_ip.csr 110623 S_1 Head flit sop for VC 1 Layer 0 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_SET ns_noc_io_pcie_soc_ip.csr 110634 B_1 Head flit barrier state for VC 1 Layer 0 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_SET ns_noc_io_pcie_soc_ip.csr 110645 F_1 Buffer full for VC 1 Layer 0 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 110655 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 110666 OUTI_2 Head flit output interface for VC 2 Layer 0 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_SET ns_noc_io_pcie_soc_ip.csr 110677 V_2 Head flit (buffer ready) for VC 2 Layer 0 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_SET ns_noc_io_pcie_soc_ip.csr 110688 S_2 Head flit sop for VC 2 Layer 0 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_SET ns_noc_io_pcie_soc_ip.csr 110699 B_2 Head flit barrier state for VC 2 Layer 0 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_SET ns_noc_io_pcie_soc_ip.csr 110710 F_2 Buffer full for VC 2 Layer 0 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 110720 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 110731 OUTI_3 Head flit output interface for VC 3 Layer 0 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_SET ns_noc_io_pcie_soc_ip.csr 110742 V_3 Head flit (buffer ready) for VC 3 Layer 0 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_SET ns_noc_io_pcie_soc_ip.csr 110753 S_3 Head flit sop for VC 3 Layer 0 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_SET ns_noc_io_pcie_soc_ip.csr 110764 B_3 Head flit barrier state for VC 3 Layer 0 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_SET ns_noc_io_pcie_soc_ip.csr 110775 F_3 Buffer full for VC 3 Layer 0 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 110785 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_spio_m_5_7_brs_1 bridge_p0_spio_m_5_7_brs_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111060 p0_spio_m register brs_1 0x37138 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_brs_1 These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer). false false false false OUTI_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_SET ns_noc_io_pcie_soc_ip.csr 110810 OUTI_0 Head flit output interface for VC 0 Layer 1 1 0 0x0 R V_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_SET ns_noc_io_pcie_soc_ip.csr 110821 V_0 Head flit (buffer ready) for VC 0 Layer 1 2 2 0x0 R S_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_SET ns_noc_io_pcie_soc_ip.csr 110832 S_0 Head flit sop for VC 0 Layer 1 3 3 0x0 R B_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_SET ns_noc_io_pcie_soc_ip.csr 110843 B_0 Head flit barrier state for VC 0 Layer 1 4 4 0x0 R F_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_SET ns_noc_io_pcie_soc_ip.csr 110854 F_0 Buffer full for VC 0 Layer 1 5 5 0x0 R UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 110864 UNSD_7_6 7 6 0x0 R OUTI_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_SET ns_noc_io_pcie_soc_ip.csr 110875 OUTI_1 Head flit output interface for VC 1 Layer 1 9 8 0x0 R V_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_SET ns_noc_io_pcie_soc_ip.csr 110886 V_1 Head flit (buffer ready) for VC 1 Layer 1 10 10 0x0 R S_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_SET ns_noc_io_pcie_soc_ip.csr 110897 S_1 Head flit sop for VC 1 Layer 1 11 11 0x0 R B_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_SET ns_noc_io_pcie_soc_ip.csr 110908 B_1 Head flit barrier state for VC 1 Layer 1 12 12 0x0 R F_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_SET ns_noc_io_pcie_soc_ip.csr 110919 F_1 Buffer full for VC 1 Layer 1 13 13 0x0 R UNSD_15_14 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_SET ns_noc_io_pcie_soc_ip.csr 110929 UNSD_15_14 15 14 0x0 R OUTI_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_SET ns_noc_io_pcie_soc_ip.csr 110940 OUTI_2 Head flit output interface for VC 2 Layer 1 17 16 0x0 R V_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_SET ns_noc_io_pcie_soc_ip.csr 110951 V_2 Head flit (buffer ready) for VC 2 Layer 1 18 18 0x0 R S_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_SET ns_noc_io_pcie_soc_ip.csr 110962 S_2 Head flit sop for VC 2 Layer 1 19 19 0x0 R B_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_SET ns_noc_io_pcie_soc_ip.csr 110973 B_2 Head flit barrier state for VC 2 Layer 1 20 20 0x0 R F_2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_SET ns_noc_io_pcie_soc_ip.csr 110984 F_2 Buffer full for VC 2 Layer 1 21 21 0x0 R UNSD_23_22 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_SET ns_noc_io_pcie_soc_ip.csr 110994 UNSD_23_22 23 22 0x0 R OUTI_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_SET ns_noc_io_pcie_soc_ip.csr 111005 OUTI_3 Head flit output interface for VC 3 Layer 1 25 24 0x0 R V_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_SET ns_noc_io_pcie_soc_ip.csr 111016 V_3 Head flit (buffer ready) for VC 3 Layer 1 26 26 0x0 R S_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_SET ns_noc_io_pcie_soc_ip.csr 111027 S_3 Head flit sop for VC 3 Layer 1 27 27 0x0 R B_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_SET ns_noc_io_pcie_soc_ip.csr 111038 B_3 Head flit barrier state for VC 3 Layer 1 28 28 0x0 R F_3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_SET ns_noc_io_pcie_soc_ip.csr 111049 F_3 Buffer full for VC 3 Layer 1 29 29 0x0 R UNSD_31_30 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_SET ns_noc_io_pcie_soc_ip.csr 111059 UNSD_31_30 31 30 0x0 R register pcie_noc.bridge_p0_spio_m_5_7_brus bridge_p0_spio_m_5_7_brus PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111129 p0_spio_m register brus 0x371B0 R 0x00000000 Pcie_noc_bridge_p0_spio_m_5_7_brus This register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces. false false false false V_A PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_SET ns_noc_io_pcie_soc_ip.csr 111085 V_A Interface A upsizer/downsizer valid 0 0 0x0 R V_B PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_SET ns_noc_io_pcie_soc_ip.csr 111096 V_B Interface B upsizer/downsizer valid 1 1 0x0 R V_C PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_SET ns_noc_io_pcie_soc_ip.csr 111107 V_C Interface C upsizer/downsizer valid 2 2 0x0 R V_D PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_SET ns_noc_io_pcie_soc_ip.csr 111118 V_D Interface D upsizer/downsizer valid 3 3 0x0 R UNSD_31_4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_SET ns_noc_io_pcie_soc_ip.csr 111128 UNSD_31_4 31 4 0x0000000 R register pcie_noc.bridge_p0_spio_m_5_7_brperr0 bridge_p0_spio_m_5_7_brperr0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111357 p0_spio_m register brperr0 0x371D0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_brperr0 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false D0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_SET ns_noc_io_pcie_soc_ip.csr 111167 D0 Uncorrectable Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_SET ns_noc_io_pcie_soc_ip.csr 111178 DC0 Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_SET ns_noc_io_pcie_soc_ip.csr 111189 SB0 Uncorrectable User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 111201 SBC0 Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_SET ns_noc_io_pcie_soc_ip.csr 111212 PK0 Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 111223 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_SET ns_noc_io_pcie_soc_ip.csr 111234 D1 Uncorrectable Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_SET ns_noc_io_pcie_soc_ip.csr 111245 DC1 Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_SET ns_noc_io_pcie_soc_ip.csr 111256 SB1 Uncorrectable User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 111268 SBC1 Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_SET ns_noc_io_pcie_soc_ip.csr 111279 PK1 Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 111290 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 111301 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 111312 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 111323 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 111334 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 111345 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 111356 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_brperr1 bridge_p0_spio_m_5_7_brperr1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111473 p0_spio_m register brperr1 0x371D8 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_brperr1 Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored. - Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded. - User sideband ECC/parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 111395 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 111406 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 111417 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 111428 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 111439 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 111450 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 111461 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 111472 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_brperrm0 bridge_p0_spio_m_5_7_brperrm0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111694 p0_spio_m register brperrm0 0x371E0 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_brperrm0 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false D0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_SET ns_noc_io_pcie_soc_ip.csr 111500 D0 Mask Data ECC/parity error in layer 0 0 0 0x0 R/W DC0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_SET ns_noc_io_pcie_soc_ip.csr 111512 DC0 Mask Correctable single bit data error (only ECC) in layer 0 1 1 0x0 R/W SB0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_SET ns_noc_io_pcie_soc_ip.csr 111523 SB0 Mask User sideband ECC/parity error in layer 0 2 2 0x0 R/W SBC0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_SET ns_noc_io_pcie_soc_ip.csr 111535 SBC0 Mask Correctable single bit user sideband error (only ECC) in layer 0 3 3 0x0 R/W PK0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_SET ns_noc_io_pcie_soc_ip.csr 111547 PK0 Mask Parity error in packet delineation controls in layer 0 4 4 0x0 R/W UNSD_7_5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_SET ns_noc_io_pcie_soc_ip.csr 111558 UNSD_7_5 7 5 0x0 R D1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_SET ns_noc_io_pcie_soc_ip.csr 111569 D1 Mask Data ECC/parity error in layer 1 8 8 0x0 R/W DC1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_SET ns_noc_io_pcie_soc_ip.csr 111581 DC1 Mask Correctable single bit data error (only ECC) in layer 1 9 9 0x0 R/W SB1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_SET ns_noc_io_pcie_soc_ip.csr 111592 SB1 Mask User sideband ECC/parity error in layer 1 10 10 0x0 R/W SBC1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_SET ns_noc_io_pcie_soc_ip.csr 111604 SBC1 Mask Correctable single bit user sideband error (only ECC) in layer 1 11 11 0x0 R/W PK1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_SET ns_noc_io_pcie_soc_ip.csr 111616 PK1 Mask Parity error in packet delineation controls in layer 1 12 12 0x0 R/W UNSD_15_13 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_SET ns_noc_io_pcie_soc_ip.csr 111627 UNSD_15_13 15 13 0x0 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 111638 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 111649 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 111660 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 111671 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 111682 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 111693 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_brperrm1 bridge_p0_spio_m_5_7_brperrm1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111799 p0_spio_m register brperrm1 0x371E8 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_brperrm1 Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event. This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help. false false false false UNSD_7_0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_SET ns_noc_io_pcie_soc_ip.csr 111721 UNSD_7_0 7 0 0x00 R UNSD_15_8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_SET ns_noc_io_pcie_soc_ip.csr 111732 UNSD_15_8 15 8 0x00 R UNSD_23_16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_SET ns_noc_io_pcie_soc_ip.csr 111743 UNSD_23_16 23 16 0x00 R UNSD_31_24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_SET ns_noc_io_pcie_soc_ip.csr 111754 UNSD_31_24 31 24 0x00 R UNSD_39_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_SET ns_noc_io_pcie_soc_ip.csr 111765 UNSD_39_32 39 32 0x00 R UNSD_47_40 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_SET ns_noc_io_pcie_soc_ip.csr 111776 UNSD_47_40 47 40 0x00 R UNSD_55_48 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_SET ns_noc_io_pcie_soc_ip.csr 111787 UNSD_55_48 55 48 0x00 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 111798 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_am_tocfg bridge_p0_spio_m_5_7_am_tocfg PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111873 p0_spio_m register am_tocfg 0x37C00 R/W 0x000000000000001f Pcie_noc_bridge_p0_spio_m_5_7_am_tocfg This register is used to configure response timeouts. AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval. AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent. When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited. false false false false TI PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_SET ns_noc_io_pcie_soc_ip.csr 111836 TI Timer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller. 5 0 0x1f R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 111847 UNSD_7_6 7 6 0x0 R EN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_SET ns_noc_io_pcie_soc_ip.csr 111861 EN 1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval. 1'b0: No timestamps are recorded to generate timeout interrupts 8 8 0x0 R/W UNSD_63_9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_SET ns_noc_io_pcie_soc_ip.csr 111872 UNSD_63_9 63 9 0x00000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_osslv bridge_p0_spio_m_5_7_am_osslv PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111908 p0_spio_m register am_osslv 0x37C08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_osslv This register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS. false false false false SLVID PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_SET ns_noc_io_pcie_soc_ip.csr 111896 SLVID A slave ID associated with the current master for command outstanding status 15 0 0x0000 R/W UNSD_63_16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 111907 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_cgc bridge_p0_spio_m_5_7_am_cgc PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111945 p0_spio_m register am_cgc 0x37C10 R/W 0x0000000000000064 Pcie_noc_bridge_p0_spio_m_5_7_am_cgc Programmable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain. false false false false HYSTERESIS_COUNTER PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 111933 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 111944 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_cgo bridge_p0_spio_m_5_7_am_cgo PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 111980 p0_spio_m register am_cgo 0x37C18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_cgo Clock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge. false false false false FPO PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 111968 FPO 1'b1: Clock gating override is enabled (clock gating logic is disabled). 1'b0: Clock gating override is disabled (clock gating logic is enabled). 0 0 0x0 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 111979 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_cfg bridge_p0_spio_m_5_7_am_cfg PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112017 p0_spio_m register am_cfg 0x37C20 R/W 0x0000000000000001 Pcie_noc_bridge_p0_spio_m_5_7_am_cfg Configures the master bridge's support for autowake of power domains. When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state. false false false false AW PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_SET ns_noc_io_pcie_soc_ip.csr 112005 AW 1'b1: Autowake enabled 1'b0: Autowake disabled 0 0 0x1 R/W UNSD_63_1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_SET ns_noc_io_pcie_soc_ip.csr 112016 UNSD_63_1 63 1 0x0000000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_sts bridge_p0_spio_m_5_7_am_sts PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112145 p0_spio_m register am_sts 0x37D00 R 0x000000000000000c Pcie_noc_bridge_p0_spio_m_5_7_am_sts When reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet. When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID. false false false false ROF PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_SET ns_noc_io_pcie_soc_ip.csr 112050 ROF 1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more read requests 0 0 0x0 R WOF PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_SET ns_noc_io_pcie_soc_ip.csr 112064 WOF 1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted 1'b0: Master bridge can accept more write requests 1 1 0x0 R ROE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_SET ns_noc_io_pcie_soc_ip.csr 112076 ROE 1'b1: There are no read commands outstanding from the attached master device 2 2 0x1 R WOE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_SET ns_noc_io_pcie_soc_ip.csr 112088 WOE 1'b1: There are no write commands outstanding from the attached master device 3 3 0x1 R ARS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_SET ns_noc_io_pcie_soc_ip.csr 112099 ARS 1'b1: AR channel is stalled on hazard 4 4 0x0 R AWS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_SET ns_noc_io_pcie_soc_ip.csr 112110 AWS 1'b1: AW channel is stalled on hazard 5 5 0x0 R ARO PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_SET ns_noc_io_pcie_soc_ip.csr 112122 ARO 1'b1: Read commands are outstanding to the slave specified in OSSLV register 6 6 0x0 R AWO PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_SET ns_noc_io_pcie_soc_ip.csr 112134 AWO 1'b1: Write commands are outstanding to the slave specified in OSSLV register 7 7 0x0 R UNSD_63_8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_SET ns_noc_io_pcie_soc_ip.csr 112144 UNSD_63_8 63 8 0x00000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_bridge_id bridge_p0_spio_m_5_7_am_bridge_id PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112175 p0_spio_m register am_bridge_id 0x37D08 R 0x0000000000000005 Pcie_noc_bridge_p0_spio_m_5_7_am_bridge_id Unique identifier assigned to the master bridge. false false false false ID PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_SET ns_noc_io_pcie_soc_ip.csr 112164 ID Unique bridge ID 15 0 0x0005 R UNSD_63_16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_SET ns_noc_io_pcie_soc_ip.csr 112174 UNSD_63_16 63 16 0x000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_err bridge_p0_spio_m_5_7_am_err PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112671 p0_spio_m register am_err 0x37E00 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_err These error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded. false false false false E0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_SET ns_noc_io_pcie_soc_ip.csr 112197 E0 1'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued 0 0 0x0 R/W E1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_SET ns_noc_io_pcie_soc_ip.csr 112209 E1 1'b1: Read address decode error from slave: A decode error response was received from a slave device 1 1 0x0 R/W E2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_SET ns_noc_io_pcie_soc_ip.csr 112221 E2 1'b1: Read slave error: A slave error response was received from a slave device 2 2 0x0 R/W E3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_SET ns_noc_io_pcie_soc_ip.csr 112233 E3 1'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected 3 3 0x0 R/W E4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_SET ns_noc_io_pcie_soc_ip.csr 112245 E4 1'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected 4 4 0x0 R/W E5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_SET ns_noc_io_pcie_soc_ip.csr 112257 E5 1'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table 5 5 0x0 R/W E6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_SET ns_noc_io_pcie_soc_ip.csr 112270 E6 1'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval 6 6 0x0 R/W E7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_SET ns_noc_io_pcie_soc_ip.csr 112283 E7 1'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected 7 7 0x0 R/W E8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_SET ns_noc_io_pcie_soc_ip.csr 112294 E8 1'b1: [FATAL] Unexpected narrow read detected 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 112305 UNSD_15_9 15 9 0x00 R E16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_SET ns_noc_io_pcie_soc_ip.csr 112316 E16 1'b1: Local write address decode error 16 16 0x0 R/W E17 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_SET ns_noc_io_pcie_soc_ip.csr 112327 E17 1'b1: Write address decode error from slave 17 17 0x0 R/W E18 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_SET ns_noc_io_pcie_soc_ip.csr 112338 E18 1'b1: Write slave error 18 18 0x0 R/W E19 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_SET ns_noc_io_pcie_soc_ip.csr 112349 E19 1'b1: Non modifiable WRAP 19 19 0x0 R/W E20 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_SET ns_noc_io_pcie_soc_ip.csr 112360 E20 1'b1: [FATAL] Write exclusive split 20 20 0x0 R/W E21 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_SET ns_noc_io_pcie_soc_ip.csr 112371 E21 1'b1: [FATAL] Write address multi-hit 21 21 0x0 R/W E22 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_SET ns_noc_io_pcie_soc_ip.csr 112382 E22 1'b1: Write respone timeout 22 22 0x0 R/W E23 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_SET ns_noc_io_pcie_soc_ip.csr 112394 E23 1'b1: [FATAL] Write WRAP not equal to supported cacheline size 23 23 0x0 R/W E24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_SET ns_noc_io_pcie_soc_ip.csr 112405 E24 1'b1: [FATAL] Unexpected narrow write detected 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 112416 UNSD_31_25 31 25 0x00 R E32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_SET ns_noc_io_pcie_soc_ip.csr 112427 E32 1'b1: Capture counter0 overflow 32 32 0x0 R/W E33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_SET ns_noc_io_pcie_soc_ip.csr 112438 E33 1'b1: Capture counter1 overflow 33 33 0x0 R/W E34 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_SET ns_noc_io_pcie_soc_ip.csr 112450 E34 1'b1: [FATAL] Traffic sent to a noc layer which is power gate 34 34 0x0 R/W E35 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_SET ns_noc_io_pcie_soc_ip.csr 112462 E35 1'b1: [FATAL] Parity error in configuration/status registers 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 112473 UNSD_39_36 39 36 0x0 R E40 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_SET ns_noc_io_pcie_soc_ip.csr 112485 E40 1'b1: [FATAL] Indicates that portcheck detected error (SIB mode only) 40 40 0x0 R/W E41 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_SET ns_noc_io_pcie_soc_ip.csr 112496 E41 1'b1: [FATAL] AR Parity Err 41 41 0x0 R/W E42 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_SET ns_noc_io_pcie_soc_ip.csr 112507 E42 1'b1: [FATAL] ARADDR Parity Err 42 42 0x0 R/W E43 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_SET ns_noc_io_pcie_soc_ip.csr 112518 E43 1'b1: [FATAL] AW Parity Err 43 43 0x0 R/W E44 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_SET ns_noc_io_pcie_soc_ip.csr 112529 E44 1'b1: [FATAL] AWADDR Parity Err 44 44 0x0 R/W E45 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_SET ns_noc_io_pcie_soc_ip.csr 112540 E45 1'b1: [FATAL] WDATA Parity Err 45 45 0x0 R/W E46 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_SET ns_noc_io_pcie_soc_ip.csr 112551 E46 1'b1: [FATAL] CDDATA Parity Err 46 46 0x0 R/W E47 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_SET ns_noc_io_pcie_soc_ip.csr 112563 E47 1'b1: [FATAL] Ridtbl Entry Parity Err 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_SET ns_noc_io_pcie_soc_ip.csr 112575 E48 1'b1: [FATAL] Widtbl Entry Parity Err 48 48 0x0 R E49 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_SET ns_noc_io_pcie_soc_ip.csr 112587 E49 1'b1: [FATAL] Read Reorder Buffer Parity Err 49 49 0x0 R E50 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_SET ns_noc_io_pcie_soc_ip.csr 112599 E50 1'b1: [FATAL] Write Reorder Buffer Parity Err 50 50 0x0 R E51 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_SET ns_noc_io_pcie_soc_ip.csr 112611 E51 1'b1: [FATAL] Rx Fifo Parity Err 51 51 0x0 R E52 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_SET ns_noc_io_pcie_soc_ip.csr 112623 E52 1'b1: [FATAL] Ack Channel Wack Fifo Parity Error 52 52 0x0 R E53 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_SET ns_noc_io_pcie_soc_ip.csr 112635 E53 1'b1: [FATAL] Ack Channel Rack Fifo Parity Error 53 53 0x0 R E54 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_SET ns_noc_io_pcie_soc_ip.csr 112647 E54 1'b1: [FATAL] CRCD Channel Crid Fifo Parity Error 54 54 0x0 R E55 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_SET ns_noc_io_pcie_soc_ip.csr 112659 E55 1'b1: [FATAL] R Channel Cpkt Fifo Parity Error 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 112670 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_am_toslvid bridge_p0_spio_m_5_7_am_toslvid PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112716 p0_spio_m register am_toslvid 0x37E08 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_toslvid AR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge. false false false false AR_SLVID PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_SET ns_noc_io_pcie_soc_ip.csr 112694 AR_SLVID Slave ID of timed out AR request 15 0 0x0000 R AW_SLVID PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_SET ns_noc_io_pcie_soc_ip.csr 112705 AW_SLVID Slave ID of timed out AW request 31 16 0x0000 R UNSD_63_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 112715 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_era bridge_p0_spio_m_5_7_am_era PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112738 p0_spio_m register am_era 0x37E10 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_era This is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR. false false false false READ_DECERR_ADDRS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 112737 READ_DECERR_ADDRS Read decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_ewa bridge_p0_spio_m_5_7_am_ewa PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 112760 p0_spio_m register am_ewa 0x37E18 R 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_ewa This is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR. false false false false WRITE_DECERR_ADDRS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_SET ns_noc_io_pcie_soc_ip.csr 112759 WRITE_DECERR_ADDRS Write decerr address 63 0 0x0000000000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_intm bridge_p0_spio_m_5_7_am_intm PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113244 p0_spio_m register am_intm 0x37E40 R/W 0x00007e07004f004f Pcie_noc_bridge_p0_spio_m_5_7_am_intm Interrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised. false false false false M0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_SET ns_noc_io_pcie_soc_ip.csr 112782 M0 1'b1: Mask interrupt for read channel 0 0 0x1 R/W M1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_SET ns_noc_io_pcie_soc_ip.csr 112793 M1 1'b1: Mask interrupt for read channel 1 1 0x1 R/W M2 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_SET ns_noc_io_pcie_soc_ip.csr 112804 M2 1'b1: Mask interrupt for read channel 2 2 0x1 R/W M3 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_SET ns_noc_io_pcie_soc_ip.csr 112815 M3 1'b1: Mask interrupt for read channel 3 3 0x1 R/W M4 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_SET ns_noc_io_pcie_soc_ip.csr 112826 M4 1'b1: Mask interrupt for read channel 4 4 0x0 R/W M5 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_SET ns_noc_io_pcie_soc_ip.csr 112837 M5 1'b1: Mask interrupt for read channel 5 5 0x0 R/W M6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_SET ns_noc_io_pcie_soc_ip.csr 112848 M6 1'b1: Mask interrupt for read channel 6 6 0x1 R/W M7 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_SET ns_noc_io_pcie_soc_ip.csr 112859 M7 1'b1: Mask interrupt for read channel 7 7 0x0 R/W M8 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_SET ns_noc_io_pcie_soc_ip.csr 112870 M8 1'b1: Mask interrupt for read channel 8 8 0x0 R/W UNSD_15_9 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_SET ns_noc_io_pcie_soc_ip.csr 112881 UNSD_15_9 15 9 0x00 R M16 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_SET ns_noc_io_pcie_soc_ip.csr 112892 M16 1'b1: Mask interrupt for write channel 16 16 0x1 R/W M17 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_SET ns_noc_io_pcie_soc_ip.csr 112903 M17 1'b1: Mask interrupt for write channel 17 17 0x1 R/W M18 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_SET ns_noc_io_pcie_soc_ip.csr 112914 M18 1'b1: Mask interrupt for write channel 18 18 0x1 R/W M19 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_SET ns_noc_io_pcie_soc_ip.csr 112925 M19 1'b1: Mask interrupt for write channel 19 19 0x1 R/W M20 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_SET ns_noc_io_pcie_soc_ip.csr 112936 M20 1'b1: Mask interrupt for write channel 20 20 0x0 R/W M21 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_SET ns_noc_io_pcie_soc_ip.csr 112947 M21 1'b1: Mask interrupt for write channel 21 21 0x0 R/W M22 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_SET ns_noc_io_pcie_soc_ip.csr 112958 M22 1'b1: Mask interrupt for write channel 22 22 0x1 R/W M23 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_SET ns_noc_io_pcie_soc_ip.csr 112969 M23 1'b1: Mask interrupt for write channel 23 23 0x0 R/W M24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_SET ns_noc_io_pcie_soc_ip.csr 112980 M24 1'b1: Mask interrupt for write channel 24 24 0x0 R/W UNSD_31_25 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 112991 UNSD_31_25 31 25 0x00 R M32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_SET ns_noc_io_pcie_soc_ip.csr 113002 M32 1'b1: Counter 0 overflow interrupt mask 32 32 0x1 R/W M33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_SET ns_noc_io_pcie_soc_ip.csr 113013 M33 1'b1: Counter 1 overflow interrupt mask 33 33 0x1 R/W M34 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_SET ns_noc_io_pcie_soc_ip.csr 113024 M34 1'b1: Mask interrupt on traffic to PG layer 34 34 0x1 R/W M35 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_SET ns_noc_io_pcie_soc_ip.csr 113035 M35 1'b1: Mask interrupt on csr parity errors 35 35 0x0 R/W UNSD_39_36 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_SET ns_noc_io_pcie_soc_ip.csr 113046 UNSD_39_36 39 36 0x0 R M40 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_SET ns_noc_io_pcie_soc_ip.csr 113058 M40 1'b1: Mask interrupt for SIB portcheck error (SIB mode only) 40 40 0x0 R/W M41 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_SET ns_noc_io_pcie_soc_ip.csr 113069 M41 1'b1: AR Parity Intr Mask 41 41 0x1 R/W M42 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_SET ns_noc_io_pcie_soc_ip.csr 113080 M42 1'b1: ARADDR Parity Intr Mask 42 42 0x1 R/W M43 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_SET ns_noc_io_pcie_soc_ip.csr 113091 M43 1'b1: AW Parity Intr Mask 43 43 0x1 R/W M44 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_SET ns_noc_io_pcie_soc_ip.csr 113102 M44 1'b1: AWADDR Parity Intr Mask 44 44 0x1 R/W M45 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_SET ns_noc_io_pcie_soc_ip.csr 113113 M45 1'b1: WDATA Parity Intr Mask 45 45 0x1 R/W M46 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_SET ns_noc_io_pcie_soc_ip.csr 113124 M46 1'b1: CDDATA Parity Intr Mask 46 46 0x1 R/W E47 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_SET ns_noc_io_pcie_soc_ip.csr 113136 E47 1'b1: Ridtbl Parity Intr Mask 47 47 0x0 R E48 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_SET ns_noc_io_pcie_soc_ip.csr 113148 E48 1'b1: Widtbl Parity Intr Mask 48 48 0x0 R E49 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_SET ns_noc_io_pcie_soc_ip.csr 113160 E49 1'b1: Read Reorder Buffer Parity Intr Mask 49 49 0x0 R E50 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_SET ns_noc_io_pcie_soc_ip.csr 113172 E50 1'b1: Write Reorder Buffer Parity Intr Mask 50 50 0x0 R E51 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_SET ns_noc_io_pcie_soc_ip.csr 113184 E51 1'b1: Rx Fifo Parity Intr Mask 51 51 0x0 R E52 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_SET ns_noc_io_pcie_soc_ip.csr 113196 E52 1'b1: Ack Channel Wack Fifo Parity Intr Mask 52 52 0x0 R E53 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_SET ns_noc_io_pcie_soc_ip.csr 113208 E53 1'b1: Ack Channel Rack Fifo Parity Intr Mask 53 53 0x0 R E54 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_SET ns_noc_io_pcie_soc_ip.csr 113220 E54 1'b1: CRCD Channel Crid Fifo Parity Intr Mask 54 54 0x0 R E55 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_SET ns_noc_io_pcie_soc_ip.csr 113232 E55 1'b1: R Channel Cpkt Fifo Parity Intr Mask 55 55 0x0 R UNSD_63_56 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_SET ns_noc_io_pcie_soc_ip.csr 113243 UNSD_63_56 63 56 0x00 R register pcie_noc.bridge_p0_spio_m_5_7_am_caddr bridge_p0_spio_m_5_7_am_caddr PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113266 p0_spio_m register am_caddr 0x37F00 R/W 0xffffffffffffffff Pcie_noc_bridge_p0_spio_m_5_7_am_caddr This register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering. false false false false CAPTURE_ADDR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_SET ns_noc_io_pcie_soc_ip.csr 113265 CAPTURE_ADDR Capture address 63 0 0xffffffffffffffff R/W register pcie_noc.bridge_p0_spio_m_5_7_am_caddrmsk bridge_p0_spio_m_5_7_am_caddrmsk PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113289 p0_spio_m register am_caddrmsk 0x37F08 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_caddrmsk If command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison. false false false false CAPTURE_ADDR_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_SET ns_noc_io_pcie_soc_ip.csr 113288 CAPTURE_ADDR_MASK Capture address mask 63 0 0x0000000000000000 R/W register pcie_noc.bridge_p0_spio_m_5_7_am_ccmd0 bridge_p0_spio_m_5_7_am_ccmd0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113479 p0_spio_m register am_ccmd0 0x37F10 R/W 0x0000000003fff33f Pcie_noc_bridge_p0_spio_m_5_7_am_ccmd0 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 113311 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 113322 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 113333 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_SET ns_noc_io_pcie_soc_ip.csr 113344 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 113355 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 113366 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_SET ns_noc_io_pcie_soc_ip.csr 113377 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_SET ns_noc_io_pcie_soc_ip.csr 113388 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_SET ns_noc_io_pcie_soc_ip.csr 113399 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_SET ns_noc_io_pcie_soc_ip.csr 113410 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_SET ns_noc_io_pcie_soc_ip.csr 113421 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 113432 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_SET ns_noc_io_pcie_soc_ip.csr 113444 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 113455 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_SET ns_noc_io_pcie_soc_ip.csr 113467 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 113478 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk0 bridge_p0_spio_m_5_7_am_ccmdmsk0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113623 p0_spio_m register am_ccmdmsk0 0x37F18 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_ccmdmsk0 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 113501 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 113512 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 113523 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_SET ns_noc_io_pcie_soc_ip.csr 113534 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 113545 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_SET ns_noc_io_pcie_soc_ip.csr 113556 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_SET ns_noc_io_pcie_soc_ip.csr 113567 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_SET ns_noc_io_pcie_soc_ip.csr 113578 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_SET ns_noc_io_pcie_soc_ip.csr 113589 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_SET ns_noc_io_pcie_soc_ip.csr 113600 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_SET ns_noc_io_pcie_soc_ip.csr 113611 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 113622 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_cntr0 bridge_p0_spio_m_5_7_am_cntr0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113658 p0_spio_m register am_cntr0 0x37F20 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_cntr0 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 113646 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 113657 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_latnum0 bridge_p0_spio_m_5_7_am_latnum0 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113697 p0_spio_m register am_latnum0 0x37F28 R/W 0x0000000000000007 Pcie_noc_bridge_p0_spio_m_5_7_am_latnum0 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_SET ns_noc_io_pcie_soc_ip.csr 113685 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 113696 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_ccmd1 bridge_p0_spio_m_5_7_am_ccmd1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 113887 p0_spio_m register am_ccmd1 0x37F30 R/W 0x0000000003fff33f Pcie_noc_bridge_p0_spio_m_5_7_am_ccmd1 Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands. false false false false SNOOP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 113719 SNOOP Snoop 3 0 0xf R/W DOMAIN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 113730 DOMAIN Domain 5 4 0x3 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 113741 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_SET ns_noc_io_pcie_soc_ip.csr 113752 BAR Bar 9 8 0x3 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 113763 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 113774 CACHE Cache 15 12 0xf R/W QOS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_SET ns_noc_io_pcie_soc_ip.csr 113785 QOS QoS 19 16 0xf R/W PROT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_SET ns_noc_io_pcie_soc_ip.csr 113796 PROT Prot 22 20 0x7 R/W LOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_SET ns_noc_io_pcie_soc_ip.csr 113807 LOC 1'b1: Lock 23 23 0x1 R/W RDY PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_SET ns_noc_io_pcie_soc_ip.csr 113818 RDY 1'b1: Ready 24 24 0x1 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_SET ns_noc_io_pcie_soc_ip.csr 113829 VAL 1'b1: Valid 25 25 0x1 R/W UNSD_27_26 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_SET ns_noc_io_pcie_soc_ip.csr 113840 UNSD_27_26 27 26 0x0 R INTFID PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_SET ns_noc_io_pcie_soc_ip.csr 113852 INTFID 001: AW (can count captured event or response latency) 000: AR (can count captured event or response latency) 30 28 0x0 R/W UNSD_31_31 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_SET ns_noc_io_pcie_soc_ip.csr 113863 UNSD_31_31 31 31 0x0 R TYP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_SET ns_noc_io_pcie_soc_ip.csr 113875 TYP 1'b1: Count response latency of captured command 1'b0: Count captured command 32 32 0x0 R/W UNSD_63_33 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_SET ns_noc_io_pcie_soc_ip.csr 113886 UNSD_63_33 63 33 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk1 bridge_p0_spio_m_5_7_am_ccmdmsk1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114031 p0_spio_m register am_ccmdmsk1 0x37F38 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_ccmdmsk1 If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters. false false false false SNOOP PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_SET ns_noc_io_pcie_soc_ip.csr 113909 SNOOP Snoop 3 0 0x0 R/W DOMAIN PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_SET ns_noc_io_pcie_soc_ip.csr 113920 DOMAIN Domain 5 4 0x0 R/W UNSD_7_6 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_SET ns_noc_io_pcie_soc_ip.csr 113931 UNSD_7_6 7 6 0x0 R BAR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_SET ns_noc_io_pcie_soc_ip.csr 113942 BAR Bar 9 8 0x0 R/W UNSD_11_10 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_SET ns_noc_io_pcie_soc_ip.csr 113953 UNSD_11_10 11 10 0x0 R CACHE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_SET ns_noc_io_pcie_soc_ip.csr 113964 CACHE Cache 15 12 0x0 R/W QOS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_SET ns_noc_io_pcie_soc_ip.csr 113975 QOS QoS 19 16 0x0 R/W PROT PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_SET ns_noc_io_pcie_soc_ip.csr 113986 PROT Prot 22 20 0x0 R/W LOC PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_SET ns_noc_io_pcie_soc_ip.csr 113997 LOC 1'b1: Lock 23 23 0x0 R/W RDY PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_SET ns_noc_io_pcie_soc_ip.csr 114008 RDY 1'b1: Ready 24 24 0x0 R/W VAL PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_SET ns_noc_io_pcie_soc_ip.csr 114019 VAL 1'b1: Valid 25 25 0x0 R/W UNSD_63_26 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_SET ns_noc_io_pcie_soc_ip.csr 114030 UNSD_63_26 63 26 0x0000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_cntr1 bridge_p0_spio_m_5_7_am_cntr1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114066 p0_spio_m register am_cntr1 0x37F40 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_cntr1 32-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured. false false false false CNTR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 114054 CNTR Counter 31 0 0x00000000 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 114065 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_latnum1 bridge_p0_spio_m_5_7_am_latnum1 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114105 p0_spio_m register am_latnum1 0x37F48 R/W 0x0000000000000007 Pcie_noc_bridge_p0_spio_m_5_7_am_latnum1 This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using: Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0 There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set. false false false false CNTR PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_SET ns_noc_io_pcie_soc_ip.csr 114093 CNTR Counter 31 0 0x00000007 R/W UNSD_63_32 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_SET ns_noc_io_pcie_soc_ip.csr 114104 UNSD_63_32 63 32 0x00000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_arovrd bridge_p0_spio_m_5_7_am_arovrd PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114218 p0_spio_m register am_arovrd 0x37F60 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_arovrd AR override. false false false false arcache_val PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 114123 arcache_val Value to override incoming ARCACHE 3 0 0x0 R/W arcache_enb PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 114136 arcache_enb 1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged. 7 4 0x0 R/W arprot_val PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 114147 arprot_val Value to override incoming ARPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 114158 UNSD_11_11 11 11 0x0 R arprot_enb PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 114171 arprot_enb 1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 114182 UNSD_15_15 15 15 0x0 R arqos_val PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 114193 arqos_val Value to override incoming ARQOS 19 16 0x0 R/W arqos_enb PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 114206 arqos_enb 1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 114217 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.bridge_p0_spio_m_5_7_am_awovrd bridge_p0_spio_m_5_7_am_awovrd PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_BYTE_ADDRESS PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_OFFSET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114331 p0_spio_m register am_awovrd 0x37F68 R/W 0x0000000000000000 Pcie_noc_bridge_p0_spio_m_5_7_am_awovrd AW override. false false false false awcache_val PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_SET ns_noc_io_pcie_soc_ip.csr 114236 awcache_val Value to override incoming AWCACHE 3 0 0x0 R/W awcache_enb PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_SET ns_noc_io_pcie_soc_ip.csr 114249 awcache_enb 1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged. 7 4 0x0 R/W awprot_val PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_SET ns_noc_io_pcie_soc_ip.csr 114260 awprot_val Value to override incoming AWPROT 10 8 0x0 R/W UNSD_11_11 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_SET ns_noc_io_pcie_soc_ip.csr 114271 UNSD_11_11 11 11 0x0 R awprot_enb PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_SET ns_noc_io_pcie_soc_ip.csr 114284 awprot_enb 1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged. 14 12 0x0 R/W UNSD_15_15 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_SET ns_noc_io_pcie_soc_ip.csr 114295 UNSD_15_15 15 15 0x0 R awqos_val PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_SET ns_noc_io_pcie_soc_ip.csr 114306 awqos_val Value to override incoming AWQOS 19 16 0x0 R/W awqos_enb PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_SET ns_noc_io_pcie_soc_ip.csr 114319 awqos_enb 1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged. 23 20 0x0 R/W UNSD_63_24 PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_WIDTH PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_MSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_LSB PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_RANGE PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_RESET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_FIELD_MASK PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_GET PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_SET ns_noc_io_pcie_soc_ip.csr 114330 UNSD_63_24 63 24 0x0000000000 R register pcie_noc.router_0_5_5_rivcs_h router_0_5_5_rivcs_h PCIE_NOC_ROUTER_0_5_5_RIVCS_H_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114660 R0_5 register rivcs_h 0x38000 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 114356 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_SET ns_noc_io_pcie_soc_ip.csr 114370 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_SET ns_noc_io_pcie_soc_ip.csr 114386 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_SET ns_noc_io_pcie_soc_ip.csr 114400 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_SET ns_noc_io_pcie_soc_ip.csr 114411 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_SET ns_noc_io_pcie_soc_ip.csr 114422 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 114435 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_SET ns_noc_io_pcie_soc_ip.csr 114449 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_SET ns_noc_io_pcie_soc_ip.csr 114465 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_SET ns_noc_io_pcie_soc_ip.csr 114479 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_SET ns_noc_io_pcie_soc_ip.csr 114490 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_SET ns_noc_io_pcie_soc_ip.csr 114501 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 114514 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_SET ns_noc_io_pcie_soc_ip.csr 114528 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_SET ns_noc_io_pcie_soc_ip.csr 114544 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_SET ns_noc_io_pcie_soc_ip.csr 114558 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_SET ns_noc_io_pcie_soc_ip.csr 114569 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_SET ns_noc_io_pcie_soc_ip.csr 114580 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 114593 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_SET ns_noc_io_pcie_soc_ip.csr 114607 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_SET ns_noc_io_pcie_soc_ip.csr 114623 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_SET ns_noc_io_pcie_soc_ip.csr 114637 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_SET ns_noc_io_pcie_soc_ip.csr 114648 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_SET ns_noc_io_pcie_soc_ip.csr 114659 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rivcs_e router_0_5_5_rivcs_e PCIE_NOC_ROUTER_0_5_5_RIVCS_E_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 114989 R0_5 register rivcs_e 0x38008 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 114685 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_SET ns_noc_io_pcie_soc_ip.csr 114699 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_SET ns_noc_io_pcie_soc_ip.csr 114715 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_SET ns_noc_io_pcie_soc_ip.csr 114729 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_SET ns_noc_io_pcie_soc_ip.csr 114740 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_SET ns_noc_io_pcie_soc_ip.csr 114751 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 114764 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_SET ns_noc_io_pcie_soc_ip.csr 114778 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_SET ns_noc_io_pcie_soc_ip.csr 114794 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_SET ns_noc_io_pcie_soc_ip.csr 114808 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_SET ns_noc_io_pcie_soc_ip.csr 114819 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_SET ns_noc_io_pcie_soc_ip.csr 114830 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 114843 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_SET ns_noc_io_pcie_soc_ip.csr 114857 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_SET ns_noc_io_pcie_soc_ip.csr 114873 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_SET ns_noc_io_pcie_soc_ip.csr 114887 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_SET ns_noc_io_pcie_soc_ip.csr 114898 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_SET ns_noc_io_pcie_soc_ip.csr 114909 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 114922 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_SET ns_noc_io_pcie_soc_ip.csr 114936 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_SET ns_noc_io_pcie_soc_ip.csr 114952 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_SET ns_noc_io_pcie_soc_ip.csr 114966 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_SET ns_noc_io_pcie_soc_ip.csr 114977 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_SET ns_noc_io_pcie_soc_ip.csr 114988 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rivcs_s router_0_5_5_rivcs_s PCIE_NOC_ROUTER_0_5_5_RIVCS_S_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 115318 R0_5 register rivcs_s 0x38010 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_s This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 115014 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_SET ns_noc_io_pcie_soc_ip.csr 115028 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_SET ns_noc_io_pcie_soc_ip.csr 115044 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_SET ns_noc_io_pcie_soc_ip.csr 115058 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_SET ns_noc_io_pcie_soc_ip.csr 115069 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_SET ns_noc_io_pcie_soc_ip.csr 115080 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 115093 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_SET ns_noc_io_pcie_soc_ip.csr 115107 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_SET ns_noc_io_pcie_soc_ip.csr 115123 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_SET ns_noc_io_pcie_soc_ip.csr 115137 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_SET ns_noc_io_pcie_soc_ip.csr 115148 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_SET ns_noc_io_pcie_soc_ip.csr 115159 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 115172 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_SET ns_noc_io_pcie_soc_ip.csr 115186 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_SET ns_noc_io_pcie_soc_ip.csr 115202 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_SET ns_noc_io_pcie_soc_ip.csr 115216 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_SET ns_noc_io_pcie_soc_ip.csr 115227 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_SET ns_noc_io_pcie_soc_ip.csr 115238 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 115251 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_SET ns_noc_io_pcie_soc_ip.csr 115265 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_SET ns_noc_io_pcie_soc_ip.csr 115281 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_SET ns_noc_io_pcie_soc_ip.csr 115295 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_SET ns_noc_io_pcie_soc_ip.csr 115306 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_SET ns_noc_io_pcie_soc_ip.csr 115317 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rivcs_w router_0_5_5_rivcs_w PCIE_NOC_ROUTER_0_5_5_RIVCS_W_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 115647 R0_5 register rivcs_w 0x38018 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 115343 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_SET ns_noc_io_pcie_soc_ip.csr 115357 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_SET ns_noc_io_pcie_soc_ip.csr 115373 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_SET ns_noc_io_pcie_soc_ip.csr 115387 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_SET ns_noc_io_pcie_soc_ip.csr 115398 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_SET ns_noc_io_pcie_soc_ip.csr 115409 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 115422 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_SET ns_noc_io_pcie_soc_ip.csr 115436 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_SET ns_noc_io_pcie_soc_ip.csr 115452 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_SET ns_noc_io_pcie_soc_ip.csr 115466 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_SET ns_noc_io_pcie_soc_ip.csr 115477 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_SET ns_noc_io_pcie_soc_ip.csr 115488 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 115501 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_SET ns_noc_io_pcie_soc_ip.csr 115515 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_SET ns_noc_io_pcie_soc_ip.csr 115531 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_SET ns_noc_io_pcie_soc_ip.csr 115545 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_SET ns_noc_io_pcie_soc_ip.csr 115556 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_SET ns_noc_io_pcie_soc_ip.csr 115567 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 115580 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_SET ns_noc_io_pcie_soc_ip.csr 115594 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_SET ns_noc_io_pcie_soc_ip.csr 115610 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_SET ns_noc_io_pcie_soc_ip.csr 115624 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_SET ns_noc_io_pcie_soc_ip.csr 115635 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_SET ns_noc_io_pcie_soc_ip.csr 115646 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rivcs_i router_0_5_5_rivcs_i PCIE_NOC_ROUTER_0_5_5_RIVCS_I_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 115976 R0_5 register rivcs_i 0x38028 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 115672 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_SET ns_noc_io_pcie_soc_ip.csr 115686 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_SET ns_noc_io_pcie_soc_ip.csr 115702 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_SET ns_noc_io_pcie_soc_ip.csr 115716 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_SET ns_noc_io_pcie_soc_ip.csr 115727 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_SET ns_noc_io_pcie_soc_ip.csr 115738 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 115751 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_SET ns_noc_io_pcie_soc_ip.csr 115765 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_SET ns_noc_io_pcie_soc_ip.csr 115781 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_SET ns_noc_io_pcie_soc_ip.csr 115795 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_SET ns_noc_io_pcie_soc_ip.csr 115806 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_SET ns_noc_io_pcie_soc_ip.csr 115817 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 115830 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_SET ns_noc_io_pcie_soc_ip.csr 115844 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_SET ns_noc_io_pcie_soc_ip.csr 115860 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_SET ns_noc_io_pcie_soc_ip.csr 115874 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_SET ns_noc_io_pcie_soc_ip.csr 115885 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_SET ns_noc_io_pcie_soc_ip.csr 115896 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 115909 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_SET ns_noc_io_pcie_soc_ip.csr 115923 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_SET ns_noc_io_pcie_soc_ip.csr 115939 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_SET ns_noc_io_pcie_soc_ip.csr 115953 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_SET ns_noc_io_pcie_soc_ip.csr 115964 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_SET ns_noc_io_pcie_soc_ip.csr 115975 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rivcs_j router_0_5_5_rivcs_j PCIE_NOC_ROUTER_0_5_5_RIVCS_J_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 116305 R0_5 register rivcs_j 0x38030 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 116001 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_SET ns_noc_io_pcie_soc_ip.csr 116015 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_SET ns_noc_io_pcie_soc_ip.csr 116031 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_SET ns_noc_io_pcie_soc_ip.csr 116045 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_SET ns_noc_io_pcie_soc_ip.csr 116056 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_SET ns_noc_io_pcie_soc_ip.csr 116067 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 116080 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_SET ns_noc_io_pcie_soc_ip.csr 116094 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_SET ns_noc_io_pcie_soc_ip.csr 116110 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_SET ns_noc_io_pcie_soc_ip.csr 116124 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_SET ns_noc_io_pcie_soc_ip.csr 116135 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_SET ns_noc_io_pcie_soc_ip.csr 116146 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 116159 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_SET ns_noc_io_pcie_soc_ip.csr 116173 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_SET ns_noc_io_pcie_soc_ip.csr 116189 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_SET ns_noc_io_pcie_soc_ip.csr 116203 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_SET ns_noc_io_pcie_soc_ip.csr 116214 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_SET ns_noc_io_pcie_soc_ip.csr 116225 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 116238 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_SET ns_noc_io_pcie_soc_ip.csr 116252 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_SET ns_noc_io_pcie_soc_ip.csr 116268 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_SET ns_noc_io_pcie_soc_ip.csr 116282 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_SET ns_noc_io_pcie_soc_ip.csr 116293 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_SET ns_noc_io_pcie_soc_ip.csr 116304 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rivcs_k router_0_5_5_rivcs_k PCIE_NOC_ROUTER_0_5_5_RIVCS_K_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OFFSET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 116634 R0_5 register rivcs_k 0x38038 R 0x00000000 Pcie_noc_router_0_5_5_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 116330 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_SET ns_noc_io_pcie_soc_ip.csr 116344 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_SET ns_noc_io_pcie_soc_ip.csr 116360 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_SET ns_noc_io_pcie_soc_ip.csr 116374 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_SET ns_noc_io_pcie_soc_ip.csr 116385 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_SET ns_noc_io_pcie_soc_ip.csr 116396 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 116409 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_SET ns_noc_io_pcie_soc_ip.csr 116423 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_SET ns_noc_io_pcie_soc_ip.csr 116439 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_SET ns_noc_io_pcie_soc_ip.csr 116453 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_SET ns_noc_io_pcie_soc_ip.csr 116464 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_SET ns_noc_io_pcie_soc_ip.csr 116475 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 116488 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_SET ns_noc_io_pcie_soc_ip.csr 116502 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_SET ns_noc_io_pcie_soc_ip.csr 116518 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_SET ns_noc_io_pcie_soc_ip.csr 116532 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_SET ns_noc_io_pcie_soc_ip.csr 116543 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_SET ns_noc_io_pcie_soc_ip.csr 116554 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 116567 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_SET ns_noc_io_pcie_soc_ip.csr 116581 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_SET ns_noc_io_pcie_soc_ip.csr 116597 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_SET ns_noc_io_pcie_soc_ip.csr 116611 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_SET ns_noc_io_pcie_soc_ip.csr 116622 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_MSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_LSB PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_RANGE PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_RESET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_GET PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_SET ns_noc_io_pcie_soc_ip.csr 116633 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_5_5_rovcs_h router_0_5_5_rovcs_h PCIE_NOC_ROUTER_0_5_5_ROVCS_H_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_H_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 116895 R0_5 register rovcs_h 0x38040 R 0x00000101 Pcie_noc_router_0_5_5_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_SET ns_noc_io_pcie_soc_ip.csr 116658 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_SET ns_noc_io_pcie_soc_ip.csr 116672 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_SET ns_noc_io_pcie_soc_ip.csr 116687 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 116698 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 116708 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_SET ns_noc_io_pcie_soc_ip.csr 116720 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_SET ns_noc_io_pcie_soc_ip.csr 116734 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_SET ns_noc_io_pcie_soc_ip.csr 116749 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 116760 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 116770 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_SET ns_noc_io_pcie_soc_ip.csr 116782 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_SET ns_noc_io_pcie_soc_ip.csr 116796 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_SET ns_noc_io_pcie_soc_ip.csr 116811 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 116822 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 116832 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_SET ns_noc_io_pcie_soc_ip.csr 116844 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_SET ns_noc_io_pcie_soc_ip.csr 116858 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_SET ns_noc_io_pcie_soc_ip.csr 116873 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 116884 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 116894 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_rovcs_e router_0_5_5_rovcs_e PCIE_NOC_ROUTER_0_5_5_ROVCS_E_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_E_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 117156 R0_5 register rovcs_e 0x38048 R 0x00000001 Pcie_noc_router_0_5_5_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_SET ns_noc_io_pcie_soc_ip.csr 116919 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_SET ns_noc_io_pcie_soc_ip.csr 116933 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_SET ns_noc_io_pcie_soc_ip.csr 116948 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 116959 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 116969 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_SET ns_noc_io_pcie_soc_ip.csr 116981 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_SET ns_noc_io_pcie_soc_ip.csr 116995 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_SET ns_noc_io_pcie_soc_ip.csr 117010 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 117021 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 117031 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_SET ns_noc_io_pcie_soc_ip.csr 117043 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_SET ns_noc_io_pcie_soc_ip.csr 117057 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_SET ns_noc_io_pcie_soc_ip.csr 117072 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 117083 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 117093 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_SET ns_noc_io_pcie_soc_ip.csr 117105 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_SET ns_noc_io_pcie_soc_ip.csr 117119 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_SET ns_noc_io_pcie_soc_ip.csr 117134 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 117145 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 117155 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_rovcs_s router_0_5_5_rovcs_s PCIE_NOC_ROUTER_0_5_5_ROVCS_S_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_S_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 117417 R0_5 register rovcs_s 0x38050 R 0x00000001 Pcie_noc_router_0_5_5_rovcs_s This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_SET ns_noc_io_pcie_soc_ip.csr 117180 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_SET ns_noc_io_pcie_soc_ip.csr 117194 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_SET ns_noc_io_pcie_soc_ip.csr 117209 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 117220 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 117230 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_SET ns_noc_io_pcie_soc_ip.csr 117242 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_SET ns_noc_io_pcie_soc_ip.csr 117256 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_SET ns_noc_io_pcie_soc_ip.csr 117271 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 117282 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 117292 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_SET ns_noc_io_pcie_soc_ip.csr 117304 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_SET ns_noc_io_pcie_soc_ip.csr 117318 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_SET ns_noc_io_pcie_soc_ip.csr 117333 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 117344 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 117354 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_SET ns_noc_io_pcie_soc_ip.csr 117366 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_SET ns_noc_io_pcie_soc_ip.csr 117380 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_SET ns_noc_io_pcie_soc_ip.csr 117395 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 117406 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 117416 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_rovcs_w router_0_5_5_rovcs_w PCIE_NOC_ROUTER_0_5_5_ROVCS_W_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_W_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 117678 R0_5 register rovcs_w 0x38058 R 0x00000101 Pcie_noc_router_0_5_5_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_SET ns_noc_io_pcie_soc_ip.csr 117441 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_SET ns_noc_io_pcie_soc_ip.csr 117455 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_SET ns_noc_io_pcie_soc_ip.csr 117470 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 117481 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 117491 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_SET ns_noc_io_pcie_soc_ip.csr 117503 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_SET ns_noc_io_pcie_soc_ip.csr 117517 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_SET ns_noc_io_pcie_soc_ip.csr 117532 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 117543 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 117553 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_SET ns_noc_io_pcie_soc_ip.csr 117565 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_SET ns_noc_io_pcie_soc_ip.csr 117579 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_SET ns_noc_io_pcie_soc_ip.csr 117594 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 117605 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 117615 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_SET ns_noc_io_pcie_soc_ip.csr 117627 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_SET ns_noc_io_pcie_soc_ip.csr 117641 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_SET ns_noc_io_pcie_soc_ip.csr 117656 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 117667 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 117677 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_rovcs_i router_0_5_5_rovcs_i PCIE_NOC_ROUTER_0_5_5_ROVCS_I_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_I_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 117939 R0_5 register rovcs_i 0x38068 R 0x00000001 Pcie_noc_router_0_5_5_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_SET ns_noc_io_pcie_soc_ip.csr 117702 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_SET ns_noc_io_pcie_soc_ip.csr 117716 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_SET ns_noc_io_pcie_soc_ip.csr 117731 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 117742 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 117752 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_SET ns_noc_io_pcie_soc_ip.csr 117764 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_SET ns_noc_io_pcie_soc_ip.csr 117778 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_SET ns_noc_io_pcie_soc_ip.csr 117793 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 117804 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 117814 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_SET ns_noc_io_pcie_soc_ip.csr 117826 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_SET ns_noc_io_pcie_soc_ip.csr 117840 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_SET ns_noc_io_pcie_soc_ip.csr 117855 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 117866 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 117876 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_SET ns_noc_io_pcie_soc_ip.csr 117888 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_SET ns_noc_io_pcie_soc_ip.csr 117902 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_SET ns_noc_io_pcie_soc_ip.csr 117917 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 117928 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 117938 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_rovcs_j router_0_5_5_rovcs_j PCIE_NOC_ROUTER_0_5_5_ROVCS_J_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_J_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118200 R0_5 register rovcs_j 0x38070 R 0x00000001 Pcie_noc_router_0_5_5_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_SET ns_noc_io_pcie_soc_ip.csr 117963 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_SET ns_noc_io_pcie_soc_ip.csr 117977 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_SET ns_noc_io_pcie_soc_ip.csr 117992 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 118003 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 118013 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_SET ns_noc_io_pcie_soc_ip.csr 118025 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_SET ns_noc_io_pcie_soc_ip.csr 118039 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_SET ns_noc_io_pcie_soc_ip.csr 118054 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 118065 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 118075 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_SET ns_noc_io_pcie_soc_ip.csr 118087 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_SET ns_noc_io_pcie_soc_ip.csr 118101 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_SET ns_noc_io_pcie_soc_ip.csr 118116 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 118127 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 118137 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_SET ns_noc_io_pcie_soc_ip.csr 118149 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_SET ns_noc_io_pcie_soc_ip.csr 118163 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_SET ns_noc_io_pcie_soc_ip.csr 118178 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 118189 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 118199 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_rovcs_k router_0_5_5_rovcs_k PCIE_NOC_ROUTER_0_5_5_ROVCS_K_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROVCS_K_OFFSET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118461 R0_5 register rovcs_k 0x38078 R 0x00000101 Pcie_noc_router_0_5_5_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_SET ns_noc_io_pcie_soc_ip.csr 118224 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_SET ns_noc_io_pcie_soc_ip.csr 118238 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_SET ns_noc_io_pcie_soc_ip.csr 118253 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 118264 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 118274 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_SET ns_noc_io_pcie_soc_ip.csr 118286 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_SET ns_noc_io_pcie_soc_ip.csr 118300 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_SET ns_noc_io_pcie_soc_ip.csr 118315 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 118326 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 118336 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_SET ns_noc_io_pcie_soc_ip.csr 118348 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_SET ns_noc_io_pcie_soc_ip.csr 118362 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_SET ns_noc_io_pcie_soc_ip.csr 118377 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 118388 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 118398 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_SET ns_noc_io_pcie_soc_ip.csr 118410 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_SET ns_noc_io_pcie_soc_ip.csr 118424 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_SET ns_noc_io_pcie_soc_ip.csr 118439 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 118450 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_MSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_LSB PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_RANGE PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_RESET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_GET PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 118460 UNSD_3 31 28 0x0 R register pcie_noc.router_0_5_5_re router_0_5_5_re PCIE_NOC_ROUTER_0_5_5_RE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RE_OFFSET PCIE_NOC_ROUTER_0_5_5_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118635 R0_5 register re 0x38080 R/W 0x00000000 Pcie_noc_router_0_5_5_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_0_5_5_RE_OVFI_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_OVFI_MSB PCIE_NOC_ROUTER_0_5_5_RE_OVFI_LSB PCIE_NOC_ROUTER_0_5_5_RE_OVFI_RANGE PCIE_NOC_ROUTER_0_5_5_RE_OVFI_RESET PCIE_NOC_ROUTER_0_5_5_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_OVFI_GET PCIE_NOC_ROUTER_0_5_5_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 118487 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 118498 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_0_5_5_RE_OVFO_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_OVFO_MSB PCIE_NOC_ROUTER_0_5_5_RE_OVFO_LSB PCIE_NOC_ROUTER_0_5_5_RE_OVFO_RANGE PCIE_NOC_ROUTER_0_5_5_RE_OVFO_RESET PCIE_NOC_ROUTER_0_5_5_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_OVFO_GET PCIE_NOC_ROUTER_0_5_5_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 118512 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 118523 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_0_5_5_RE_PGE_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_PGE_MSB PCIE_NOC_ROUTER_0_5_5_RE_PGE_LSB PCIE_NOC_ROUTER_0_5_5_RE_PGE_RANGE PCIE_NOC_ROUTER_0_5_5_RE_PGE_RESET PCIE_NOC_ROUTER_0_5_5_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_PGE_GET PCIE_NOC_ROUTER_0_5_5_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 118535 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_0_5_5_RE_NLU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_NLU_MSB PCIE_NOC_ROUTER_0_5_5_RE_NLU_LSB PCIE_NOC_ROUTER_0_5_5_RE_NLU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_NLU_RESET PCIE_NOC_ROUTER_0_5_5_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_NLU_GET PCIE_NOC_ROUTER_0_5_5_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 118546 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_0_5_5_RE_ELU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_ELU_MSB PCIE_NOC_ROUTER_0_5_5_RE_ELU_LSB PCIE_NOC_ROUTER_0_5_5_RE_ELU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_ELU_RESET PCIE_NOC_ROUTER_0_5_5_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_ELU_GET PCIE_NOC_ROUTER_0_5_5_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 118557 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_0_5_5_RE_WLU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_WLU_MSB PCIE_NOC_ROUTER_0_5_5_RE_WLU_LSB PCIE_NOC_ROUTER_0_5_5_RE_WLU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_WLU_RESET PCIE_NOC_ROUTER_0_5_5_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_WLU_GET PCIE_NOC_ROUTER_0_5_5_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 118568 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_0_5_5_RE_SLU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_SLU_MSB PCIE_NOC_ROUTER_0_5_5_RE_SLU_LSB PCIE_NOC_ROUTER_0_5_5_RE_SLU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_SLU_RESET PCIE_NOC_ROUTER_0_5_5_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_SLU_GET PCIE_NOC_ROUTER_0_5_5_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 118579 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_0_5_5_RE_HLU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_HLU_MSB PCIE_NOC_ROUTER_0_5_5_RE_HLU_LSB PCIE_NOC_ROUTER_0_5_5_RE_HLU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_HLU_RESET PCIE_NOC_ROUTER_0_5_5_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_HLU_GET PCIE_NOC_ROUTER_0_5_5_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 118590 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_0_5_5_RE_ILU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_ILU_MSB PCIE_NOC_ROUTER_0_5_5_RE_ILU_LSB PCIE_NOC_ROUTER_0_5_5_RE_ILU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_ILU_RESET PCIE_NOC_ROUTER_0_5_5_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_ILU_GET PCIE_NOC_ROUTER_0_5_5_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 118601 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_0_5_5_RE_JLU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_JLU_MSB PCIE_NOC_ROUTER_0_5_5_RE_JLU_LSB PCIE_NOC_ROUTER_0_5_5_RE_JLU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_JLU_RESET PCIE_NOC_ROUTER_0_5_5_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_JLU_GET PCIE_NOC_ROUTER_0_5_5_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 118612 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_0_5_5_RE_KLU_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_KLU_MSB PCIE_NOC_ROUTER_0_5_5_RE_KLU_LSB PCIE_NOC_ROUTER_0_5_5_RE_KLU_RANGE PCIE_NOC_ROUTER_0_5_5_RE_KLU_RESET PCIE_NOC_ROUTER_0_5_5_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_KLU_GET PCIE_NOC_ROUTER_0_5_5_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 118623 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 118634 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_0_5_5_rem router_0_5_5_rem PCIE_NOC_ROUTER_0_5_5_REM_ADDRESS PCIE_NOC_ROUTER_0_5_5_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_REM_OFFSET PCIE_NOC_ROUTER_0_5_5_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118808 R0_5 register rem 0x38088 R/W 0x0001fe00 Pcie_noc_router_0_5_5_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_MSB PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_LSB PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_RANGE PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_RESET PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_GET PCIE_NOC_ROUTER_0_5_5_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 118661 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 118672 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_MSB PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_LSB PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_RANGE PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_RESET PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_GET PCIE_NOC_ROUTER_0_5_5_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 118686 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 118697 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_0_5_5_REM_PGM_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_PGM_MSB PCIE_NOC_ROUTER_0_5_5_REM_PGM_LSB PCIE_NOC_ROUTER_0_5_5_REM_PGM_RANGE PCIE_NOC_ROUTER_0_5_5_REM_PGM_RESET PCIE_NOC_ROUTER_0_5_5_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_PGM_GET PCIE_NOC_ROUTER_0_5_5_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 118708 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_0_5_5_REM_MN_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MN_MSB PCIE_NOC_ROUTER_0_5_5_REM_MN_LSB PCIE_NOC_ROUTER_0_5_5_REM_MN_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MN_RESET PCIE_NOC_ROUTER_0_5_5_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MN_GET PCIE_NOC_ROUTER_0_5_5_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 118719 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_0_5_5_REM_ME_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_ME_MSB PCIE_NOC_ROUTER_0_5_5_REM_ME_LSB PCIE_NOC_ROUTER_0_5_5_REM_ME_RANGE PCIE_NOC_ROUTER_0_5_5_REM_ME_RESET PCIE_NOC_ROUTER_0_5_5_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_ME_GET PCIE_NOC_ROUTER_0_5_5_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 118730 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_0_5_5_REM_MW_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MW_MSB PCIE_NOC_ROUTER_0_5_5_REM_MW_LSB PCIE_NOC_ROUTER_0_5_5_REM_MW_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MW_RESET PCIE_NOC_ROUTER_0_5_5_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MW_GET PCIE_NOC_ROUTER_0_5_5_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 118741 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_0_5_5_REM_MS_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MS_MSB PCIE_NOC_ROUTER_0_5_5_REM_MS_LSB PCIE_NOC_ROUTER_0_5_5_REM_MS_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MS_RESET PCIE_NOC_ROUTER_0_5_5_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MS_GET PCIE_NOC_ROUTER_0_5_5_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 118752 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_0_5_5_REM_MH_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MH_MSB PCIE_NOC_ROUTER_0_5_5_REM_MH_LSB PCIE_NOC_ROUTER_0_5_5_REM_MH_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MH_RESET PCIE_NOC_ROUTER_0_5_5_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MH_GET PCIE_NOC_ROUTER_0_5_5_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 118763 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_0_5_5_REM_MI_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MI_MSB PCIE_NOC_ROUTER_0_5_5_REM_MI_LSB PCIE_NOC_ROUTER_0_5_5_REM_MI_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MI_RESET PCIE_NOC_ROUTER_0_5_5_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MI_GET PCIE_NOC_ROUTER_0_5_5_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 118774 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_0_5_5_REM_MJ_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MJ_MSB PCIE_NOC_ROUTER_0_5_5_REM_MJ_LSB PCIE_NOC_ROUTER_0_5_5_REM_MJ_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MJ_RESET PCIE_NOC_ROUTER_0_5_5_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MJ_GET PCIE_NOC_ROUTER_0_5_5_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 118785 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_0_5_5_REM_MK_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_MK_MSB PCIE_NOC_ROUTER_0_5_5_REM_MK_LSB PCIE_NOC_ROUTER_0_5_5_REM_MK_RANGE PCIE_NOC_ROUTER_0_5_5_REM_MK_RESET PCIE_NOC_ROUTER_0_5_5_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_MK_GET PCIE_NOC_ROUTER_0_5_5_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 118796 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 118807 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_0_5_5_recc router_0_5_5_recc PCIE_NOC_ROUTER_0_5_5_RECC_ADDRESS PCIE_NOC_ROUTER_0_5_5_RECC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RECC_OFFSET PCIE_NOC_ROUTER_0_5_5_RECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118893 R0_5 register recc 0x38090 R/W 0x00000000 Pcie_noc_router_0_5_5_recc This register is used to select which hardware events will increment the event counter. false false false false IVC PCIE_NOC_ROUTER_0_5_5_RECC_IVC_WIDTH PCIE_NOC_ROUTER_0_5_5_RECC_IVC_MSB PCIE_NOC_ROUTER_0_5_5_RECC_IVC_LSB PCIE_NOC_ROUTER_0_5_5_RECC_IVC_RANGE PCIE_NOC_ROUTER_0_5_5_RECC_IVC_RESET PCIE_NOC_ROUTER_0_5_5_RECC_IVC_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RECC_IVC_GET PCIE_NOC_ROUTER_0_5_5_RECC_IVC_SET ns_noc_io_pcie_soc_ip.csr 118829 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_WIDTH PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_MSB PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_LSB PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_RANGE PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_RESET PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_GET PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_SET ns_noc_io_pcie_soc_ip.csr 118840 UNSD_3_2 3 2 0x0 R INP PCIE_NOC_ROUTER_0_5_5_RECC_INP_WIDTH PCIE_NOC_ROUTER_0_5_5_RECC_INP_MSB PCIE_NOC_ROUTER_0_5_5_RECC_INP_LSB PCIE_NOC_ROUTER_0_5_5_RECC_INP_RANGE PCIE_NOC_ROUTER_0_5_5_RECC_INP_RESET PCIE_NOC_ROUTER_0_5_5_RECC_INP_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RECC_INP_GET PCIE_NOC_ROUTER_0_5_5_RECC_INP_SET ns_noc_io_pcie_soc_ip.csr 118851 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_GET PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 118862 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_0_5_5_RECC_EVT_WIDTH PCIE_NOC_ROUTER_0_5_5_RECC_EVT_MSB PCIE_NOC_ROUTER_0_5_5_RECC_EVT_LSB PCIE_NOC_ROUTER_0_5_5_RECC_EVT_RANGE PCIE_NOC_ROUTER_0_5_5_RECC_EVT_RESET PCIE_NOC_ROUTER_0_5_5_RECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RECC_EVT_GET PCIE_NOC_ROUTER_0_5_5_RECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 118881 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_WIDTH PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_MSB PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_LSB PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_RANGE PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_RESET PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_GET PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_SET ns_noc_io_pcie_soc_ip.csr 118892 UNSD_31_10 31 10 0x000000 R register pcie_noc.router_0_5_5_rec router_0_5_5_rec PCIE_NOC_ROUTER_0_5_5_REC_ADDRESS PCIE_NOC_ROUTER_0_5_5_REC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_REC_OFFSET PCIE_NOC_ROUTER_0_5_5_REC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118918 R0_5 register rec 0x38098 R/W 0x00000000 Pcie_noc_router_0_5_5_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_GET PCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 118917 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_0_5_5_id router_0_5_5_id PCIE_NOC_ROUTER_0_5_5_ID_ADDRESS PCIE_NOC_ROUTER_0_5_5_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ID_OFFSET PCIE_NOC_ROUTER_0_5_5_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 118987 R0_5 register id 0x380A0 R 0x010000a0 Pcie_noc_router_0_5_5_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_0_5_5_ID_LAYER_WIDTH PCIE_NOC_ROUTER_0_5_5_ID_LAYER_MSB PCIE_NOC_ROUTER_0_5_5_ID_LAYER_LSB PCIE_NOC_ROUTER_0_5_5_ID_LAYER_RANGE PCIE_NOC_ROUTER_0_5_5_ID_LAYER_RESET PCIE_NOC_ROUTER_0_5_5_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ID_LAYER_GET PCIE_NOC_ROUTER_0_5_5_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 118943 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x00 R POS PCIE_NOC_ROUTER_0_5_5_ID_POS_WIDTH PCIE_NOC_ROUTER_0_5_5_ID_POS_MSB PCIE_NOC_ROUTER_0_5_5_ID_POS_LSB PCIE_NOC_ROUTER_0_5_5_ID_POS_RANGE PCIE_NOC_ROUTER_0_5_5_ID_POS_RESET PCIE_NOC_ROUTER_0_5_5_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ID_POS_GET PCIE_NOC_ROUTER_0_5_5_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 118954 POS 16-bit position ID of this router in the NoC 20 5 0x0005 R ZERO PCIE_NOC_ROUTER_0_5_5_ID_ZERO_WIDTH PCIE_NOC_ROUTER_0_5_5_ID_ZERO_MSB PCIE_NOC_ROUTER_0_5_5_ID_ZERO_LSB PCIE_NOC_ROUTER_0_5_5_ID_ZERO_RANGE PCIE_NOC_ROUTER_0_5_5_ID_ZERO_RESET PCIE_NOC_ROUTER_0_5_5_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ID_ZERO_GET PCIE_NOC_ROUTER_0_5_5_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 118965 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_0_5_5_ID_ONE_WIDTH PCIE_NOC_ROUTER_0_5_5_ID_ONE_MSB PCIE_NOC_ROUTER_0_5_5_ID_ONE_LSB PCIE_NOC_ROUTER_0_5_5_ID_ONE_RANGE PCIE_NOC_ROUTER_0_5_5_ID_ONE_RESET PCIE_NOC_ROUTER_0_5_5_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ID_ONE_GET PCIE_NOC_ROUTER_0_5_5_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 118976 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 118986 UNSD_31_25 31 25 0x00 R register pcie_noc.router_0_5_5_rcgc router_0_5_5_rcgc PCIE_NOC_ROUTER_0_5_5_RCGC_ADDRESS PCIE_NOC_ROUTER_0_5_5_RCGC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RCGC_OFFSET PCIE_NOC_ROUTER_0_5_5_RCGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 119013 R0_5 register rcgc 0x380A8 R/W 0x00000064 Pcie_noc_router_0_5_5_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_GET PCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 119012 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register pcie_noc.router_0_5_5_rcgo router_0_5_5_rcgo PCIE_NOC_ROUTER_0_5_5_RCGO_ADDRESS PCIE_NOC_ROUTER_0_5_5_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_RCGO_OFFSET PCIE_NOC_ROUTER_0_5_5_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 119052 R0_5 register rcgo 0x380B0 R/W 0x00000000 Pcie_noc_router_0_5_5_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_MSB PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_LSB PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_RANGE PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_RESET PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_GET PCIE_NOC_ROUTER_0_5_5_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 119040 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 119051 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_0_5_5_p1_rperr router_0_5_5_p1_rperr PCIE_NOC_ROUTER_0_5_5_P1_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P1_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P1_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 119339 R0_5 register p1_rperr 0x380C0 R/W 0x00000000 Pcie_noc_router_0_5_5_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 119095 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 119106 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 119117 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 119128 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 119139 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 119150 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 119161 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 119172 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 119184 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 119195 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 119206 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 119217 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 119229 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 119240 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 119252 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 119264 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 119277 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 119289 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 119301 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 119313 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 119326 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 119338 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p2_rperr router_0_5_5_p2_rperr PCIE_NOC_ROUTER_0_5_5_P2_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P2_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P2_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 119630 R0_5 register p2_rperr 0x380C8 R/W 0x00000000 Pcie_noc_router_0_5_5_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 119382 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 119393 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 119404 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 119415 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 119426 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 119437 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 119448 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 119459 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 119471 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 119482 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 119494 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 119506 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 119519 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 119531 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 119543 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 119555 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 119568 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 119580 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 119592 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 119604 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 119617 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 119629 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p3_rperr router_0_5_5_p3_rperr PCIE_NOC_ROUTER_0_5_5_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P3_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 119921 R0_5 register p3_rperr 0x380D0 R/W 0x00000000 Pcie_noc_router_0_5_5_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 119673 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 119684 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 119695 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 119706 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 119717 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 119728 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 119739 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 119750 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 119762 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 119773 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 119785 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 119797 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 119810 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 119822 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 119834 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 119846 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 119859 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 119871 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 119883 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 119895 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 119908 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 119920 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p4_rperr router_0_5_5_p4_rperr PCIE_NOC_ROUTER_0_5_5_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P4_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 120212 R0_5 register p4_rperr 0x380D8 R/W 0x00000000 Pcie_noc_router_0_5_5_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 119964 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 119975 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 119986 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 119997 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 120008 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 120019 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 120030 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 120041 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 120053 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 120064 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 120076 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 120088 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 120101 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 120113 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 120125 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 120137 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 120150 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 120162 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 120174 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 120186 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 120199 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 120211 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p5_rperr router_0_5_5_p5_rperr PCIE_NOC_ROUTER_0_5_5_P5_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P5_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P5_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 120503 R0_5 register p5_rperr 0x380E0 R/W 0x00000000 Pcie_noc_router_0_5_5_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 120255 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 120266 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 120277 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 120288 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 120299 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 120310 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 120321 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 120332 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 120344 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 120355 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 120367 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 120379 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 120392 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 120404 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 120416 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 120428 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 120441 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 120453 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 120465 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 120477 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 120490 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 120502 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p6_rperr router_0_5_5_p6_rperr PCIE_NOC_ROUTER_0_5_5_P6_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P6_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P6_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 120794 R0_5 register p6_rperr 0x380E8 R/W 0x00000000 Pcie_noc_router_0_5_5_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 120546 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 120557 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 120568 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 120579 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 120590 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 120601 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 120612 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 120623 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 120635 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 120646 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 120658 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 120670 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 120683 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 120695 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 120707 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 120719 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 120732 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 120744 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 120756 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 120768 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 120781 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 120793 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p7_rperr router_0_5_5_p7_rperr PCIE_NOC_ROUTER_0_5_5_P7_RPERR_ADDRESS PCIE_NOC_ROUTER_0_5_5_P7_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P7_RPERR_OFFSET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 121085 R0_5 register p7_rperr 0x380F0 R/W 0x00000000 Pcie_noc_router_0_5_5_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 120837 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 120848 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 120859 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 120870 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 120881 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 120892 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 120903 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 120914 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 120926 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 120937 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 120949 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 120961 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 120974 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 120986 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 120998 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 121010 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 121023 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 121035 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 121047 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 121059 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 121072 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 121084 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_5_5_p1_rperrm router_0_5_5_p1_rperrm PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 121343 R0_5 register p1_rperrm 0x38100 R/W 0x00000000 Pcie_noc_router_0_5_5_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 121107 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 121118 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 121129 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 121140 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 121151 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 121162 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 121173 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 121184 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 121196 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 121207 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 121218 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 121229 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 121241 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 121252 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 121263 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 121274 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 121286 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 121297 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 121308 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 121319 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 121331 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 121342 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_p2_rperrm router_0_5_5_p2_rperrm PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 121601 R0_5 register p2_rperrm 0x38108 R/W 0x00000000 Pcie_noc_router_0_5_5_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 121365 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 121376 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 121387 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 121398 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 121409 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 121420 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 121431 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 121442 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 121454 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 121465 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 121476 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 121487 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 121499 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 121510 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 121521 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 121532 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 121544 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 121555 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 121566 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 121577 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 121589 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 121600 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_p3_rperrm router_0_5_5_p3_rperrm PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 121859 R0_5 register p3_rperrm 0x38110 R/W 0x00000000 Pcie_noc_router_0_5_5_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 121623 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 121634 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 121645 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 121656 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 121667 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 121678 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 121689 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 121700 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 121712 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 121723 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 121734 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 121745 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 121757 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 121768 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 121779 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 121790 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 121802 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 121813 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 121824 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 121835 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 121847 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 121858 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_p4_rperrm router_0_5_5_p4_rperrm PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 122117 R0_5 register p4_rperrm 0x38118 R/W 0x00000000 Pcie_noc_router_0_5_5_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 121881 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 121892 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 121903 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 121914 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 121925 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 121936 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 121947 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 121958 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 121970 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 121981 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 121992 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 122003 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 122015 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 122026 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 122037 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 122048 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 122060 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 122071 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 122082 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 122093 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 122105 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 122116 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_p5_rperrm router_0_5_5_p5_rperrm PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 122375 R0_5 register p5_rperrm 0x38120 R/W 0x00000000 Pcie_noc_router_0_5_5_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 122139 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 122150 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 122161 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 122172 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 122183 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 122194 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 122205 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 122216 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 122228 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 122239 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 122250 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 122261 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 122273 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 122284 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 122295 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 122306 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 122318 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 122329 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 122340 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 122351 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 122363 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 122374 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_p6_rperrm router_0_5_5_p6_rperrm PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 122633 R0_5 register p6_rperrm 0x38128 R/W 0x00000000 Pcie_noc_router_0_5_5_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 122397 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 122408 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 122419 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 122430 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 122441 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 122452 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 122463 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 122474 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 122486 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 122497 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 122508 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 122519 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 122531 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 122542 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 122553 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 122564 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 122576 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 122587 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 122598 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 122609 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 122621 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 122632 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_p7_rperrm router_0_5_5_p7_rperrm PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_OFFSET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 122891 R0_5 register p7_rperrm 0x38130 R/W 0x00000000 Pcie_noc_router_0_5_5_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 122655 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 122666 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 122677 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 122688 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 122699 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 122710 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 122721 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 122732 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 122744 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 122755 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 122766 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 122777 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 122789 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 122800 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 122811 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 122822 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 122834 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 122845 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 122856 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 122867 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 122879 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 122890 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_5_5_roecc router_0_5_5_roecc PCIE_NOC_ROUTER_0_5_5_ROECC_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROECC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROECC_OFFSET PCIE_NOC_ROUTER_0_5_5_ROECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 122964 R0_5 register roecc 0x38138 R/W 0x00000000 Pcie_noc_router_0_5_5_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_WIDTH PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_MSB PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_LSB PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_RANGE PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_RESET PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_GET PCIE_NOC_ROUTER_0_5_5_ROECC_OVC_SET ns_noc_io_pcie_soc_ip.csr 122909 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP PCIE_NOC_ROUTER_0_5_5_ROECC_OP_WIDTH PCIE_NOC_ROUTER_0_5_5_ROECC_OP_MSB PCIE_NOC_ROUTER_0_5_5_ROECC_OP_LSB PCIE_NOC_ROUTER_0_5_5_ROECC_OP_RANGE PCIE_NOC_ROUTER_0_5_5_ROECC_OP_RESET PCIE_NOC_ROUTER_0_5_5_ROECC_OP_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROECC_OP_GET PCIE_NOC_ROUTER_0_5_5_ROECC_OP_SET ns_noc_io_pcie_soc_ip.csr 122920 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_GET PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 122931 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_WIDTH PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_MSB PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_LSB PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_RANGE PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_RESET PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_GET PCIE_NOC_ROUTER_0_5_5_ROECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 122952 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_WIDTH PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_MSB PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_LSB PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_RANGE PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_RESET PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_GET PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_SET ns_noc_io_pcie_soc_ip.csr 122963 UNSD_31_11 31 11 0x000000 R register pcie_noc.router_0_5_5_roec router_0_5_5_roec PCIE_NOC_ROUTER_0_5_5_ROEC_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROEC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_5_5_ROEC_OFFSET PCIE_NOC_ROUTER_0_5_5_ROEC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 122989 R0_5 register roec 0x38140 R/W 0x00000000 Pcie_noc_router_0_5_5_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_GET PCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 122988 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_0_6_6_rivcs_h router_0_6_6_rivcs_h PCIE_NOC_ROUTER_0_6_6_RIVCS_H_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 123318 R0_6 register rivcs_h 0x3C000 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 123014 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_SET ns_noc_io_pcie_soc_ip.csr 123028 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_SET ns_noc_io_pcie_soc_ip.csr 123044 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_SET ns_noc_io_pcie_soc_ip.csr 123058 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_SET ns_noc_io_pcie_soc_ip.csr 123069 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_SET ns_noc_io_pcie_soc_ip.csr 123080 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 123093 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_SET ns_noc_io_pcie_soc_ip.csr 123107 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_SET ns_noc_io_pcie_soc_ip.csr 123123 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_SET ns_noc_io_pcie_soc_ip.csr 123137 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_SET ns_noc_io_pcie_soc_ip.csr 123148 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_SET ns_noc_io_pcie_soc_ip.csr 123159 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 123172 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_SET ns_noc_io_pcie_soc_ip.csr 123186 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_SET ns_noc_io_pcie_soc_ip.csr 123202 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_SET ns_noc_io_pcie_soc_ip.csr 123216 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_SET ns_noc_io_pcie_soc_ip.csr 123227 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_SET ns_noc_io_pcie_soc_ip.csr 123238 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 123251 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_SET ns_noc_io_pcie_soc_ip.csr 123265 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_SET ns_noc_io_pcie_soc_ip.csr 123281 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_SET ns_noc_io_pcie_soc_ip.csr 123295 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_SET ns_noc_io_pcie_soc_ip.csr 123306 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_SET ns_noc_io_pcie_soc_ip.csr 123317 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_e router_0_6_6_rivcs_e PCIE_NOC_ROUTER_0_6_6_RIVCS_E_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 123647 R0_6 register rivcs_e 0x3C008 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 123343 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_SET ns_noc_io_pcie_soc_ip.csr 123357 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_SET ns_noc_io_pcie_soc_ip.csr 123373 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_SET ns_noc_io_pcie_soc_ip.csr 123387 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_SET ns_noc_io_pcie_soc_ip.csr 123398 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_SET ns_noc_io_pcie_soc_ip.csr 123409 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 123422 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_SET ns_noc_io_pcie_soc_ip.csr 123436 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_SET ns_noc_io_pcie_soc_ip.csr 123452 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_SET ns_noc_io_pcie_soc_ip.csr 123466 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_SET ns_noc_io_pcie_soc_ip.csr 123477 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_SET ns_noc_io_pcie_soc_ip.csr 123488 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 123501 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_SET ns_noc_io_pcie_soc_ip.csr 123515 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_SET ns_noc_io_pcie_soc_ip.csr 123531 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_SET ns_noc_io_pcie_soc_ip.csr 123545 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_SET ns_noc_io_pcie_soc_ip.csr 123556 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_SET ns_noc_io_pcie_soc_ip.csr 123567 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 123580 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_SET ns_noc_io_pcie_soc_ip.csr 123594 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_SET ns_noc_io_pcie_soc_ip.csr 123610 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_SET ns_noc_io_pcie_soc_ip.csr 123624 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_SET ns_noc_io_pcie_soc_ip.csr 123635 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_SET ns_noc_io_pcie_soc_ip.csr 123646 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_s router_0_6_6_rivcs_s PCIE_NOC_ROUTER_0_6_6_RIVCS_S_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 123976 R0_6 register rivcs_s 0x3C010 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_s This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 123672 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_SET ns_noc_io_pcie_soc_ip.csr 123686 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_SET ns_noc_io_pcie_soc_ip.csr 123702 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_SET ns_noc_io_pcie_soc_ip.csr 123716 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_SET ns_noc_io_pcie_soc_ip.csr 123727 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_SET ns_noc_io_pcie_soc_ip.csr 123738 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 123751 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_SET ns_noc_io_pcie_soc_ip.csr 123765 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_SET ns_noc_io_pcie_soc_ip.csr 123781 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_SET ns_noc_io_pcie_soc_ip.csr 123795 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_SET ns_noc_io_pcie_soc_ip.csr 123806 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_SET ns_noc_io_pcie_soc_ip.csr 123817 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 123830 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_SET ns_noc_io_pcie_soc_ip.csr 123844 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_SET ns_noc_io_pcie_soc_ip.csr 123860 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_SET ns_noc_io_pcie_soc_ip.csr 123874 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_SET ns_noc_io_pcie_soc_ip.csr 123885 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_SET ns_noc_io_pcie_soc_ip.csr 123896 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 123909 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_SET ns_noc_io_pcie_soc_ip.csr 123923 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_SET ns_noc_io_pcie_soc_ip.csr 123939 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_SET ns_noc_io_pcie_soc_ip.csr 123953 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_SET ns_noc_io_pcie_soc_ip.csr 123964 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_SET ns_noc_io_pcie_soc_ip.csr 123975 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_w router_0_6_6_rivcs_w PCIE_NOC_ROUTER_0_6_6_RIVCS_W_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 124305 R0_6 register rivcs_w 0x3C018 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 124001 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_SET ns_noc_io_pcie_soc_ip.csr 124015 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_SET ns_noc_io_pcie_soc_ip.csr 124031 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_SET ns_noc_io_pcie_soc_ip.csr 124045 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_SET ns_noc_io_pcie_soc_ip.csr 124056 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_SET ns_noc_io_pcie_soc_ip.csr 124067 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 124080 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_SET ns_noc_io_pcie_soc_ip.csr 124094 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_SET ns_noc_io_pcie_soc_ip.csr 124110 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_SET ns_noc_io_pcie_soc_ip.csr 124124 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_SET ns_noc_io_pcie_soc_ip.csr 124135 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_SET ns_noc_io_pcie_soc_ip.csr 124146 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 124159 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_SET ns_noc_io_pcie_soc_ip.csr 124173 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_SET ns_noc_io_pcie_soc_ip.csr 124189 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_SET ns_noc_io_pcie_soc_ip.csr 124203 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_SET ns_noc_io_pcie_soc_ip.csr 124214 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_SET ns_noc_io_pcie_soc_ip.csr 124225 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 124238 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_SET ns_noc_io_pcie_soc_ip.csr 124252 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_SET ns_noc_io_pcie_soc_ip.csr 124268 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_SET ns_noc_io_pcie_soc_ip.csr 124282 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_SET ns_noc_io_pcie_soc_ip.csr 124293 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_SET ns_noc_io_pcie_soc_ip.csr 124304 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_n router_0_6_6_rivcs_n PCIE_NOC_ROUTER_0_6_6_RIVCS_N_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_N_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 124634 R0_6 register rivcs_n 0x3C020 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 124330 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_SET ns_noc_io_pcie_soc_ip.csr 124344 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_SET ns_noc_io_pcie_soc_ip.csr 124360 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_SET ns_noc_io_pcie_soc_ip.csr 124374 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_SET ns_noc_io_pcie_soc_ip.csr 124385 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_SET ns_noc_io_pcie_soc_ip.csr 124396 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 124409 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_SET ns_noc_io_pcie_soc_ip.csr 124423 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_SET ns_noc_io_pcie_soc_ip.csr 124439 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_SET ns_noc_io_pcie_soc_ip.csr 124453 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_SET ns_noc_io_pcie_soc_ip.csr 124464 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_SET ns_noc_io_pcie_soc_ip.csr 124475 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 124488 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_SET ns_noc_io_pcie_soc_ip.csr 124502 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_SET ns_noc_io_pcie_soc_ip.csr 124518 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_SET ns_noc_io_pcie_soc_ip.csr 124532 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_SET ns_noc_io_pcie_soc_ip.csr 124543 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_SET ns_noc_io_pcie_soc_ip.csr 124554 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 124567 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_SET ns_noc_io_pcie_soc_ip.csr 124581 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_SET ns_noc_io_pcie_soc_ip.csr 124597 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_SET ns_noc_io_pcie_soc_ip.csr 124611 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_SET ns_noc_io_pcie_soc_ip.csr 124622 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_SET ns_noc_io_pcie_soc_ip.csr 124633 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_i router_0_6_6_rivcs_i PCIE_NOC_ROUTER_0_6_6_RIVCS_I_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 124963 R0_6 register rivcs_i 0x3C028 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 124659 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_SET ns_noc_io_pcie_soc_ip.csr 124673 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_SET ns_noc_io_pcie_soc_ip.csr 124689 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_SET ns_noc_io_pcie_soc_ip.csr 124703 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_SET ns_noc_io_pcie_soc_ip.csr 124714 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_SET ns_noc_io_pcie_soc_ip.csr 124725 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 124738 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_SET ns_noc_io_pcie_soc_ip.csr 124752 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_SET ns_noc_io_pcie_soc_ip.csr 124768 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_SET ns_noc_io_pcie_soc_ip.csr 124782 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_SET ns_noc_io_pcie_soc_ip.csr 124793 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_SET ns_noc_io_pcie_soc_ip.csr 124804 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 124817 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_SET ns_noc_io_pcie_soc_ip.csr 124831 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_SET ns_noc_io_pcie_soc_ip.csr 124847 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_SET ns_noc_io_pcie_soc_ip.csr 124861 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_SET ns_noc_io_pcie_soc_ip.csr 124872 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_SET ns_noc_io_pcie_soc_ip.csr 124883 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 124896 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_SET ns_noc_io_pcie_soc_ip.csr 124910 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_SET ns_noc_io_pcie_soc_ip.csr 124926 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_SET ns_noc_io_pcie_soc_ip.csr 124940 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_SET ns_noc_io_pcie_soc_ip.csr 124951 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_SET ns_noc_io_pcie_soc_ip.csr 124962 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_j router_0_6_6_rivcs_j PCIE_NOC_ROUTER_0_6_6_RIVCS_J_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 125292 R0_6 register rivcs_j 0x3C030 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 124988 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_SET ns_noc_io_pcie_soc_ip.csr 125002 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_SET ns_noc_io_pcie_soc_ip.csr 125018 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_SET ns_noc_io_pcie_soc_ip.csr 125032 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_SET ns_noc_io_pcie_soc_ip.csr 125043 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_SET ns_noc_io_pcie_soc_ip.csr 125054 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 125067 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_SET ns_noc_io_pcie_soc_ip.csr 125081 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_SET ns_noc_io_pcie_soc_ip.csr 125097 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_SET ns_noc_io_pcie_soc_ip.csr 125111 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_SET ns_noc_io_pcie_soc_ip.csr 125122 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_SET ns_noc_io_pcie_soc_ip.csr 125133 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 125146 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_SET ns_noc_io_pcie_soc_ip.csr 125160 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_SET ns_noc_io_pcie_soc_ip.csr 125176 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_SET ns_noc_io_pcie_soc_ip.csr 125190 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_SET ns_noc_io_pcie_soc_ip.csr 125201 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_SET ns_noc_io_pcie_soc_ip.csr 125212 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 125225 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_SET ns_noc_io_pcie_soc_ip.csr 125239 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_SET ns_noc_io_pcie_soc_ip.csr 125255 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_SET ns_noc_io_pcie_soc_ip.csr 125269 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_SET ns_noc_io_pcie_soc_ip.csr 125280 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_SET ns_noc_io_pcie_soc_ip.csr 125291 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rivcs_k router_0_6_6_rivcs_k PCIE_NOC_ROUTER_0_6_6_RIVCS_K_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OFFSET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 125621 R0_6 register rivcs_k 0x3C038 R 0x00000000 Pcie_noc_router_0_6_6_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 125317 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_SET ns_noc_io_pcie_soc_ip.csr 125331 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_SET ns_noc_io_pcie_soc_ip.csr 125347 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_SET ns_noc_io_pcie_soc_ip.csr 125361 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_SET ns_noc_io_pcie_soc_ip.csr 125372 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_SET ns_noc_io_pcie_soc_ip.csr 125383 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 125396 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_SET ns_noc_io_pcie_soc_ip.csr 125410 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_SET ns_noc_io_pcie_soc_ip.csr 125426 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_SET ns_noc_io_pcie_soc_ip.csr 125440 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_SET ns_noc_io_pcie_soc_ip.csr 125451 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_SET ns_noc_io_pcie_soc_ip.csr 125462 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 125475 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_SET ns_noc_io_pcie_soc_ip.csr 125489 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_SET ns_noc_io_pcie_soc_ip.csr 125505 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_SET ns_noc_io_pcie_soc_ip.csr 125519 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_SET ns_noc_io_pcie_soc_ip.csr 125530 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_SET ns_noc_io_pcie_soc_ip.csr 125541 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 125554 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_SET ns_noc_io_pcie_soc_ip.csr 125568 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_SET ns_noc_io_pcie_soc_ip.csr 125584 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_SET ns_noc_io_pcie_soc_ip.csr 125598 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_SET ns_noc_io_pcie_soc_ip.csr 125609 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_MSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_LSB PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_RANGE PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_RESET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_GET PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_SET ns_noc_io_pcie_soc_ip.csr 125620 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_0_6_6_rovcs_h router_0_6_6_rovcs_h PCIE_NOC_ROUTER_0_6_6_ROVCS_H_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_H_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 125882 R0_6 register rovcs_h 0x3C040 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_SET ns_noc_io_pcie_soc_ip.csr 125645 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_SET ns_noc_io_pcie_soc_ip.csr 125659 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_SET ns_noc_io_pcie_soc_ip.csr 125674 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 125685 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 125695 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_SET ns_noc_io_pcie_soc_ip.csr 125707 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_SET ns_noc_io_pcie_soc_ip.csr 125721 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_SET ns_noc_io_pcie_soc_ip.csr 125736 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 125747 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 125757 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_SET ns_noc_io_pcie_soc_ip.csr 125769 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_SET ns_noc_io_pcie_soc_ip.csr 125783 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_SET ns_noc_io_pcie_soc_ip.csr 125798 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 125809 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 125819 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_SET ns_noc_io_pcie_soc_ip.csr 125831 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_SET ns_noc_io_pcie_soc_ip.csr 125845 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_SET ns_noc_io_pcie_soc_ip.csr 125860 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 125871 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 125881 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_e router_0_6_6_rovcs_e PCIE_NOC_ROUTER_0_6_6_ROVCS_E_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_E_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 126143 R0_6 register rovcs_e 0x3C048 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_SET ns_noc_io_pcie_soc_ip.csr 125906 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_SET ns_noc_io_pcie_soc_ip.csr 125920 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_SET ns_noc_io_pcie_soc_ip.csr 125935 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 125946 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 125956 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_SET ns_noc_io_pcie_soc_ip.csr 125968 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_SET ns_noc_io_pcie_soc_ip.csr 125982 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_SET ns_noc_io_pcie_soc_ip.csr 125997 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 126008 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 126018 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_SET ns_noc_io_pcie_soc_ip.csr 126030 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_SET ns_noc_io_pcie_soc_ip.csr 126044 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_SET ns_noc_io_pcie_soc_ip.csr 126059 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 126070 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 126080 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_SET ns_noc_io_pcie_soc_ip.csr 126092 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_SET ns_noc_io_pcie_soc_ip.csr 126106 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_SET ns_noc_io_pcie_soc_ip.csr 126121 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 126132 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 126142 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_s router_0_6_6_rovcs_s PCIE_NOC_ROUTER_0_6_6_ROVCS_S_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_S_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 126404 R0_6 register rovcs_s 0x3C050 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_s This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_SET ns_noc_io_pcie_soc_ip.csr 126167 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_SET ns_noc_io_pcie_soc_ip.csr 126181 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_SET ns_noc_io_pcie_soc_ip.csr 126196 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 126207 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 126217 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_SET ns_noc_io_pcie_soc_ip.csr 126229 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_SET ns_noc_io_pcie_soc_ip.csr 126243 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_SET ns_noc_io_pcie_soc_ip.csr 126258 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 126269 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 126279 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_SET ns_noc_io_pcie_soc_ip.csr 126291 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_SET ns_noc_io_pcie_soc_ip.csr 126305 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_SET ns_noc_io_pcie_soc_ip.csr 126320 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 126331 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 126341 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_SET ns_noc_io_pcie_soc_ip.csr 126353 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_SET ns_noc_io_pcie_soc_ip.csr 126367 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_SET ns_noc_io_pcie_soc_ip.csr 126382 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 126393 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 126403 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_w router_0_6_6_rovcs_w PCIE_NOC_ROUTER_0_6_6_ROVCS_W_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_W_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 126665 R0_6 register rovcs_w 0x3C058 R 0x00000101 Pcie_noc_router_0_6_6_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_SET ns_noc_io_pcie_soc_ip.csr 126428 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_SET ns_noc_io_pcie_soc_ip.csr 126442 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_SET ns_noc_io_pcie_soc_ip.csr 126457 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 126468 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 126478 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_SET ns_noc_io_pcie_soc_ip.csr 126490 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_SET ns_noc_io_pcie_soc_ip.csr 126504 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_SET ns_noc_io_pcie_soc_ip.csr 126519 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 126530 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 126540 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_SET ns_noc_io_pcie_soc_ip.csr 126552 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_SET ns_noc_io_pcie_soc_ip.csr 126566 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_SET ns_noc_io_pcie_soc_ip.csr 126581 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 126592 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 126602 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_SET ns_noc_io_pcie_soc_ip.csr 126614 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_SET ns_noc_io_pcie_soc_ip.csr 126628 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_SET ns_noc_io_pcie_soc_ip.csr 126643 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 126654 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 126664 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_n router_0_6_6_rovcs_n PCIE_NOC_ROUTER_0_6_6_ROVCS_N_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_N_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_N_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 126926 R0_6 register rovcs_n 0x3C060 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_SET ns_noc_io_pcie_soc_ip.csr 126689 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_SET ns_noc_io_pcie_soc_ip.csr 126703 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_SET ns_noc_io_pcie_soc_ip.csr 126718 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 126729 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 126739 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_SET ns_noc_io_pcie_soc_ip.csr 126751 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_SET ns_noc_io_pcie_soc_ip.csr 126765 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_SET ns_noc_io_pcie_soc_ip.csr 126780 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 126791 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 126801 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_SET ns_noc_io_pcie_soc_ip.csr 126813 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_SET ns_noc_io_pcie_soc_ip.csr 126827 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_SET ns_noc_io_pcie_soc_ip.csr 126842 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 126853 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 126863 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_SET ns_noc_io_pcie_soc_ip.csr 126875 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_SET ns_noc_io_pcie_soc_ip.csr 126889 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_SET ns_noc_io_pcie_soc_ip.csr 126904 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 126915 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 126925 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_i router_0_6_6_rovcs_i PCIE_NOC_ROUTER_0_6_6_ROVCS_I_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_I_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 127187 R0_6 register rovcs_i 0x3C068 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_SET ns_noc_io_pcie_soc_ip.csr 126950 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_SET ns_noc_io_pcie_soc_ip.csr 126964 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_SET ns_noc_io_pcie_soc_ip.csr 126979 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 126990 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 127000 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_SET ns_noc_io_pcie_soc_ip.csr 127012 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_SET ns_noc_io_pcie_soc_ip.csr 127026 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_SET ns_noc_io_pcie_soc_ip.csr 127041 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 127052 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 127062 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_SET ns_noc_io_pcie_soc_ip.csr 127074 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_SET ns_noc_io_pcie_soc_ip.csr 127088 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_SET ns_noc_io_pcie_soc_ip.csr 127103 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 127114 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 127124 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_SET ns_noc_io_pcie_soc_ip.csr 127136 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_SET ns_noc_io_pcie_soc_ip.csr 127150 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_SET ns_noc_io_pcie_soc_ip.csr 127165 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 127176 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 127186 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_j router_0_6_6_rovcs_j PCIE_NOC_ROUTER_0_6_6_ROVCS_J_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_J_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 127448 R0_6 register rovcs_j 0x3C070 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_SET ns_noc_io_pcie_soc_ip.csr 127211 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_SET ns_noc_io_pcie_soc_ip.csr 127225 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_SET ns_noc_io_pcie_soc_ip.csr 127240 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 127251 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 127261 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_SET ns_noc_io_pcie_soc_ip.csr 127273 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_SET ns_noc_io_pcie_soc_ip.csr 127287 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_SET ns_noc_io_pcie_soc_ip.csr 127302 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 127313 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 127323 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_SET ns_noc_io_pcie_soc_ip.csr 127335 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_SET ns_noc_io_pcie_soc_ip.csr 127349 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_SET ns_noc_io_pcie_soc_ip.csr 127364 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 127375 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 127385 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_SET ns_noc_io_pcie_soc_ip.csr 127397 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_SET ns_noc_io_pcie_soc_ip.csr 127411 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_SET ns_noc_io_pcie_soc_ip.csr 127426 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 127437 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 127447 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_rovcs_k router_0_6_6_rovcs_k PCIE_NOC_ROUTER_0_6_6_ROVCS_K_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROVCS_K_OFFSET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 127709 R0_6 register rovcs_k 0x3C078 R 0x00000001 Pcie_noc_router_0_6_6_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_SET ns_noc_io_pcie_soc_ip.csr 127472 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_SET ns_noc_io_pcie_soc_ip.csr 127486 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_SET ns_noc_io_pcie_soc_ip.csr 127501 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 127512 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 127522 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_SET ns_noc_io_pcie_soc_ip.csr 127534 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_SET ns_noc_io_pcie_soc_ip.csr 127548 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_SET ns_noc_io_pcie_soc_ip.csr 127563 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 127574 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 127584 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_SET ns_noc_io_pcie_soc_ip.csr 127596 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_SET ns_noc_io_pcie_soc_ip.csr 127610 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_SET ns_noc_io_pcie_soc_ip.csr 127625 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 127636 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 127646 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_SET ns_noc_io_pcie_soc_ip.csr 127658 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_SET ns_noc_io_pcie_soc_ip.csr 127672 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_SET ns_noc_io_pcie_soc_ip.csr 127687 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 127698 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_WIDTH PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_MSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_LSB PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_RANGE PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_RESET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_GET PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 127708 UNSD_3 31 28 0x0 R register pcie_noc.router_0_6_6_re router_0_6_6_re PCIE_NOC_ROUTER_0_6_6_RE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RE_OFFSET PCIE_NOC_ROUTER_0_6_6_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 127883 R0_6 register re 0x3C080 R/W 0x00000000 Pcie_noc_router_0_6_6_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_0_6_6_RE_OVFI_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_OVFI_MSB PCIE_NOC_ROUTER_0_6_6_RE_OVFI_LSB PCIE_NOC_ROUTER_0_6_6_RE_OVFI_RANGE PCIE_NOC_ROUTER_0_6_6_RE_OVFI_RESET PCIE_NOC_ROUTER_0_6_6_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_OVFI_GET PCIE_NOC_ROUTER_0_6_6_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 127735 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 127746 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_0_6_6_RE_OVFO_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_OVFO_MSB PCIE_NOC_ROUTER_0_6_6_RE_OVFO_LSB PCIE_NOC_ROUTER_0_6_6_RE_OVFO_RANGE PCIE_NOC_ROUTER_0_6_6_RE_OVFO_RESET PCIE_NOC_ROUTER_0_6_6_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_OVFO_GET PCIE_NOC_ROUTER_0_6_6_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 127760 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 127771 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_0_6_6_RE_PGE_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_PGE_MSB PCIE_NOC_ROUTER_0_6_6_RE_PGE_LSB PCIE_NOC_ROUTER_0_6_6_RE_PGE_RANGE PCIE_NOC_ROUTER_0_6_6_RE_PGE_RESET PCIE_NOC_ROUTER_0_6_6_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_PGE_GET PCIE_NOC_ROUTER_0_6_6_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 127783 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_0_6_6_RE_NLU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_NLU_MSB PCIE_NOC_ROUTER_0_6_6_RE_NLU_LSB PCIE_NOC_ROUTER_0_6_6_RE_NLU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_NLU_RESET PCIE_NOC_ROUTER_0_6_6_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_NLU_GET PCIE_NOC_ROUTER_0_6_6_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 127794 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_0_6_6_RE_ELU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_ELU_MSB PCIE_NOC_ROUTER_0_6_6_RE_ELU_LSB PCIE_NOC_ROUTER_0_6_6_RE_ELU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_ELU_RESET PCIE_NOC_ROUTER_0_6_6_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_ELU_GET PCIE_NOC_ROUTER_0_6_6_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 127805 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_0_6_6_RE_WLU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_WLU_MSB PCIE_NOC_ROUTER_0_6_6_RE_WLU_LSB PCIE_NOC_ROUTER_0_6_6_RE_WLU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_WLU_RESET PCIE_NOC_ROUTER_0_6_6_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_WLU_GET PCIE_NOC_ROUTER_0_6_6_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 127816 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_0_6_6_RE_SLU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_SLU_MSB PCIE_NOC_ROUTER_0_6_6_RE_SLU_LSB PCIE_NOC_ROUTER_0_6_6_RE_SLU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_SLU_RESET PCIE_NOC_ROUTER_0_6_6_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_SLU_GET PCIE_NOC_ROUTER_0_6_6_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 127827 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_0_6_6_RE_HLU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_HLU_MSB PCIE_NOC_ROUTER_0_6_6_RE_HLU_LSB PCIE_NOC_ROUTER_0_6_6_RE_HLU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_HLU_RESET PCIE_NOC_ROUTER_0_6_6_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_HLU_GET PCIE_NOC_ROUTER_0_6_6_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 127838 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_0_6_6_RE_ILU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_ILU_MSB PCIE_NOC_ROUTER_0_6_6_RE_ILU_LSB PCIE_NOC_ROUTER_0_6_6_RE_ILU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_ILU_RESET PCIE_NOC_ROUTER_0_6_6_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_ILU_GET PCIE_NOC_ROUTER_0_6_6_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 127849 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_0_6_6_RE_JLU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_JLU_MSB PCIE_NOC_ROUTER_0_6_6_RE_JLU_LSB PCIE_NOC_ROUTER_0_6_6_RE_JLU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_JLU_RESET PCIE_NOC_ROUTER_0_6_6_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_JLU_GET PCIE_NOC_ROUTER_0_6_6_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 127860 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_0_6_6_RE_KLU_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_KLU_MSB PCIE_NOC_ROUTER_0_6_6_RE_KLU_LSB PCIE_NOC_ROUTER_0_6_6_RE_KLU_RANGE PCIE_NOC_ROUTER_0_6_6_RE_KLU_RESET PCIE_NOC_ROUTER_0_6_6_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_KLU_GET PCIE_NOC_ROUTER_0_6_6_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 127871 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 127882 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_0_6_6_rem router_0_6_6_rem PCIE_NOC_ROUTER_0_6_6_REM_ADDRESS PCIE_NOC_ROUTER_0_6_6_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_REM_OFFSET PCIE_NOC_ROUTER_0_6_6_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128056 R0_6 register rem 0x3C088 R/W 0x0001fe00 Pcie_noc_router_0_6_6_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_MSB PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_LSB PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_RANGE PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_RESET PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_GET PCIE_NOC_ROUTER_0_6_6_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 127909 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 127920 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_MSB PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_LSB PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_RANGE PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_RESET PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_GET PCIE_NOC_ROUTER_0_6_6_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 127934 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 127945 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_0_6_6_REM_PGM_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_PGM_MSB PCIE_NOC_ROUTER_0_6_6_REM_PGM_LSB PCIE_NOC_ROUTER_0_6_6_REM_PGM_RANGE PCIE_NOC_ROUTER_0_6_6_REM_PGM_RESET PCIE_NOC_ROUTER_0_6_6_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_PGM_GET PCIE_NOC_ROUTER_0_6_6_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 127956 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_0_6_6_REM_MN_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MN_MSB PCIE_NOC_ROUTER_0_6_6_REM_MN_LSB PCIE_NOC_ROUTER_0_6_6_REM_MN_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MN_RESET PCIE_NOC_ROUTER_0_6_6_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MN_GET PCIE_NOC_ROUTER_0_6_6_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 127967 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_0_6_6_REM_ME_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_ME_MSB PCIE_NOC_ROUTER_0_6_6_REM_ME_LSB PCIE_NOC_ROUTER_0_6_6_REM_ME_RANGE PCIE_NOC_ROUTER_0_6_6_REM_ME_RESET PCIE_NOC_ROUTER_0_6_6_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_ME_GET PCIE_NOC_ROUTER_0_6_6_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 127978 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_0_6_6_REM_MW_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MW_MSB PCIE_NOC_ROUTER_0_6_6_REM_MW_LSB PCIE_NOC_ROUTER_0_6_6_REM_MW_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MW_RESET PCIE_NOC_ROUTER_0_6_6_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MW_GET PCIE_NOC_ROUTER_0_6_6_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 127989 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_0_6_6_REM_MS_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MS_MSB PCIE_NOC_ROUTER_0_6_6_REM_MS_LSB PCIE_NOC_ROUTER_0_6_6_REM_MS_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MS_RESET PCIE_NOC_ROUTER_0_6_6_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MS_GET PCIE_NOC_ROUTER_0_6_6_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 128000 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_0_6_6_REM_MH_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MH_MSB PCIE_NOC_ROUTER_0_6_6_REM_MH_LSB PCIE_NOC_ROUTER_0_6_6_REM_MH_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MH_RESET PCIE_NOC_ROUTER_0_6_6_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MH_GET PCIE_NOC_ROUTER_0_6_6_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 128011 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_0_6_6_REM_MI_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MI_MSB PCIE_NOC_ROUTER_0_6_6_REM_MI_LSB PCIE_NOC_ROUTER_0_6_6_REM_MI_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MI_RESET PCIE_NOC_ROUTER_0_6_6_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MI_GET PCIE_NOC_ROUTER_0_6_6_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 128022 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_0_6_6_REM_MJ_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MJ_MSB PCIE_NOC_ROUTER_0_6_6_REM_MJ_LSB PCIE_NOC_ROUTER_0_6_6_REM_MJ_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MJ_RESET PCIE_NOC_ROUTER_0_6_6_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MJ_GET PCIE_NOC_ROUTER_0_6_6_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 128033 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_0_6_6_REM_MK_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_MK_MSB PCIE_NOC_ROUTER_0_6_6_REM_MK_LSB PCIE_NOC_ROUTER_0_6_6_REM_MK_RANGE PCIE_NOC_ROUTER_0_6_6_REM_MK_RESET PCIE_NOC_ROUTER_0_6_6_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_MK_GET PCIE_NOC_ROUTER_0_6_6_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 128044 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 128055 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_0_6_6_recc router_0_6_6_recc PCIE_NOC_ROUTER_0_6_6_RECC_ADDRESS PCIE_NOC_ROUTER_0_6_6_RECC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RECC_OFFSET PCIE_NOC_ROUTER_0_6_6_RECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128141 R0_6 register recc 0x3C090 R/W 0x00000000 Pcie_noc_router_0_6_6_recc This register is used to select which hardware events will increment the event counter. false false false false IVC PCIE_NOC_ROUTER_0_6_6_RECC_IVC_WIDTH PCIE_NOC_ROUTER_0_6_6_RECC_IVC_MSB PCIE_NOC_ROUTER_0_6_6_RECC_IVC_LSB PCIE_NOC_ROUTER_0_6_6_RECC_IVC_RANGE PCIE_NOC_ROUTER_0_6_6_RECC_IVC_RESET PCIE_NOC_ROUTER_0_6_6_RECC_IVC_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RECC_IVC_GET PCIE_NOC_ROUTER_0_6_6_RECC_IVC_SET ns_noc_io_pcie_soc_ip.csr 128077 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_WIDTH PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_MSB PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_LSB PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_RANGE PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_RESET PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_GET PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_SET ns_noc_io_pcie_soc_ip.csr 128088 UNSD_3_2 3 2 0x0 R INP PCIE_NOC_ROUTER_0_6_6_RECC_INP_WIDTH PCIE_NOC_ROUTER_0_6_6_RECC_INP_MSB PCIE_NOC_ROUTER_0_6_6_RECC_INP_LSB PCIE_NOC_ROUTER_0_6_6_RECC_INP_RANGE PCIE_NOC_ROUTER_0_6_6_RECC_INP_RESET PCIE_NOC_ROUTER_0_6_6_RECC_INP_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RECC_INP_GET PCIE_NOC_ROUTER_0_6_6_RECC_INP_SET ns_noc_io_pcie_soc_ip.csr 128099 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_GET PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 128110 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_0_6_6_RECC_EVT_WIDTH PCIE_NOC_ROUTER_0_6_6_RECC_EVT_MSB PCIE_NOC_ROUTER_0_6_6_RECC_EVT_LSB PCIE_NOC_ROUTER_0_6_6_RECC_EVT_RANGE PCIE_NOC_ROUTER_0_6_6_RECC_EVT_RESET PCIE_NOC_ROUTER_0_6_6_RECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RECC_EVT_GET PCIE_NOC_ROUTER_0_6_6_RECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 128129 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_WIDTH PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_MSB PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_LSB PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_RANGE PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_RESET PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_GET PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_SET ns_noc_io_pcie_soc_ip.csr 128140 UNSD_31_10 31 10 0x000000 R register pcie_noc.router_0_6_6_rec router_0_6_6_rec PCIE_NOC_ROUTER_0_6_6_REC_ADDRESS PCIE_NOC_ROUTER_0_6_6_REC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_REC_OFFSET PCIE_NOC_ROUTER_0_6_6_REC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128166 R0_6 register rec 0x3C098 R/W 0x00000000 Pcie_noc_router_0_6_6_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_GET PCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 128165 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_0_6_6_id router_0_6_6_id PCIE_NOC_ROUTER_0_6_6_ID_ADDRESS PCIE_NOC_ROUTER_0_6_6_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ID_OFFSET PCIE_NOC_ROUTER_0_6_6_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128235 R0_6 register id 0x3C0A0 R 0x010000c0 Pcie_noc_router_0_6_6_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_0_6_6_ID_LAYER_WIDTH PCIE_NOC_ROUTER_0_6_6_ID_LAYER_MSB PCIE_NOC_ROUTER_0_6_6_ID_LAYER_LSB PCIE_NOC_ROUTER_0_6_6_ID_LAYER_RANGE PCIE_NOC_ROUTER_0_6_6_ID_LAYER_RESET PCIE_NOC_ROUTER_0_6_6_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ID_LAYER_GET PCIE_NOC_ROUTER_0_6_6_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 128191 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x00 R POS PCIE_NOC_ROUTER_0_6_6_ID_POS_WIDTH PCIE_NOC_ROUTER_0_6_6_ID_POS_MSB PCIE_NOC_ROUTER_0_6_6_ID_POS_LSB PCIE_NOC_ROUTER_0_6_6_ID_POS_RANGE PCIE_NOC_ROUTER_0_6_6_ID_POS_RESET PCIE_NOC_ROUTER_0_6_6_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ID_POS_GET PCIE_NOC_ROUTER_0_6_6_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 128202 POS 16-bit position ID of this router in the NoC 20 5 0x0006 R ZERO PCIE_NOC_ROUTER_0_6_6_ID_ZERO_WIDTH PCIE_NOC_ROUTER_0_6_6_ID_ZERO_MSB PCIE_NOC_ROUTER_0_6_6_ID_ZERO_LSB PCIE_NOC_ROUTER_0_6_6_ID_ZERO_RANGE PCIE_NOC_ROUTER_0_6_6_ID_ZERO_RESET PCIE_NOC_ROUTER_0_6_6_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ID_ZERO_GET PCIE_NOC_ROUTER_0_6_6_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 128213 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_0_6_6_ID_ONE_WIDTH PCIE_NOC_ROUTER_0_6_6_ID_ONE_MSB PCIE_NOC_ROUTER_0_6_6_ID_ONE_LSB PCIE_NOC_ROUTER_0_6_6_ID_ONE_RANGE PCIE_NOC_ROUTER_0_6_6_ID_ONE_RESET PCIE_NOC_ROUTER_0_6_6_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ID_ONE_GET PCIE_NOC_ROUTER_0_6_6_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 128224 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 128234 UNSD_31_25 31 25 0x00 R register pcie_noc.router_0_6_6_rcgc router_0_6_6_rcgc PCIE_NOC_ROUTER_0_6_6_RCGC_ADDRESS PCIE_NOC_ROUTER_0_6_6_RCGC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RCGC_OFFSET PCIE_NOC_ROUTER_0_6_6_RCGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128261 R0_6 register rcgc 0x3C0A8 R/W 0x00000064 Pcie_noc_router_0_6_6_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_GET PCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 128260 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register pcie_noc.router_0_6_6_rcgo router_0_6_6_rcgo PCIE_NOC_ROUTER_0_6_6_RCGO_ADDRESS PCIE_NOC_ROUTER_0_6_6_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_RCGO_OFFSET PCIE_NOC_ROUTER_0_6_6_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128300 R0_6 register rcgo 0x3C0B0 R/W 0x00000000 Pcie_noc_router_0_6_6_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_MSB PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_LSB PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_RANGE PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_RESET PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_GET PCIE_NOC_ROUTER_0_6_6_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 128288 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 128299 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_0_6_6_p0_rperr router_0_6_6_p0_rperr PCIE_NOC_ROUTER_0_6_6_P0_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P0_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P0_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128591 R0_6 register p0_rperr 0x3C0B8 R/W 0x00000000 Pcie_noc_router_0_6_6_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 128343 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 128354 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 128365 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 128376 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 128387 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 128398 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 128409 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 128420 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 128432 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 128443 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 128455 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 128467 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 128480 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 128492 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 128504 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 128516 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 128529 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 128541 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 128553 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 128565 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 128578 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 128590 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p1_rperr router_0_6_6_p1_rperr PCIE_NOC_ROUTER_0_6_6_P1_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P1_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P1_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 128878 R0_6 register p1_rperr 0x3C0C0 R/W 0x00000000 Pcie_noc_router_0_6_6_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 128634 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 128645 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 128656 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 128667 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 128678 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 128689 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 128700 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 128711 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 128723 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 128734 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 128745 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 128756 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 128768 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 128779 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 128791 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 128803 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 128816 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 128828 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 128840 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 128852 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 128865 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 128877 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p2_rperr router_0_6_6_p2_rperr PCIE_NOC_ROUTER_0_6_6_P2_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P2_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P2_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 129169 R0_6 register p2_rperr 0x3C0C8 R/W 0x00000000 Pcie_noc_router_0_6_6_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 128921 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 128932 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 128943 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 128954 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 128965 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 128976 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 128987 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 128998 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 129010 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 129021 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 129033 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 129045 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 129058 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 129070 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 129082 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 129094 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 129107 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 129119 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 129131 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 129143 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 129156 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 129168 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p3_rperr router_0_6_6_p3_rperr PCIE_NOC_ROUTER_0_6_6_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P3_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 129460 R0_6 register p3_rperr 0x3C0D0 R/W 0x00000000 Pcie_noc_router_0_6_6_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 129212 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 129223 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 129234 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 129245 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 129256 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 129267 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 129278 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 129289 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 129301 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 129312 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 129324 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 129336 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 129349 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 129361 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 129373 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 129385 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 129398 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 129410 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 129422 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 129434 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 129447 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 129459 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p4_rperr router_0_6_6_p4_rperr PCIE_NOC_ROUTER_0_6_6_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P4_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 129751 R0_6 register p4_rperr 0x3C0D8 R/W 0x00000000 Pcie_noc_router_0_6_6_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 129503 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 129514 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 129525 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 129536 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 129547 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 129558 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 129570 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R SB_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 129582 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R PK_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 129595 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R RI_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 129607 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R D_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 129618 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 129629 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 129641 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 129652 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 129664 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 129676 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 129689 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 129701 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 129713 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 129725 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 129738 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 129750 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p5_rperr router_0_6_6_p5_rperr PCIE_NOC_ROUTER_0_6_6_P5_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P5_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P5_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 130042 R0_6 register p5_rperr 0x3C0E0 R/W 0x00000000 Pcie_noc_router_0_6_6_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 129794 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 129805 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 129816 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 129827 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 129838 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 129849 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 129861 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R SB_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 129873 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R PK_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 129886 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R RI_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 129898 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R D_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 129909 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 129920 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 129932 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 129943 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 129955 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 129967 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 129980 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 129992 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 130004 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 130016 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 130029 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 130041 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p6_rperr router_0_6_6_p6_rperr PCIE_NOC_ROUTER_0_6_6_P6_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P6_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P6_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 130333 R0_6 register p6_rperr 0x3C0E8 R/W 0x00000000 Pcie_noc_router_0_6_6_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 130085 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 130096 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 130107 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 130118 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 130129 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 130140 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 130151 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 130162 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 130174 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 130185 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 130197 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 130209 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 130222 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 130234 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 130246 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 130258 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 130271 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 130283 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 130295 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 130307 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 130320 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 130332 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p7_rperr router_0_6_6_p7_rperr PCIE_NOC_ROUTER_0_6_6_P7_RPERR_ADDRESS PCIE_NOC_ROUTER_0_6_6_P7_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P7_RPERR_OFFSET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 130624 R0_6 register p7_rperr 0x3C0F0 R/W 0x00000000 Pcie_noc_router_0_6_6_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 130376 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 130387 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 130398 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 130409 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 130420 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 130431 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 130442 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 130453 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 130465 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 130476 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 130488 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 130500 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 130513 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 130525 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 130537 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 130549 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 130562 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 130574 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 130586 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 130598 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 130611 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 130623 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_0_6_6_p0_rperrm router_0_6_6_p0_rperrm PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 130882 R0_6 register p0_rperrm 0x3C0F8 R/W 0x00000000 Pcie_noc_router_0_6_6_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 130646 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 130657 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 130668 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 130679 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 130690 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 130701 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 130712 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 130723 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 130735 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 130746 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 130757 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 130768 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 130780 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 130791 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 130802 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 130813 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 130825 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 130836 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 130847 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 130858 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 130870 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 130881 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p1_rperrm router_0_6_6_p1_rperrm PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 131140 R0_6 register p1_rperrm 0x3C100 R/W 0x00000000 Pcie_noc_router_0_6_6_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 130904 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 130915 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 130926 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 130937 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 130948 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 130959 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 130970 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 130981 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 130993 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 131004 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 131015 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 131026 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 131038 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 131049 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 131060 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 131071 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 131083 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 131094 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 131105 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 131116 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 131128 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 131139 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p2_rperrm router_0_6_6_p2_rperrm PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 131398 R0_6 register p2_rperrm 0x3C108 R/W 0x00000000 Pcie_noc_router_0_6_6_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 131162 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 131173 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 131184 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 131195 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 131206 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 131217 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 131228 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 131239 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 131251 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 131262 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 131273 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 131284 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 131296 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 131307 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 131318 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 131329 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 131341 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 131352 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 131363 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 131374 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 131386 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 131397 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p3_rperrm router_0_6_6_p3_rperrm PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 131656 R0_6 register p3_rperrm 0x3C110 R/W 0x00000000 Pcie_noc_router_0_6_6_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 131420 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 131431 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 131442 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 131453 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 131464 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 131475 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 131486 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 131497 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 131509 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 131520 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 131531 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 131542 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 131554 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 131565 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 131576 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 131587 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 131599 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 131610 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 131621 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 131632 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 131644 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 131655 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p4_rperrm router_0_6_6_p4_rperrm PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 131914 R0_6 register p4_rperrm 0x3C118 R/W 0x00000000 Pcie_noc_router_0_6_6_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 131678 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 131689 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 131700 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 131711 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 131722 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 131733 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 131744 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 131755 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 131767 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 131778 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 131789 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 131800 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 131812 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 131823 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 131834 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 131845 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 131857 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 131868 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 131879 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 131890 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 131902 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 131913 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p5_rperrm router_0_6_6_p5_rperrm PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 132172 R0_6 register p5_rperrm 0x3C120 R/W 0x00000000 Pcie_noc_router_0_6_6_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 131936 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 131947 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 131958 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 131969 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 131980 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 131991 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 132002 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 132013 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 132025 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 132036 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 132047 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 132058 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 132070 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 132081 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 132092 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 132103 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 132115 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 132126 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 132137 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 132148 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 132160 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 132171 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p6_rperrm router_0_6_6_p6_rperrm PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 132430 R0_6 register p6_rperrm 0x3C128 R/W 0x00000000 Pcie_noc_router_0_6_6_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 132194 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 132205 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 132216 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 132227 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 132238 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 132249 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 132260 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 132271 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 132283 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 132294 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 132305 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 132316 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 132328 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 132339 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 132350 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 132361 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 132373 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 132384 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 132395 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 132406 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 132418 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 132429 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_p7_rperrm router_0_6_6_p7_rperrm PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_ADDRESS PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_OFFSET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 132688 R0_6 register p7_rperrm 0x3C130 R/W 0x00000000 Pcie_noc_router_0_6_6_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 132452 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 132463 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 132474 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 132485 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 132496 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 132507 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 132518 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 132529 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 132541 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 132552 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 132563 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 132574 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 132586 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 132597 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 132608 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 132619 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 132631 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 132642 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 132653 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 132664 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 132676 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_GET PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 132687 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_0_6_6_roecc router_0_6_6_roecc PCIE_NOC_ROUTER_0_6_6_ROECC_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROECC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROECC_OFFSET PCIE_NOC_ROUTER_0_6_6_ROECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 132761 R0_6 register roecc 0x3C138 R/W 0x00000000 Pcie_noc_router_0_6_6_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_WIDTH PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_MSB PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_LSB PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_RANGE PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_RESET PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_GET PCIE_NOC_ROUTER_0_6_6_ROECC_OVC_SET ns_noc_io_pcie_soc_ip.csr 132706 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP PCIE_NOC_ROUTER_0_6_6_ROECC_OP_WIDTH PCIE_NOC_ROUTER_0_6_6_ROECC_OP_MSB PCIE_NOC_ROUTER_0_6_6_ROECC_OP_LSB PCIE_NOC_ROUTER_0_6_6_ROECC_OP_RANGE PCIE_NOC_ROUTER_0_6_6_ROECC_OP_RESET PCIE_NOC_ROUTER_0_6_6_ROECC_OP_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROECC_OP_GET PCIE_NOC_ROUTER_0_6_6_ROECC_OP_SET ns_noc_io_pcie_soc_ip.csr 132717 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_GET PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 132728 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_WIDTH PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_MSB PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_LSB PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_RANGE PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_RESET PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_GET PCIE_NOC_ROUTER_0_6_6_ROECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 132749 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_WIDTH PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_MSB PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_LSB PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_RANGE PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_RESET PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_GET PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_SET ns_noc_io_pcie_soc_ip.csr 132760 UNSD_31_11 31 11 0x000000 R register pcie_noc.router_0_6_6_roec router_0_6_6_roec PCIE_NOC_ROUTER_0_6_6_ROEC_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROEC_BYTE_ADDRESS PCIE_NOC_ROUTER_0_6_6_ROEC_OFFSET PCIE_NOC_ROUTER_0_6_6_ROEC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 132786 R0_6 register roec 0x3C140 R/W 0x00000000 Pcie_noc_router_0_6_6_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_GET PCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 132785 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_1_5_5_rivcs_h router_1_5_5_rivcs_h PCIE_NOC_ROUTER_1_5_5_RIVCS_H_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 133115 R1_5 register rivcs_h 0x40000 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 132811 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_SET ns_noc_io_pcie_soc_ip.csr 132825 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_SET ns_noc_io_pcie_soc_ip.csr 132841 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_SET ns_noc_io_pcie_soc_ip.csr 132855 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_SET ns_noc_io_pcie_soc_ip.csr 132866 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_SET ns_noc_io_pcie_soc_ip.csr 132877 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 132890 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_SET ns_noc_io_pcie_soc_ip.csr 132904 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_SET ns_noc_io_pcie_soc_ip.csr 132920 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_SET ns_noc_io_pcie_soc_ip.csr 132934 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_SET ns_noc_io_pcie_soc_ip.csr 132945 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_SET ns_noc_io_pcie_soc_ip.csr 132956 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 132969 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_SET ns_noc_io_pcie_soc_ip.csr 132983 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_SET ns_noc_io_pcie_soc_ip.csr 132999 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_SET ns_noc_io_pcie_soc_ip.csr 133013 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_SET ns_noc_io_pcie_soc_ip.csr 133024 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_SET ns_noc_io_pcie_soc_ip.csr 133035 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 133048 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_SET ns_noc_io_pcie_soc_ip.csr 133062 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_SET ns_noc_io_pcie_soc_ip.csr 133078 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_SET ns_noc_io_pcie_soc_ip.csr 133092 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_SET ns_noc_io_pcie_soc_ip.csr 133103 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_SET ns_noc_io_pcie_soc_ip.csr 133114 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rivcs_e router_1_5_5_rivcs_e PCIE_NOC_ROUTER_1_5_5_RIVCS_E_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 133444 R1_5 register rivcs_e 0x40008 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 133140 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_SET ns_noc_io_pcie_soc_ip.csr 133154 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_SET ns_noc_io_pcie_soc_ip.csr 133170 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_SET ns_noc_io_pcie_soc_ip.csr 133184 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_SET ns_noc_io_pcie_soc_ip.csr 133195 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_SET ns_noc_io_pcie_soc_ip.csr 133206 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 133219 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_SET ns_noc_io_pcie_soc_ip.csr 133233 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_SET ns_noc_io_pcie_soc_ip.csr 133249 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_SET ns_noc_io_pcie_soc_ip.csr 133263 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_SET ns_noc_io_pcie_soc_ip.csr 133274 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_SET ns_noc_io_pcie_soc_ip.csr 133285 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 133298 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_SET ns_noc_io_pcie_soc_ip.csr 133312 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_SET ns_noc_io_pcie_soc_ip.csr 133328 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_SET ns_noc_io_pcie_soc_ip.csr 133342 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_SET ns_noc_io_pcie_soc_ip.csr 133353 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_SET ns_noc_io_pcie_soc_ip.csr 133364 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 133377 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_SET ns_noc_io_pcie_soc_ip.csr 133391 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_SET ns_noc_io_pcie_soc_ip.csr 133407 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_SET ns_noc_io_pcie_soc_ip.csr 133421 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_SET ns_noc_io_pcie_soc_ip.csr 133432 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_SET ns_noc_io_pcie_soc_ip.csr 133443 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rivcs_s router_1_5_5_rivcs_s PCIE_NOC_ROUTER_1_5_5_RIVCS_S_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 133773 R1_5 register rivcs_s 0x40010 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_s This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 133469 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_SET ns_noc_io_pcie_soc_ip.csr 133483 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_SET ns_noc_io_pcie_soc_ip.csr 133499 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_SET ns_noc_io_pcie_soc_ip.csr 133513 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_SET ns_noc_io_pcie_soc_ip.csr 133524 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_SET ns_noc_io_pcie_soc_ip.csr 133535 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 133548 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_SET ns_noc_io_pcie_soc_ip.csr 133562 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_SET ns_noc_io_pcie_soc_ip.csr 133578 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_SET ns_noc_io_pcie_soc_ip.csr 133592 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_SET ns_noc_io_pcie_soc_ip.csr 133603 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_SET ns_noc_io_pcie_soc_ip.csr 133614 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 133627 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_SET ns_noc_io_pcie_soc_ip.csr 133641 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_SET ns_noc_io_pcie_soc_ip.csr 133657 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_SET ns_noc_io_pcie_soc_ip.csr 133671 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_SET ns_noc_io_pcie_soc_ip.csr 133682 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_SET ns_noc_io_pcie_soc_ip.csr 133693 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 133706 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_SET ns_noc_io_pcie_soc_ip.csr 133720 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_SET ns_noc_io_pcie_soc_ip.csr 133736 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_SET ns_noc_io_pcie_soc_ip.csr 133750 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_SET ns_noc_io_pcie_soc_ip.csr 133761 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_SET ns_noc_io_pcie_soc_ip.csr 133772 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rivcs_w router_1_5_5_rivcs_w PCIE_NOC_ROUTER_1_5_5_RIVCS_W_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 134102 R1_5 register rivcs_w 0x40018 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 133798 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_SET ns_noc_io_pcie_soc_ip.csr 133812 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_SET ns_noc_io_pcie_soc_ip.csr 133828 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_SET ns_noc_io_pcie_soc_ip.csr 133842 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_SET ns_noc_io_pcie_soc_ip.csr 133853 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_SET ns_noc_io_pcie_soc_ip.csr 133864 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 133877 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_SET ns_noc_io_pcie_soc_ip.csr 133891 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_SET ns_noc_io_pcie_soc_ip.csr 133907 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_SET ns_noc_io_pcie_soc_ip.csr 133921 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_SET ns_noc_io_pcie_soc_ip.csr 133932 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_SET ns_noc_io_pcie_soc_ip.csr 133943 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 133956 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_SET ns_noc_io_pcie_soc_ip.csr 133970 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_SET ns_noc_io_pcie_soc_ip.csr 133986 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_SET ns_noc_io_pcie_soc_ip.csr 134000 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_SET ns_noc_io_pcie_soc_ip.csr 134011 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_SET ns_noc_io_pcie_soc_ip.csr 134022 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 134035 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_SET ns_noc_io_pcie_soc_ip.csr 134049 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_SET ns_noc_io_pcie_soc_ip.csr 134065 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_SET ns_noc_io_pcie_soc_ip.csr 134079 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_SET ns_noc_io_pcie_soc_ip.csr 134090 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_SET ns_noc_io_pcie_soc_ip.csr 134101 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rivcs_i router_1_5_5_rivcs_i PCIE_NOC_ROUTER_1_5_5_RIVCS_I_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 134431 R1_5 register rivcs_i 0x40028 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 134127 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_SET ns_noc_io_pcie_soc_ip.csr 134141 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_SET ns_noc_io_pcie_soc_ip.csr 134157 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_SET ns_noc_io_pcie_soc_ip.csr 134171 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_SET ns_noc_io_pcie_soc_ip.csr 134182 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_SET ns_noc_io_pcie_soc_ip.csr 134193 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 134206 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_SET ns_noc_io_pcie_soc_ip.csr 134220 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_SET ns_noc_io_pcie_soc_ip.csr 134236 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_SET ns_noc_io_pcie_soc_ip.csr 134250 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_SET ns_noc_io_pcie_soc_ip.csr 134261 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_SET ns_noc_io_pcie_soc_ip.csr 134272 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 134285 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_SET ns_noc_io_pcie_soc_ip.csr 134299 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_SET ns_noc_io_pcie_soc_ip.csr 134315 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_SET ns_noc_io_pcie_soc_ip.csr 134329 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_SET ns_noc_io_pcie_soc_ip.csr 134340 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_SET ns_noc_io_pcie_soc_ip.csr 134351 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 134364 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_SET ns_noc_io_pcie_soc_ip.csr 134378 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_SET ns_noc_io_pcie_soc_ip.csr 134394 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_SET ns_noc_io_pcie_soc_ip.csr 134408 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_SET ns_noc_io_pcie_soc_ip.csr 134419 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_SET ns_noc_io_pcie_soc_ip.csr 134430 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rivcs_j router_1_5_5_rivcs_j PCIE_NOC_ROUTER_1_5_5_RIVCS_J_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 134760 R1_5 register rivcs_j 0x40030 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 134456 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_SET ns_noc_io_pcie_soc_ip.csr 134470 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_SET ns_noc_io_pcie_soc_ip.csr 134486 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_SET ns_noc_io_pcie_soc_ip.csr 134500 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_SET ns_noc_io_pcie_soc_ip.csr 134511 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_SET ns_noc_io_pcie_soc_ip.csr 134522 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 134535 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_SET ns_noc_io_pcie_soc_ip.csr 134549 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_SET ns_noc_io_pcie_soc_ip.csr 134565 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_SET ns_noc_io_pcie_soc_ip.csr 134579 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_SET ns_noc_io_pcie_soc_ip.csr 134590 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_SET ns_noc_io_pcie_soc_ip.csr 134601 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 134614 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_SET ns_noc_io_pcie_soc_ip.csr 134628 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_SET ns_noc_io_pcie_soc_ip.csr 134644 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_SET ns_noc_io_pcie_soc_ip.csr 134658 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_SET ns_noc_io_pcie_soc_ip.csr 134669 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_SET ns_noc_io_pcie_soc_ip.csr 134680 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 134693 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_SET ns_noc_io_pcie_soc_ip.csr 134707 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_SET ns_noc_io_pcie_soc_ip.csr 134723 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_SET ns_noc_io_pcie_soc_ip.csr 134737 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_SET ns_noc_io_pcie_soc_ip.csr 134748 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_SET ns_noc_io_pcie_soc_ip.csr 134759 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rivcs_k router_1_5_5_rivcs_k PCIE_NOC_ROUTER_1_5_5_RIVCS_K_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OFFSET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 135089 R1_5 register rivcs_k 0x40038 R 0x00000000 Pcie_noc_router_1_5_5_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 134785 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_SET ns_noc_io_pcie_soc_ip.csr 134799 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_SET ns_noc_io_pcie_soc_ip.csr 134815 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_SET ns_noc_io_pcie_soc_ip.csr 134829 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_SET ns_noc_io_pcie_soc_ip.csr 134840 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_SET ns_noc_io_pcie_soc_ip.csr 134851 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 134864 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_SET ns_noc_io_pcie_soc_ip.csr 134878 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_SET ns_noc_io_pcie_soc_ip.csr 134894 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_SET ns_noc_io_pcie_soc_ip.csr 134908 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_SET ns_noc_io_pcie_soc_ip.csr 134919 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_SET ns_noc_io_pcie_soc_ip.csr 134930 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 134943 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_SET ns_noc_io_pcie_soc_ip.csr 134957 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_SET ns_noc_io_pcie_soc_ip.csr 134973 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_SET ns_noc_io_pcie_soc_ip.csr 134987 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_SET ns_noc_io_pcie_soc_ip.csr 134998 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_SET ns_noc_io_pcie_soc_ip.csr 135009 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 135022 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_SET ns_noc_io_pcie_soc_ip.csr 135036 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_SET ns_noc_io_pcie_soc_ip.csr 135052 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_SET ns_noc_io_pcie_soc_ip.csr 135066 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_SET ns_noc_io_pcie_soc_ip.csr 135077 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_MSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_LSB PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_RANGE PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_RESET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_GET PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_SET ns_noc_io_pcie_soc_ip.csr 135088 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_5_5_rovcs_h router_1_5_5_rovcs_h PCIE_NOC_ROUTER_1_5_5_ROVCS_H_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_H_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 135350 R1_5 register rovcs_h 0x40040 R 0x00000101 Pcie_noc_router_1_5_5_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_SET ns_noc_io_pcie_soc_ip.csr 135113 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_SET ns_noc_io_pcie_soc_ip.csr 135127 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_SET ns_noc_io_pcie_soc_ip.csr 135142 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 135153 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 135163 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_SET ns_noc_io_pcie_soc_ip.csr 135175 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_SET ns_noc_io_pcie_soc_ip.csr 135189 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_SET ns_noc_io_pcie_soc_ip.csr 135204 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 135215 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 135225 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_SET ns_noc_io_pcie_soc_ip.csr 135237 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_SET ns_noc_io_pcie_soc_ip.csr 135251 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_SET ns_noc_io_pcie_soc_ip.csr 135266 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 135277 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 135287 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_SET ns_noc_io_pcie_soc_ip.csr 135299 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_SET ns_noc_io_pcie_soc_ip.csr 135313 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_SET ns_noc_io_pcie_soc_ip.csr 135328 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 135339 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 135349 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_rovcs_e router_1_5_5_rovcs_e PCIE_NOC_ROUTER_1_5_5_ROVCS_E_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_E_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 135611 R1_5 register rovcs_e 0x40048 R 0x00000001 Pcie_noc_router_1_5_5_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_SET ns_noc_io_pcie_soc_ip.csr 135374 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_SET ns_noc_io_pcie_soc_ip.csr 135388 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_SET ns_noc_io_pcie_soc_ip.csr 135403 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 135414 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 135424 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_SET ns_noc_io_pcie_soc_ip.csr 135436 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_SET ns_noc_io_pcie_soc_ip.csr 135450 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_SET ns_noc_io_pcie_soc_ip.csr 135465 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 135476 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 135486 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_SET ns_noc_io_pcie_soc_ip.csr 135498 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_SET ns_noc_io_pcie_soc_ip.csr 135512 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_SET ns_noc_io_pcie_soc_ip.csr 135527 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 135538 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 135548 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_SET ns_noc_io_pcie_soc_ip.csr 135560 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_SET ns_noc_io_pcie_soc_ip.csr 135574 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_SET ns_noc_io_pcie_soc_ip.csr 135589 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 135600 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 135610 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_rovcs_s router_1_5_5_rovcs_s PCIE_NOC_ROUTER_1_5_5_ROVCS_S_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_S_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 135872 R1_5 register rovcs_s 0x40050 R 0x00000001 Pcie_noc_router_1_5_5_rovcs_s This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_SET ns_noc_io_pcie_soc_ip.csr 135635 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_SET ns_noc_io_pcie_soc_ip.csr 135649 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_SET ns_noc_io_pcie_soc_ip.csr 135664 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 135675 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 135685 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_SET ns_noc_io_pcie_soc_ip.csr 135697 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_SET ns_noc_io_pcie_soc_ip.csr 135711 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_SET ns_noc_io_pcie_soc_ip.csr 135726 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 135737 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 135747 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_SET ns_noc_io_pcie_soc_ip.csr 135759 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_SET ns_noc_io_pcie_soc_ip.csr 135773 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_SET ns_noc_io_pcie_soc_ip.csr 135788 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 135799 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 135809 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_SET ns_noc_io_pcie_soc_ip.csr 135821 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_SET ns_noc_io_pcie_soc_ip.csr 135835 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_SET ns_noc_io_pcie_soc_ip.csr 135850 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 135861 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 135871 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_rovcs_w router_1_5_5_rovcs_w PCIE_NOC_ROUTER_1_5_5_ROVCS_W_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_W_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 136133 R1_5 register rovcs_w 0x40058 R 0x00000101 Pcie_noc_router_1_5_5_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_SET ns_noc_io_pcie_soc_ip.csr 135896 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_SET ns_noc_io_pcie_soc_ip.csr 135910 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_SET ns_noc_io_pcie_soc_ip.csr 135925 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 135936 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 135946 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_SET ns_noc_io_pcie_soc_ip.csr 135958 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_SET ns_noc_io_pcie_soc_ip.csr 135972 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_SET ns_noc_io_pcie_soc_ip.csr 135987 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 135998 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 136008 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_SET ns_noc_io_pcie_soc_ip.csr 136020 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_SET ns_noc_io_pcie_soc_ip.csr 136034 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_SET ns_noc_io_pcie_soc_ip.csr 136049 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 136060 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 136070 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_SET ns_noc_io_pcie_soc_ip.csr 136082 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_SET ns_noc_io_pcie_soc_ip.csr 136096 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_SET ns_noc_io_pcie_soc_ip.csr 136111 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 136122 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 136132 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_rovcs_i router_1_5_5_rovcs_i PCIE_NOC_ROUTER_1_5_5_ROVCS_I_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_I_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 136394 R1_5 register rovcs_i 0x40068 R 0x00000001 Pcie_noc_router_1_5_5_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_SET ns_noc_io_pcie_soc_ip.csr 136157 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_SET ns_noc_io_pcie_soc_ip.csr 136171 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_SET ns_noc_io_pcie_soc_ip.csr 136186 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 136197 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 136207 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_SET ns_noc_io_pcie_soc_ip.csr 136219 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_SET ns_noc_io_pcie_soc_ip.csr 136233 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_SET ns_noc_io_pcie_soc_ip.csr 136248 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 136259 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 136269 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_SET ns_noc_io_pcie_soc_ip.csr 136281 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_SET ns_noc_io_pcie_soc_ip.csr 136295 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_SET ns_noc_io_pcie_soc_ip.csr 136310 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 136321 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 136331 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_SET ns_noc_io_pcie_soc_ip.csr 136343 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_SET ns_noc_io_pcie_soc_ip.csr 136357 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_SET ns_noc_io_pcie_soc_ip.csr 136372 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 136383 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 136393 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_rovcs_j router_1_5_5_rovcs_j PCIE_NOC_ROUTER_1_5_5_ROVCS_J_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_J_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 136655 R1_5 register rovcs_j 0x40070 R 0x00000001 Pcie_noc_router_1_5_5_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_SET ns_noc_io_pcie_soc_ip.csr 136418 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_SET ns_noc_io_pcie_soc_ip.csr 136432 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_SET ns_noc_io_pcie_soc_ip.csr 136447 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 136458 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 136468 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_SET ns_noc_io_pcie_soc_ip.csr 136480 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_SET ns_noc_io_pcie_soc_ip.csr 136494 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_SET ns_noc_io_pcie_soc_ip.csr 136509 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 136520 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 136530 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_SET ns_noc_io_pcie_soc_ip.csr 136542 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_SET ns_noc_io_pcie_soc_ip.csr 136556 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_SET ns_noc_io_pcie_soc_ip.csr 136571 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 136582 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 136592 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_SET ns_noc_io_pcie_soc_ip.csr 136604 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_SET ns_noc_io_pcie_soc_ip.csr 136618 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_SET ns_noc_io_pcie_soc_ip.csr 136633 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 136644 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 136654 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_rovcs_k router_1_5_5_rovcs_k PCIE_NOC_ROUTER_1_5_5_ROVCS_K_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROVCS_K_OFFSET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 136916 R1_5 register rovcs_k 0x40078 R 0x00000101 Pcie_noc_router_1_5_5_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_SET ns_noc_io_pcie_soc_ip.csr 136679 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_SET ns_noc_io_pcie_soc_ip.csr 136693 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_SET ns_noc_io_pcie_soc_ip.csr 136708 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 136719 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 136729 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_SET ns_noc_io_pcie_soc_ip.csr 136741 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_SET ns_noc_io_pcie_soc_ip.csr 136755 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_SET ns_noc_io_pcie_soc_ip.csr 136770 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 136781 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 136791 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_SET ns_noc_io_pcie_soc_ip.csr 136803 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_SET ns_noc_io_pcie_soc_ip.csr 136817 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_SET ns_noc_io_pcie_soc_ip.csr 136832 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 136843 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 136853 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_SET ns_noc_io_pcie_soc_ip.csr 136865 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_SET ns_noc_io_pcie_soc_ip.csr 136879 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_SET ns_noc_io_pcie_soc_ip.csr 136894 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 136905 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_MSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_LSB PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_RANGE PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_RESET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_GET PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 136915 UNSD_3 31 28 0x0 R register pcie_noc.router_1_5_5_re router_1_5_5_re PCIE_NOC_ROUTER_1_5_5_RE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RE_OFFSET PCIE_NOC_ROUTER_1_5_5_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137090 R1_5 register re 0x40080 R/W 0x00000000 Pcie_noc_router_1_5_5_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_1_5_5_RE_OVFI_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_OVFI_MSB PCIE_NOC_ROUTER_1_5_5_RE_OVFI_LSB PCIE_NOC_ROUTER_1_5_5_RE_OVFI_RANGE PCIE_NOC_ROUTER_1_5_5_RE_OVFI_RESET PCIE_NOC_ROUTER_1_5_5_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_OVFI_GET PCIE_NOC_ROUTER_1_5_5_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 136942 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 136953 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_1_5_5_RE_OVFO_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_OVFO_MSB PCIE_NOC_ROUTER_1_5_5_RE_OVFO_LSB PCIE_NOC_ROUTER_1_5_5_RE_OVFO_RANGE PCIE_NOC_ROUTER_1_5_5_RE_OVFO_RESET PCIE_NOC_ROUTER_1_5_5_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_OVFO_GET PCIE_NOC_ROUTER_1_5_5_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 136967 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 136978 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_1_5_5_RE_PGE_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_PGE_MSB PCIE_NOC_ROUTER_1_5_5_RE_PGE_LSB PCIE_NOC_ROUTER_1_5_5_RE_PGE_RANGE PCIE_NOC_ROUTER_1_5_5_RE_PGE_RESET PCIE_NOC_ROUTER_1_5_5_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_PGE_GET PCIE_NOC_ROUTER_1_5_5_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 136990 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_1_5_5_RE_NLU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_NLU_MSB PCIE_NOC_ROUTER_1_5_5_RE_NLU_LSB PCIE_NOC_ROUTER_1_5_5_RE_NLU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_NLU_RESET PCIE_NOC_ROUTER_1_5_5_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_NLU_GET PCIE_NOC_ROUTER_1_5_5_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 137001 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_1_5_5_RE_ELU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_ELU_MSB PCIE_NOC_ROUTER_1_5_5_RE_ELU_LSB PCIE_NOC_ROUTER_1_5_5_RE_ELU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_ELU_RESET PCIE_NOC_ROUTER_1_5_5_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_ELU_GET PCIE_NOC_ROUTER_1_5_5_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 137012 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_1_5_5_RE_WLU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_WLU_MSB PCIE_NOC_ROUTER_1_5_5_RE_WLU_LSB PCIE_NOC_ROUTER_1_5_5_RE_WLU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_WLU_RESET PCIE_NOC_ROUTER_1_5_5_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_WLU_GET PCIE_NOC_ROUTER_1_5_5_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 137023 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_1_5_5_RE_SLU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_SLU_MSB PCIE_NOC_ROUTER_1_5_5_RE_SLU_LSB PCIE_NOC_ROUTER_1_5_5_RE_SLU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_SLU_RESET PCIE_NOC_ROUTER_1_5_5_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_SLU_GET PCIE_NOC_ROUTER_1_5_5_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 137034 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_1_5_5_RE_HLU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_HLU_MSB PCIE_NOC_ROUTER_1_5_5_RE_HLU_LSB PCIE_NOC_ROUTER_1_5_5_RE_HLU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_HLU_RESET PCIE_NOC_ROUTER_1_5_5_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_HLU_GET PCIE_NOC_ROUTER_1_5_5_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 137045 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_1_5_5_RE_ILU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_ILU_MSB PCIE_NOC_ROUTER_1_5_5_RE_ILU_LSB PCIE_NOC_ROUTER_1_5_5_RE_ILU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_ILU_RESET PCIE_NOC_ROUTER_1_5_5_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_ILU_GET PCIE_NOC_ROUTER_1_5_5_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 137056 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_1_5_5_RE_JLU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_JLU_MSB PCIE_NOC_ROUTER_1_5_5_RE_JLU_LSB PCIE_NOC_ROUTER_1_5_5_RE_JLU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_JLU_RESET PCIE_NOC_ROUTER_1_5_5_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_JLU_GET PCIE_NOC_ROUTER_1_5_5_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 137067 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_1_5_5_RE_KLU_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_KLU_MSB PCIE_NOC_ROUTER_1_5_5_RE_KLU_LSB PCIE_NOC_ROUTER_1_5_5_RE_KLU_RANGE PCIE_NOC_ROUTER_1_5_5_RE_KLU_RESET PCIE_NOC_ROUTER_1_5_5_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_KLU_GET PCIE_NOC_ROUTER_1_5_5_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 137078 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 137089 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_1_5_5_rem router_1_5_5_rem PCIE_NOC_ROUTER_1_5_5_REM_ADDRESS PCIE_NOC_ROUTER_1_5_5_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_REM_OFFSET PCIE_NOC_ROUTER_1_5_5_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137263 R1_5 register rem 0x40088 R/W 0x0001fe00 Pcie_noc_router_1_5_5_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_MSB PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_LSB PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_RANGE PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_RESET PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_GET PCIE_NOC_ROUTER_1_5_5_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 137116 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 137127 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_MSB PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_LSB PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_RANGE PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_RESET PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_GET PCIE_NOC_ROUTER_1_5_5_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 137141 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 137152 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_1_5_5_REM_PGM_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_PGM_MSB PCIE_NOC_ROUTER_1_5_5_REM_PGM_LSB PCIE_NOC_ROUTER_1_5_5_REM_PGM_RANGE PCIE_NOC_ROUTER_1_5_5_REM_PGM_RESET PCIE_NOC_ROUTER_1_5_5_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_PGM_GET PCIE_NOC_ROUTER_1_5_5_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 137163 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_1_5_5_REM_MN_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MN_MSB PCIE_NOC_ROUTER_1_5_5_REM_MN_LSB PCIE_NOC_ROUTER_1_5_5_REM_MN_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MN_RESET PCIE_NOC_ROUTER_1_5_5_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MN_GET PCIE_NOC_ROUTER_1_5_5_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 137174 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_1_5_5_REM_ME_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_ME_MSB PCIE_NOC_ROUTER_1_5_5_REM_ME_LSB PCIE_NOC_ROUTER_1_5_5_REM_ME_RANGE PCIE_NOC_ROUTER_1_5_5_REM_ME_RESET PCIE_NOC_ROUTER_1_5_5_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_ME_GET PCIE_NOC_ROUTER_1_5_5_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 137185 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_1_5_5_REM_MW_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MW_MSB PCIE_NOC_ROUTER_1_5_5_REM_MW_LSB PCIE_NOC_ROUTER_1_5_5_REM_MW_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MW_RESET PCIE_NOC_ROUTER_1_5_5_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MW_GET PCIE_NOC_ROUTER_1_5_5_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 137196 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_1_5_5_REM_MS_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MS_MSB PCIE_NOC_ROUTER_1_5_5_REM_MS_LSB PCIE_NOC_ROUTER_1_5_5_REM_MS_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MS_RESET PCIE_NOC_ROUTER_1_5_5_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MS_GET PCIE_NOC_ROUTER_1_5_5_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 137207 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_1_5_5_REM_MH_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MH_MSB PCIE_NOC_ROUTER_1_5_5_REM_MH_LSB PCIE_NOC_ROUTER_1_5_5_REM_MH_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MH_RESET PCIE_NOC_ROUTER_1_5_5_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MH_GET PCIE_NOC_ROUTER_1_5_5_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 137218 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_1_5_5_REM_MI_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MI_MSB PCIE_NOC_ROUTER_1_5_5_REM_MI_LSB PCIE_NOC_ROUTER_1_5_5_REM_MI_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MI_RESET PCIE_NOC_ROUTER_1_5_5_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MI_GET PCIE_NOC_ROUTER_1_5_5_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 137229 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_1_5_5_REM_MJ_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MJ_MSB PCIE_NOC_ROUTER_1_5_5_REM_MJ_LSB PCIE_NOC_ROUTER_1_5_5_REM_MJ_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MJ_RESET PCIE_NOC_ROUTER_1_5_5_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MJ_GET PCIE_NOC_ROUTER_1_5_5_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 137240 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_1_5_5_REM_MK_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_MK_MSB PCIE_NOC_ROUTER_1_5_5_REM_MK_LSB PCIE_NOC_ROUTER_1_5_5_REM_MK_RANGE PCIE_NOC_ROUTER_1_5_5_REM_MK_RESET PCIE_NOC_ROUTER_1_5_5_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_MK_GET PCIE_NOC_ROUTER_1_5_5_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 137251 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 137262 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_1_5_5_recc router_1_5_5_recc PCIE_NOC_ROUTER_1_5_5_RECC_ADDRESS PCIE_NOC_ROUTER_1_5_5_RECC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RECC_OFFSET PCIE_NOC_ROUTER_1_5_5_RECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137348 R1_5 register recc 0x40090 R/W 0x00000000 Pcie_noc_router_1_5_5_recc This register is used to select which hardware events will increment the event counter. false false false false IVC PCIE_NOC_ROUTER_1_5_5_RECC_IVC_WIDTH PCIE_NOC_ROUTER_1_5_5_RECC_IVC_MSB PCIE_NOC_ROUTER_1_5_5_RECC_IVC_LSB PCIE_NOC_ROUTER_1_5_5_RECC_IVC_RANGE PCIE_NOC_ROUTER_1_5_5_RECC_IVC_RESET PCIE_NOC_ROUTER_1_5_5_RECC_IVC_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RECC_IVC_GET PCIE_NOC_ROUTER_1_5_5_RECC_IVC_SET ns_noc_io_pcie_soc_ip.csr 137284 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_WIDTH PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_MSB PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_LSB PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_RANGE PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_RESET PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_GET PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_SET ns_noc_io_pcie_soc_ip.csr 137295 UNSD_3_2 3 2 0x0 R INP PCIE_NOC_ROUTER_1_5_5_RECC_INP_WIDTH PCIE_NOC_ROUTER_1_5_5_RECC_INP_MSB PCIE_NOC_ROUTER_1_5_5_RECC_INP_LSB PCIE_NOC_ROUTER_1_5_5_RECC_INP_RANGE PCIE_NOC_ROUTER_1_5_5_RECC_INP_RESET PCIE_NOC_ROUTER_1_5_5_RECC_INP_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RECC_INP_GET PCIE_NOC_ROUTER_1_5_5_RECC_INP_SET ns_noc_io_pcie_soc_ip.csr 137306 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_GET PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 137317 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_1_5_5_RECC_EVT_WIDTH PCIE_NOC_ROUTER_1_5_5_RECC_EVT_MSB PCIE_NOC_ROUTER_1_5_5_RECC_EVT_LSB PCIE_NOC_ROUTER_1_5_5_RECC_EVT_RANGE PCIE_NOC_ROUTER_1_5_5_RECC_EVT_RESET PCIE_NOC_ROUTER_1_5_5_RECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RECC_EVT_GET PCIE_NOC_ROUTER_1_5_5_RECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 137336 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_WIDTH PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_MSB PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_LSB PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_RANGE PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_RESET PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_GET PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_SET ns_noc_io_pcie_soc_ip.csr 137347 UNSD_31_10 31 10 0x000000 R register pcie_noc.router_1_5_5_rec router_1_5_5_rec PCIE_NOC_ROUTER_1_5_5_REC_ADDRESS PCIE_NOC_ROUTER_1_5_5_REC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_REC_OFFSET PCIE_NOC_ROUTER_1_5_5_REC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137373 R1_5 register rec 0x40098 R/W 0x00000000 Pcie_noc_router_1_5_5_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_GET PCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 137372 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_1_5_5_id router_1_5_5_id PCIE_NOC_ROUTER_1_5_5_ID_ADDRESS PCIE_NOC_ROUTER_1_5_5_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ID_OFFSET PCIE_NOC_ROUTER_1_5_5_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137442 R1_5 register id 0x400A0 R 0x010000a1 Pcie_noc_router_1_5_5_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_1_5_5_ID_LAYER_WIDTH PCIE_NOC_ROUTER_1_5_5_ID_LAYER_MSB PCIE_NOC_ROUTER_1_5_5_ID_LAYER_LSB PCIE_NOC_ROUTER_1_5_5_ID_LAYER_RANGE PCIE_NOC_ROUTER_1_5_5_ID_LAYER_RESET PCIE_NOC_ROUTER_1_5_5_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ID_LAYER_GET PCIE_NOC_ROUTER_1_5_5_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 137398 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x01 R POS PCIE_NOC_ROUTER_1_5_5_ID_POS_WIDTH PCIE_NOC_ROUTER_1_5_5_ID_POS_MSB PCIE_NOC_ROUTER_1_5_5_ID_POS_LSB PCIE_NOC_ROUTER_1_5_5_ID_POS_RANGE PCIE_NOC_ROUTER_1_5_5_ID_POS_RESET PCIE_NOC_ROUTER_1_5_5_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ID_POS_GET PCIE_NOC_ROUTER_1_5_5_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 137409 POS 16-bit position ID of this router in the NoC 20 5 0x0005 R ZERO PCIE_NOC_ROUTER_1_5_5_ID_ZERO_WIDTH PCIE_NOC_ROUTER_1_5_5_ID_ZERO_MSB PCIE_NOC_ROUTER_1_5_5_ID_ZERO_LSB PCIE_NOC_ROUTER_1_5_5_ID_ZERO_RANGE PCIE_NOC_ROUTER_1_5_5_ID_ZERO_RESET PCIE_NOC_ROUTER_1_5_5_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ID_ZERO_GET PCIE_NOC_ROUTER_1_5_5_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 137420 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_1_5_5_ID_ONE_WIDTH PCIE_NOC_ROUTER_1_5_5_ID_ONE_MSB PCIE_NOC_ROUTER_1_5_5_ID_ONE_LSB PCIE_NOC_ROUTER_1_5_5_ID_ONE_RANGE PCIE_NOC_ROUTER_1_5_5_ID_ONE_RESET PCIE_NOC_ROUTER_1_5_5_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ID_ONE_GET PCIE_NOC_ROUTER_1_5_5_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 137431 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 137441 UNSD_31_25 31 25 0x00 R register pcie_noc.router_1_5_5_rcgc router_1_5_5_rcgc PCIE_NOC_ROUTER_1_5_5_RCGC_ADDRESS PCIE_NOC_ROUTER_1_5_5_RCGC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RCGC_OFFSET PCIE_NOC_ROUTER_1_5_5_RCGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137468 R1_5 register rcgc 0x400A8 R/W 0x00000064 Pcie_noc_router_1_5_5_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_GET PCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 137467 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register pcie_noc.router_1_5_5_rcgo router_1_5_5_rcgo PCIE_NOC_ROUTER_1_5_5_RCGO_ADDRESS PCIE_NOC_ROUTER_1_5_5_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_RCGO_OFFSET PCIE_NOC_ROUTER_1_5_5_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137507 R1_5 register rcgo 0x400B0 R/W 0x00000000 Pcie_noc_router_1_5_5_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_MSB PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_LSB PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_RANGE PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_RESET PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_GET PCIE_NOC_ROUTER_1_5_5_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 137495 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 137506 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_1_5_5_p1_rperr router_1_5_5_p1_rperr PCIE_NOC_ROUTER_1_5_5_P1_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P1_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P1_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 137794 R1_5 register p1_rperr 0x400C0 R/W 0x00000000 Pcie_noc_router_1_5_5_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 137550 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 137561 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 137572 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 137583 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 137594 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 137605 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 137616 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 137627 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 137639 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 137650 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 137661 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 137672 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 137684 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 137695 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 137707 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 137719 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 137732 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 137744 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 137756 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 137768 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 137781 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 137793 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p2_rperr router_1_5_5_p2_rperr PCIE_NOC_ROUTER_1_5_5_P2_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P2_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P2_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 138085 R1_5 register p2_rperr 0x400C8 R/W 0x00000000 Pcie_noc_router_1_5_5_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 137837 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 137848 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 137859 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 137870 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 137881 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 137892 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 137903 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 137914 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 137926 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 137937 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 137949 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 137961 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 137974 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 137986 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 137998 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 138010 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 138023 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 138035 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 138047 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 138059 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 138072 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 138084 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p3_rperr router_1_5_5_p3_rperr PCIE_NOC_ROUTER_1_5_5_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P3_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 138376 R1_5 register p3_rperr 0x400D0 R/W 0x00000000 Pcie_noc_router_1_5_5_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 138128 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 138139 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 138150 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 138161 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 138172 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 138183 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 138194 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 138205 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 138217 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 138228 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 138240 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 138252 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 138265 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 138277 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 138289 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 138301 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 138314 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 138326 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 138338 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 138350 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 138363 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 138375 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p4_rperr router_1_5_5_p4_rperr PCIE_NOC_ROUTER_1_5_5_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P4_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 138667 R1_5 register p4_rperr 0x400D8 R/W 0x00000000 Pcie_noc_router_1_5_5_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 138419 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 138430 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 138441 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 138452 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 138463 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 138474 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 138485 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 138496 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 138508 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 138519 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 138531 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 138543 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 138556 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 138568 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 138580 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 138592 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 138605 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 138617 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 138629 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 138641 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 138654 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 138666 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p5_rperr router_1_5_5_p5_rperr PCIE_NOC_ROUTER_1_5_5_P5_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P5_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P5_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 138958 R1_5 register p5_rperr 0x400E0 R/W 0x00000000 Pcie_noc_router_1_5_5_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 138710 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 138721 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 138732 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 138743 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 138754 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 138765 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 138776 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 138787 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 138799 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 138810 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 138822 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 138834 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 138847 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 138859 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 138871 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 138883 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 138896 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 138908 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 138920 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 138932 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 138945 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 138957 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p6_rperr router_1_5_5_p6_rperr PCIE_NOC_ROUTER_1_5_5_P6_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P6_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P6_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 139249 R1_5 register p6_rperr 0x400E8 R/W 0x00000000 Pcie_noc_router_1_5_5_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 139001 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 139012 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 139023 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 139034 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 139045 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 139056 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 139067 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 139078 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 139090 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 139101 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 139113 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 139125 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 139138 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 139150 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 139162 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 139174 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 139187 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 139199 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 139211 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 139223 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 139236 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 139248 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p7_rperr router_1_5_5_p7_rperr PCIE_NOC_ROUTER_1_5_5_P7_RPERR_ADDRESS PCIE_NOC_ROUTER_1_5_5_P7_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P7_RPERR_OFFSET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 139540 R1_5 register p7_rperr 0x400F0 R/W 0x00000000 Pcie_noc_router_1_5_5_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 139292 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 139303 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 139314 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 139325 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 139336 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 139347 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 139358 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 139369 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 139381 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 139392 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 139404 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 139416 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 139429 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 139441 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 139453 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 139465 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 139478 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 139490 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 139502 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 139514 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 139527 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 139539 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_5_5_p1_rperrm router_1_5_5_p1_rperrm PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 139798 R1_5 register p1_rperrm 0x40100 R/W 0x00000000 Pcie_noc_router_1_5_5_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 139562 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 139573 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 139584 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 139595 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 139606 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 139617 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 139628 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 139639 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 139651 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 139662 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 139673 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 139684 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 139696 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 139707 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 139718 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 139729 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 139741 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 139752 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 139763 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 139774 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 139786 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 139797 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_p2_rperrm router_1_5_5_p2_rperrm PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 140056 R1_5 register p2_rperrm 0x40108 R/W 0x00000000 Pcie_noc_router_1_5_5_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 139820 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 139831 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 139842 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 139853 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 139864 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 139875 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 139886 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 139897 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 139909 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 139920 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 139931 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 139942 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 139954 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 139965 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 139976 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 139987 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 139999 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 140010 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 140021 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 140032 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 140044 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 140055 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_p3_rperrm router_1_5_5_p3_rperrm PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 140314 R1_5 register p3_rperrm 0x40110 R/W 0x00000000 Pcie_noc_router_1_5_5_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 140078 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 140089 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 140100 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 140111 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 140122 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 140133 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 140144 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 140155 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 140167 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 140178 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 140189 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 140200 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 140212 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 140223 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 140234 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 140245 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 140257 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 140268 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 140279 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 140290 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 140302 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 140313 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_p4_rperrm router_1_5_5_p4_rperrm PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 140572 R1_5 register p4_rperrm 0x40118 R/W 0x00000000 Pcie_noc_router_1_5_5_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 140336 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 140347 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 140358 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 140369 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 140380 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 140391 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 140402 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 140413 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 140425 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 140436 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 140447 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 140458 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 140470 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 140481 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 140492 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 140503 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 140515 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 140526 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 140537 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 140548 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 140560 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 140571 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_p5_rperrm router_1_5_5_p5_rperrm PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 140830 R1_5 register p5_rperrm 0x40120 R/W 0x00000000 Pcie_noc_router_1_5_5_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 140594 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 140605 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 140616 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 140627 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 140638 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 140649 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 140660 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 140671 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 140683 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 140694 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 140705 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 140716 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 140728 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 140739 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 140750 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 140761 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 140773 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 140784 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 140795 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 140806 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 140818 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 140829 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_p6_rperrm router_1_5_5_p6_rperrm PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 141088 R1_5 register p6_rperrm 0x40128 R/W 0x00000000 Pcie_noc_router_1_5_5_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 140852 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 140863 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 140874 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 140885 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 140896 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 140907 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 140918 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 140929 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 140941 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 140952 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 140963 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 140974 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 140986 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 140997 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 141008 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 141019 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 141031 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 141042 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 141053 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 141064 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 141076 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 141087 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_p7_rperrm router_1_5_5_p7_rperrm PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_OFFSET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 141346 R1_5 register p7_rperrm 0x40130 R/W 0x00000000 Pcie_noc_router_1_5_5_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 141110 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 141121 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 141132 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 141143 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 141154 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 141165 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 141176 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 141187 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 141199 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 141210 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 141221 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 141232 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 141244 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 141255 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 141266 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 141277 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 141289 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 141300 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 141311 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 141322 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 141334 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 141345 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_5_5_roecc router_1_5_5_roecc PCIE_NOC_ROUTER_1_5_5_ROECC_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROECC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROECC_OFFSET PCIE_NOC_ROUTER_1_5_5_ROECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 141419 R1_5 register roecc 0x40138 R/W 0x00000000 Pcie_noc_router_1_5_5_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_WIDTH PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_MSB PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_LSB PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_RANGE PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_RESET PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_GET PCIE_NOC_ROUTER_1_5_5_ROECC_OVC_SET ns_noc_io_pcie_soc_ip.csr 141364 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP PCIE_NOC_ROUTER_1_5_5_ROECC_OP_WIDTH PCIE_NOC_ROUTER_1_5_5_ROECC_OP_MSB PCIE_NOC_ROUTER_1_5_5_ROECC_OP_LSB PCIE_NOC_ROUTER_1_5_5_ROECC_OP_RANGE PCIE_NOC_ROUTER_1_5_5_ROECC_OP_RESET PCIE_NOC_ROUTER_1_5_5_ROECC_OP_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROECC_OP_GET PCIE_NOC_ROUTER_1_5_5_ROECC_OP_SET ns_noc_io_pcie_soc_ip.csr 141375 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_GET PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 141386 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_WIDTH PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_MSB PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_LSB PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_RANGE PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_RESET PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_GET PCIE_NOC_ROUTER_1_5_5_ROECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 141407 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_WIDTH PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_MSB PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_LSB PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_RANGE PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_RESET PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_GET PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_SET ns_noc_io_pcie_soc_ip.csr 141418 UNSD_31_11 31 11 0x000000 R register pcie_noc.router_1_5_5_roec router_1_5_5_roec PCIE_NOC_ROUTER_1_5_5_ROEC_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROEC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_5_5_ROEC_OFFSET PCIE_NOC_ROUTER_1_5_5_ROEC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 141444 R1_5 register roec 0x40140 R/W 0x00000000 Pcie_noc_router_1_5_5_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_GET PCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 141443 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_1_6_6_rivcs_h router_1_6_6_rivcs_h PCIE_NOC_ROUTER_1_6_6_RIVCS_H_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 141773 R1_6 register rivcs_h 0x44000 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_h This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 141469 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_SET ns_noc_io_pcie_soc_ip.csr 141483 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_SET ns_noc_io_pcie_soc_ip.csr 141499 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_SET ns_noc_io_pcie_soc_ip.csr 141513 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_SET ns_noc_io_pcie_soc_ip.csr 141524 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_SET ns_noc_io_pcie_soc_ip.csr 141535 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 141548 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_SET ns_noc_io_pcie_soc_ip.csr 141562 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_SET ns_noc_io_pcie_soc_ip.csr 141578 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_SET ns_noc_io_pcie_soc_ip.csr 141592 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_SET ns_noc_io_pcie_soc_ip.csr 141603 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_SET ns_noc_io_pcie_soc_ip.csr 141614 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 141627 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_SET ns_noc_io_pcie_soc_ip.csr 141641 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_SET ns_noc_io_pcie_soc_ip.csr 141657 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_SET ns_noc_io_pcie_soc_ip.csr 141671 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_SET ns_noc_io_pcie_soc_ip.csr 141682 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_SET ns_noc_io_pcie_soc_ip.csr 141693 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 141706 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_SET ns_noc_io_pcie_soc_ip.csr 141720 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_SET ns_noc_io_pcie_soc_ip.csr 141736 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_SET ns_noc_io_pcie_soc_ip.csr 141750 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_SET ns_noc_io_pcie_soc_ip.csr 141761 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_SET ns_noc_io_pcie_soc_ip.csr 141772 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_e router_1_6_6_rivcs_e PCIE_NOC_ROUTER_1_6_6_RIVCS_E_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 142102 R1_6 register rivcs_e 0x44008 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_e This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 141798 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_SET ns_noc_io_pcie_soc_ip.csr 141812 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_SET ns_noc_io_pcie_soc_ip.csr 141828 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_SET ns_noc_io_pcie_soc_ip.csr 141842 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_SET ns_noc_io_pcie_soc_ip.csr 141853 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_SET ns_noc_io_pcie_soc_ip.csr 141864 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 141877 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_SET ns_noc_io_pcie_soc_ip.csr 141891 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_SET ns_noc_io_pcie_soc_ip.csr 141907 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_SET ns_noc_io_pcie_soc_ip.csr 141921 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_SET ns_noc_io_pcie_soc_ip.csr 141932 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_SET ns_noc_io_pcie_soc_ip.csr 141943 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 141956 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_SET ns_noc_io_pcie_soc_ip.csr 141970 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_SET ns_noc_io_pcie_soc_ip.csr 141986 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_SET ns_noc_io_pcie_soc_ip.csr 142000 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_SET ns_noc_io_pcie_soc_ip.csr 142011 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_SET ns_noc_io_pcie_soc_ip.csr 142022 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 142035 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_SET ns_noc_io_pcie_soc_ip.csr 142049 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_SET ns_noc_io_pcie_soc_ip.csr 142065 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_SET ns_noc_io_pcie_soc_ip.csr 142079 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_SET ns_noc_io_pcie_soc_ip.csr 142090 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_SET ns_noc_io_pcie_soc_ip.csr 142101 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_s router_1_6_6_rivcs_s PCIE_NOC_ROUTER_1_6_6_RIVCS_S_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 142431 R1_6 register rivcs_s 0x44010 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_s This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 142127 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_SET ns_noc_io_pcie_soc_ip.csr 142141 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_SET ns_noc_io_pcie_soc_ip.csr 142157 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_SET ns_noc_io_pcie_soc_ip.csr 142171 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_SET ns_noc_io_pcie_soc_ip.csr 142182 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_SET ns_noc_io_pcie_soc_ip.csr 142193 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 142206 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_SET ns_noc_io_pcie_soc_ip.csr 142220 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_SET ns_noc_io_pcie_soc_ip.csr 142236 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_SET ns_noc_io_pcie_soc_ip.csr 142250 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_SET ns_noc_io_pcie_soc_ip.csr 142261 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_SET ns_noc_io_pcie_soc_ip.csr 142272 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 142285 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_SET ns_noc_io_pcie_soc_ip.csr 142299 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_SET ns_noc_io_pcie_soc_ip.csr 142315 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_SET ns_noc_io_pcie_soc_ip.csr 142329 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_SET ns_noc_io_pcie_soc_ip.csr 142340 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_SET ns_noc_io_pcie_soc_ip.csr 142351 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 142364 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_SET ns_noc_io_pcie_soc_ip.csr 142378 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_SET ns_noc_io_pcie_soc_ip.csr 142394 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_SET ns_noc_io_pcie_soc_ip.csr 142408 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_SET ns_noc_io_pcie_soc_ip.csr 142419 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_SET ns_noc_io_pcie_soc_ip.csr 142430 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_w router_1_6_6_rivcs_w PCIE_NOC_ROUTER_1_6_6_RIVCS_W_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 142760 R1_6 register rivcs_w 0x44018 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_w This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 142456 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_SET ns_noc_io_pcie_soc_ip.csr 142470 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_SET ns_noc_io_pcie_soc_ip.csr 142486 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_SET ns_noc_io_pcie_soc_ip.csr 142500 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_SET ns_noc_io_pcie_soc_ip.csr 142511 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_SET ns_noc_io_pcie_soc_ip.csr 142522 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 142535 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_SET ns_noc_io_pcie_soc_ip.csr 142549 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_SET ns_noc_io_pcie_soc_ip.csr 142565 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_SET ns_noc_io_pcie_soc_ip.csr 142579 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_SET ns_noc_io_pcie_soc_ip.csr 142590 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_SET ns_noc_io_pcie_soc_ip.csr 142601 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 142614 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_SET ns_noc_io_pcie_soc_ip.csr 142628 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_SET ns_noc_io_pcie_soc_ip.csr 142644 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_SET ns_noc_io_pcie_soc_ip.csr 142658 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_SET ns_noc_io_pcie_soc_ip.csr 142669 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_SET ns_noc_io_pcie_soc_ip.csr 142680 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 142693 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_SET ns_noc_io_pcie_soc_ip.csr 142707 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_SET ns_noc_io_pcie_soc_ip.csr 142723 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_SET ns_noc_io_pcie_soc_ip.csr 142737 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_SET ns_noc_io_pcie_soc_ip.csr 142748 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_SET ns_noc_io_pcie_soc_ip.csr 142759 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_n router_1_6_6_rivcs_n PCIE_NOC_ROUTER_1_6_6_RIVCS_N_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_N_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 143089 R1_6 register rivcs_n 0x44020 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_n This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 142785 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_SET ns_noc_io_pcie_soc_ip.csr 142799 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_SET ns_noc_io_pcie_soc_ip.csr 142815 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_SET ns_noc_io_pcie_soc_ip.csr 142829 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_SET ns_noc_io_pcie_soc_ip.csr 142840 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_SET ns_noc_io_pcie_soc_ip.csr 142851 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 142864 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_SET ns_noc_io_pcie_soc_ip.csr 142878 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_SET ns_noc_io_pcie_soc_ip.csr 142894 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_SET ns_noc_io_pcie_soc_ip.csr 142908 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_SET ns_noc_io_pcie_soc_ip.csr 142919 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_SET ns_noc_io_pcie_soc_ip.csr 142930 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 142943 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_SET ns_noc_io_pcie_soc_ip.csr 142957 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_SET ns_noc_io_pcie_soc_ip.csr 142973 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_SET ns_noc_io_pcie_soc_ip.csr 142987 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_SET ns_noc_io_pcie_soc_ip.csr 142998 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_SET ns_noc_io_pcie_soc_ip.csr 143009 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 143022 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_SET ns_noc_io_pcie_soc_ip.csr 143036 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_SET ns_noc_io_pcie_soc_ip.csr 143052 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_SET ns_noc_io_pcie_soc_ip.csr 143066 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_SET ns_noc_io_pcie_soc_ip.csr 143077 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_SET ns_noc_io_pcie_soc_ip.csr 143088 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_i router_1_6_6_rivcs_i PCIE_NOC_ROUTER_1_6_6_RIVCS_I_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 143418 R1_6 register rivcs_i 0x44028 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_i This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 143114 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_SET ns_noc_io_pcie_soc_ip.csr 143128 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_SET ns_noc_io_pcie_soc_ip.csr 143144 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_SET ns_noc_io_pcie_soc_ip.csr 143158 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_SET ns_noc_io_pcie_soc_ip.csr 143169 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_SET ns_noc_io_pcie_soc_ip.csr 143180 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 143193 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_SET ns_noc_io_pcie_soc_ip.csr 143207 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_SET ns_noc_io_pcie_soc_ip.csr 143223 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_SET ns_noc_io_pcie_soc_ip.csr 143237 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_SET ns_noc_io_pcie_soc_ip.csr 143248 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_SET ns_noc_io_pcie_soc_ip.csr 143259 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 143272 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_SET ns_noc_io_pcie_soc_ip.csr 143286 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_SET ns_noc_io_pcie_soc_ip.csr 143302 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_SET ns_noc_io_pcie_soc_ip.csr 143316 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_SET ns_noc_io_pcie_soc_ip.csr 143327 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_SET ns_noc_io_pcie_soc_ip.csr 143338 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 143351 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_SET ns_noc_io_pcie_soc_ip.csr 143365 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_SET ns_noc_io_pcie_soc_ip.csr 143381 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_SET ns_noc_io_pcie_soc_ip.csr 143395 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_SET ns_noc_io_pcie_soc_ip.csr 143406 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_SET ns_noc_io_pcie_soc_ip.csr 143417 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_j router_1_6_6_rivcs_j PCIE_NOC_ROUTER_1_6_6_RIVCS_J_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 143747 R1_6 register rivcs_j 0x44030 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_j This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 143443 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_SET ns_noc_io_pcie_soc_ip.csr 143457 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_SET ns_noc_io_pcie_soc_ip.csr 143473 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_SET ns_noc_io_pcie_soc_ip.csr 143487 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_SET ns_noc_io_pcie_soc_ip.csr 143498 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_SET ns_noc_io_pcie_soc_ip.csr 143509 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 143522 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_SET ns_noc_io_pcie_soc_ip.csr 143536 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_SET ns_noc_io_pcie_soc_ip.csr 143552 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_SET ns_noc_io_pcie_soc_ip.csr 143566 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_SET ns_noc_io_pcie_soc_ip.csr 143577 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_SET ns_noc_io_pcie_soc_ip.csr 143588 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 143601 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_SET ns_noc_io_pcie_soc_ip.csr 143615 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_SET ns_noc_io_pcie_soc_ip.csr 143631 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_SET ns_noc_io_pcie_soc_ip.csr 143645 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_SET ns_noc_io_pcie_soc_ip.csr 143656 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_SET ns_noc_io_pcie_soc_ip.csr 143667 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 143680 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_SET ns_noc_io_pcie_soc_ip.csr 143694 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_SET ns_noc_io_pcie_soc_ip.csr 143710 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_SET ns_noc_io_pcie_soc_ip.csr 143724 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_SET ns_noc_io_pcie_soc_ip.csr 143735 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_SET ns_noc_io_pcie_soc_ip.csr 143746 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rivcs_k router_1_6_6_rivcs_k PCIE_NOC_ROUTER_1_6_6_RIVCS_K_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OFFSET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 144076 R1_6 register rivcs_k 0x44038 R 0x00000000 Pcie_noc_router_1_6_6_rivcs_k This register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port. false false false false OUTP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_SET ns_noc_io_pcie_soc_ip.csr 143772 OUTP_0 Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 2 0 0x0 R UP_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_SET ns_noc_io_pcie_soc_ip.csr 143786 UP_0 1'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0 3 3 0x0 R S_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_SET ns_noc_io_pcie_soc_ip.csr 143802 S_0 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port 4 4 0x0 R B_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_SET ns_noc_io_pcie_soc_ip.csr 143816 B_0 1'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type 5 5 0x0 R F_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_SET ns_noc_io_pcie_soc_ip.csr 143827 F_0 1'b1: Buffer full in VC 0 6 6 0x0 R V_0 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_SET ns_noc_io_pcie_soc_ip.csr 143838 V_0 1'b1: Head flit valid (buffer ready) in VC 0 7 7 0x0 R OUTP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_SET ns_noc_io_pcie_soc_ip.csr 143851 OUTP_1 Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 10 8 0x0 R UP_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_SET ns_noc_io_pcie_soc_ip.csr 143865 UP_1 1'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 1 11 11 0x0 R S_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_SET ns_noc_io_pcie_soc_ip.csr 143881 S_1 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port 12 12 0x0 R B_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_SET ns_noc_io_pcie_soc_ip.csr 143895 B_1 1'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type 13 13 0x0 R F_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_SET ns_noc_io_pcie_soc_ip.csr 143906 F_1 1'b1: Buffer full in VC 1 14 14 0x0 R V_1 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_SET ns_noc_io_pcie_soc_ip.csr 143917 V_1 1'b1: Head flit valid (buffer ready) in VC 1 15 15 0x0 R OUTP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_SET ns_noc_io_pcie_soc_ip.csr 143930 OUTP_2 Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 18 16 0x0 R UP_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_SET ns_noc_io_pcie_soc_ip.csr 143944 UP_2 1'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 2 19 19 0x0 R S_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_SET ns_noc_io_pcie_soc_ip.csr 143960 S_2 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port 20 20 0x0 R B_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_SET ns_noc_io_pcie_soc_ip.csr 143974 B_2 1'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type 21 21 0x0 R F_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_SET ns_noc_io_pcie_soc_ip.csr 143985 F_2 1'b1: Buffer full in VC 2 22 22 0x0 R V_2 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_SET ns_noc_io_pcie_soc_ip.csr 143996 V_2 1'b1: Head flit valid (buffer ready) in VC 2 23 23 0x0 R OUTP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_SET ns_noc_io_pcie_soc_ip.csr 144009 OUTP_3 Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K 26 24 0x0 R UP_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_SET ns_noc_io_pcie_soc_ip.csr 144023 UP_3 1'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit 1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 3 27 27 0x0 R S_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_SET ns_noc_io_pcie_soc_ip.csr 144039 S_3 1'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC 1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port 28 28 0x0 R B_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_SET ns_noc_io_pcie_soc_ip.csr 144053 B_3 1'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type 1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type 29 29 0x0 R F_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_SET ns_noc_io_pcie_soc_ip.csr 144064 F_3 1'b1: Buffer full in VC 3 30 30 0x0 R V_3 PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_MSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_LSB PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_RANGE PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_RESET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_GET PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_SET ns_noc_io_pcie_soc_ip.csr 144075 V_3 1'b1: Head flit valid (buffer ready) in VC 3 31 31 0x0 R register pcie_noc.router_1_6_6_rovcs_h router_1_6_6_rovcs_h PCIE_NOC_ROUTER_1_6_6_ROVCS_H_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_H_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_H_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 144337 R1_6 register rovcs_h 0x44040 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_h This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_SET ns_noc_io_pcie_soc_ip.csr 144100 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_SET ns_noc_io_pcie_soc_ip.csr 144114 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_SET ns_noc_io_pcie_soc_ip.csr 144129 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 144140 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 144150 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_SET ns_noc_io_pcie_soc_ip.csr 144162 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_SET ns_noc_io_pcie_soc_ip.csr 144176 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_SET ns_noc_io_pcie_soc_ip.csr 144191 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 144202 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 144212 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_SET ns_noc_io_pcie_soc_ip.csr 144224 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_SET ns_noc_io_pcie_soc_ip.csr 144238 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_SET ns_noc_io_pcie_soc_ip.csr 144253 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 144264 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 144274 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_SET ns_noc_io_pcie_soc_ip.csr 144286 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_SET ns_noc_io_pcie_soc_ip.csr 144300 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_SET ns_noc_io_pcie_soc_ip.csr 144315 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 144326 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 144336 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_e router_1_6_6_rovcs_e PCIE_NOC_ROUTER_1_6_6_ROVCS_E_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_E_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_E_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 144598 R1_6 register rovcs_e 0x44048 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_e This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_SET ns_noc_io_pcie_soc_ip.csr 144361 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_SET ns_noc_io_pcie_soc_ip.csr 144375 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_SET ns_noc_io_pcie_soc_ip.csr 144390 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 144401 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 144411 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_SET ns_noc_io_pcie_soc_ip.csr 144423 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_SET ns_noc_io_pcie_soc_ip.csr 144437 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_SET ns_noc_io_pcie_soc_ip.csr 144452 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 144463 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 144473 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_SET ns_noc_io_pcie_soc_ip.csr 144485 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_SET ns_noc_io_pcie_soc_ip.csr 144499 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_SET ns_noc_io_pcie_soc_ip.csr 144514 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 144525 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 144535 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_SET ns_noc_io_pcie_soc_ip.csr 144547 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_SET ns_noc_io_pcie_soc_ip.csr 144561 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_SET ns_noc_io_pcie_soc_ip.csr 144576 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 144587 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 144597 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_s router_1_6_6_rovcs_s PCIE_NOC_ROUTER_1_6_6_ROVCS_S_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_S_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_S_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 144859 R1_6 register rovcs_s 0x44050 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_s This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_SET ns_noc_io_pcie_soc_ip.csr 144622 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_SET ns_noc_io_pcie_soc_ip.csr 144636 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_SET ns_noc_io_pcie_soc_ip.csr 144651 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 144662 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 144672 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_SET ns_noc_io_pcie_soc_ip.csr 144684 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_SET ns_noc_io_pcie_soc_ip.csr 144698 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_SET ns_noc_io_pcie_soc_ip.csr 144713 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 144724 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 144734 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_SET ns_noc_io_pcie_soc_ip.csr 144746 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_SET ns_noc_io_pcie_soc_ip.csr 144760 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_SET ns_noc_io_pcie_soc_ip.csr 144775 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 144786 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 144796 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_SET ns_noc_io_pcie_soc_ip.csr 144808 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_SET ns_noc_io_pcie_soc_ip.csr 144822 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_SET ns_noc_io_pcie_soc_ip.csr 144837 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 144848 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 144858 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_w router_1_6_6_rovcs_w PCIE_NOC_ROUTER_1_6_6_ROVCS_W_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_W_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_W_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 145120 R1_6 register rovcs_w 0x44058 R 0x00000101 Pcie_noc_router_1_6_6_rovcs_w This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_SET ns_noc_io_pcie_soc_ip.csr 144883 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_SET ns_noc_io_pcie_soc_ip.csr 144897 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_SET ns_noc_io_pcie_soc_ip.csr 144912 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 144923 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 144933 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_SET ns_noc_io_pcie_soc_ip.csr 144945 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x1 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_SET ns_noc_io_pcie_soc_ip.csr 144959 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_SET ns_noc_io_pcie_soc_ip.csr 144974 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 144985 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 144995 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_SET ns_noc_io_pcie_soc_ip.csr 145007 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_SET ns_noc_io_pcie_soc_ip.csr 145021 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_SET ns_noc_io_pcie_soc_ip.csr 145036 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 145047 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 145057 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_SET ns_noc_io_pcie_soc_ip.csr 145069 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_SET ns_noc_io_pcie_soc_ip.csr 145083 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_SET ns_noc_io_pcie_soc_ip.csr 145098 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 145109 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 145119 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_n router_1_6_6_rovcs_n PCIE_NOC_ROUTER_1_6_6_ROVCS_N_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_N_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_N_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 145381 R1_6 register rovcs_n 0x44060 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_n This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_SET ns_noc_io_pcie_soc_ip.csr 145144 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_SET ns_noc_io_pcie_soc_ip.csr 145158 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_SET ns_noc_io_pcie_soc_ip.csr 145173 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 145184 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 145194 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_SET ns_noc_io_pcie_soc_ip.csr 145206 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_SET ns_noc_io_pcie_soc_ip.csr 145220 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_SET ns_noc_io_pcie_soc_ip.csr 145235 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 145246 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 145256 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_SET ns_noc_io_pcie_soc_ip.csr 145268 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_SET ns_noc_io_pcie_soc_ip.csr 145282 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_SET ns_noc_io_pcie_soc_ip.csr 145297 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 145308 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 145318 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_SET ns_noc_io_pcie_soc_ip.csr 145330 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_SET ns_noc_io_pcie_soc_ip.csr 145344 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_SET ns_noc_io_pcie_soc_ip.csr 145359 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 145370 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 145380 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_i router_1_6_6_rovcs_i PCIE_NOC_ROUTER_1_6_6_ROVCS_I_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_I_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_I_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 145642 R1_6 register rovcs_i 0x44068 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_i This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_SET ns_noc_io_pcie_soc_ip.csr 145405 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_SET ns_noc_io_pcie_soc_ip.csr 145419 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_SET ns_noc_io_pcie_soc_ip.csr 145434 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 145445 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 145455 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_SET ns_noc_io_pcie_soc_ip.csr 145467 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_SET ns_noc_io_pcie_soc_ip.csr 145481 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_SET ns_noc_io_pcie_soc_ip.csr 145496 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 145507 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 145517 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_SET ns_noc_io_pcie_soc_ip.csr 145529 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_SET ns_noc_io_pcie_soc_ip.csr 145543 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_SET ns_noc_io_pcie_soc_ip.csr 145558 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 145569 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 145579 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_SET ns_noc_io_pcie_soc_ip.csr 145591 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_SET ns_noc_io_pcie_soc_ip.csr 145605 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_SET ns_noc_io_pcie_soc_ip.csr 145620 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 145631 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 145641 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_j router_1_6_6_rovcs_j PCIE_NOC_ROUTER_1_6_6_ROVCS_J_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_J_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_J_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 145903 R1_6 register rovcs_j 0x44070 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_j This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_SET ns_noc_io_pcie_soc_ip.csr 145666 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_SET ns_noc_io_pcie_soc_ip.csr 145680 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_SET ns_noc_io_pcie_soc_ip.csr 145695 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 145706 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 145716 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_SET ns_noc_io_pcie_soc_ip.csr 145728 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_SET ns_noc_io_pcie_soc_ip.csr 145742 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_SET ns_noc_io_pcie_soc_ip.csr 145757 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 145768 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 145778 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_SET ns_noc_io_pcie_soc_ip.csr 145790 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_SET ns_noc_io_pcie_soc_ip.csr 145804 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_SET ns_noc_io_pcie_soc_ip.csr 145819 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 145830 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 145840 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_SET ns_noc_io_pcie_soc_ip.csr 145852 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_SET ns_noc_io_pcie_soc_ip.csr 145866 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_SET ns_noc_io_pcie_soc_ip.csr 145881 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 145892 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 145902 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_rovcs_k router_1_6_6_rovcs_k PCIE_NOC_ROUTER_1_6_6_ROVCS_K_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_K_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROVCS_K_OFFSET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146164 R1_6 register rovcs_k 0x44078 R 0x00000001 Pcie_noc_router_1_6_6_rovcs_k This register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved). false false false false CF_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_SET ns_noc_io_pcie_soc_ip.csr 145927 CF_0 1'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value. 0 0 0x1 R CE_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_SET ns_noc_io_pcie_soc_ip.csr 145941 CE_0 1'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 1 1 0x0 R VB_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_SET ns_noc_io_pcie_soc_ip.csr 145956 VB_0 1'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 2 2 0x0 R RSV_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_SET ns_noc_io_pcie_soc_ip.csr 145967 RSV_0 Reserved 3 3 0x0 R UNSD_0 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_SET ns_noc_io_pcie_soc_ip.csr 145977 UNSD_0 7 4 0x0 R CF_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_SET ns_noc_io_pcie_soc_ip.csr 145989 CF_1 1'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value. 8 8 0x0 R CE_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_SET ns_noc_io_pcie_soc_ip.csr 146003 CE_1 1'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 9 9 0x0 R VB_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_SET ns_noc_io_pcie_soc_ip.csr 146018 VB_1 1'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 10 10 0x0 R RSV_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_SET ns_noc_io_pcie_soc_ip.csr 146029 RSV_1 Reserved 11 11 0x0 R UNSD_1 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_SET ns_noc_io_pcie_soc_ip.csr 146039 UNSD_1 15 12 0x0 R CF_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_SET ns_noc_io_pcie_soc_ip.csr 146051 CF_2 1'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value. 16 16 0x0 R CE_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_SET ns_noc_io_pcie_soc_ip.csr 146065 CE_2 1'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 17 17 0x0 R VB_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_SET ns_noc_io_pcie_soc_ip.csr 146080 VB_2 1'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 18 18 0x0 R RSV_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_SET ns_noc_io_pcie_soc_ip.csr 146091 RSV_2 Reserved 19 19 0x0 R UNSD_2 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_SET ns_noc_io_pcie_soc_ip.csr 146101 UNSD_2 23 20 0x0 R CF_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_SET ns_noc_io_pcie_soc_ip.csr 146113 CF_3 1'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value. 24 24 0x0 R CE_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_SET ns_noc_io_pcie_soc_ip.csr 146127 CE_3 1'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link. 1'b0: Indicates that credits are available for transmission to downstream link. 25 25 0x0 R VB_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_SET ns_noc_io_pcie_soc_ip.csr 146142 VB_3 1'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports. 1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet. 26 26 0x0 R RSV_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_SET ns_noc_io_pcie_soc_ip.csr 146153 RSV_3 Reserved 27 27 0x0 R UNSD_3 PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_WIDTH PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_MSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_LSB PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_RANGE PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_RESET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_GET PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_SET ns_noc_io_pcie_soc_ip.csr 146163 UNSD_3 31 28 0x0 R register pcie_noc.router_1_6_6_re router_1_6_6_re PCIE_NOC_ROUTER_1_6_6_RE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RE_OFFSET PCIE_NOC_ROUTER_1_6_6_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146338 R1_6 register re 0x44080 R/W 0x00000000 Pcie_noc_router_1_6_6_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_1_6_6_RE_OVFI_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_OVFI_MSB PCIE_NOC_ROUTER_1_6_6_RE_OVFI_LSB PCIE_NOC_ROUTER_1_6_6_RE_OVFI_RANGE PCIE_NOC_ROUTER_1_6_6_RE_OVFI_RESET PCIE_NOC_ROUTER_1_6_6_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_OVFI_GET PCIE_NOC_ROUTER_1_6_6_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 146190 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 146201 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_1_6_6_RE_OVFO_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_OVFO_MSB PCIE_NOC_ROUTER_1_6_6_RE_OVFO_LSB PCIE_NOC_ROUTER_1_6_6_RE_OVFO_RANGE PCIE_NOC_ROUTER_1_6_6_RE_OVFO_RESET PCIE_NOC_ROUTER_1_6_6_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_OVFO_GET PCIE_NOC_ROUTER_1_6_6_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 146215 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 146226 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_1_6_6_RE_PGE_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_PGE_MSB PCIE_NOC_ROUTER_1_6_6_RE_PGE_LSB PCIE_NOC_ROUTER_1_6_6_RE_PGE_RANGE PCIE_NOC_ROUTER_1_6_6_RE_PGE_RESET PCIE_NOC_ROUTER_1_6_6_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_PGE_GET PCIE_NOC_ROUTER_1_6_6_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 146238 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_1_6_6_RE_NLU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_NLU_MSB PCIE_NOC_ROUTER_1_6_6_RE_NLU_LSB PCIE_NOC_ROUTER_1_6_6_RE_NLU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_NLU_RESET PCIE_NOC_ROUTER_1_6_6_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_NLU_GET PCIE_NOC_ROUTER_1_6_6_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 146249 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_1_6_6_RE_ELU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_ELU_MSB PCIE_NOC_ROUTER_1_6_6_RE_ELU_LSB PCIE_NOC_ROUTER_1_6_6_RE_ELU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_ELU_RESET PCIE_NOC_ROUTER_1_6_6_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_ELU_GET PCIE_NOC_ROUTER_1_6_6_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 146260 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_1_6_6_RE_WLU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_WLU_MSB PCIE_NOC_ROUTER_1_6_6_RE_WLU_LSB PCIE_NOC_ROUTER_1_6_6_RE_WLU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_WLU_RESET PCIE_NOC_ROUTER_1_6_6_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_WLU_GET PCIE_NOC_ROUTER_1_6_6_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 146271 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_1_6_6_RE_SLU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_SLU_MSB PCIE_NOC_ROUTER_1_6_6_RE_SLU_LSB PCIE_NOC_ROUTER_1_6_6_RE_SLU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_SLU_RESET PCIE_NOC_ROUTER_1_6_6_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_SLU_GET PCIE_NOC_ROUTER_1_6_6_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 146282 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_1_6_6_RE_HLU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_HLU_MSB PCIE_NOC_ROUTER_1_6_6_RE_HLU_LSB PCIE_NOC_ROUTER_1_6_6_RE_HLU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_HLU_RESET PCIE_NOC_ROUTER_1_6_6_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_HLU_GET PCIE_NOC_ROUTER_1_6_6_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 146293 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_1_6_6_RE_ILU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_ILU_MSB PCIE_NOC_ROUTER_1_6_6_RE_ILU_LSB PCIE_NOC_ROUTER_1_6_6_RE_ILU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_ILU_RESET PCIE_NOC_ROUTER_1_6_6_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_ILU_GET PCIE_NOC_ROUTER_1_6_6_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 146304 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_1_6_6_RE_JLU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_JLU_MSB PCIE_NOC_ROUTER_1_6_6_RE_JLU_LSB PCIE_NOC_ROUTER_1_6_6_RE_JLU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_JLU_RESET PCIE_NOC_ROUTER_1_6_6_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_JLU_GET PCIE_NOC_ROUTER_1_6_6_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 146315 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_1_6_6_RE_KLU_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_KLU_MSB PCIE_NOC_ROUTER_1_6_6_RE_KLU_LSB PCIE_NOC_ROUTER_1_6_6_RE_KLU_RANGE PCIE_NOC_ROUTER_1_6_6_RE_KLU_RESET PCIE_NOC_ROUTER_1_6_6_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_KLU_GET PCIE_NOC_ROUTER_1_6_6_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 146326 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 146337 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_1_6_6_rem router_1_6_6_rem PCIE_NOC_ROUTER_1_6_6_REM_ADDRESS PCIE_NOC_ROUTER_1_6_6_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_REM_OFFSET PCIE_NOC_ROUTER_1_6_6_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146511 R1_6 register rem 0x44088 R/W 0x0001fe00 Pcie_noc_router_1_6_6_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_MSB PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_LSB PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_RANGE PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_RESET PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_GET PCIE_NOC_ROUTER_1_6_6_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 146364 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 146375 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_MSB PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_LSB PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_RANGE PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_RESET PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_GET PCIE_NOC_ROUTER_1_6_6_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 146389 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 146400 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_1_6_6_REM_PGM_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_PGM_MSB PCIE_NOC_ROUTER_1_6_6_REM_PGM_LSB PCIE_NOC_ROUTER_1_6_6_REM_PGM_RANGE PCIE_NOC_ROUTER_1_6_6_REM_PGM_RESET PCIE_NOC_ROUTER_1_6_6_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_PGM_GET PCIE_NOC_ROUTER_1_6_6_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 146411 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_1_6_6_REM_MN_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MN_MSB PCIE_NOC_ROUTER_1_6_6_REM_MN_LSB PCIE_NOC_ROUTER_1_6_6_REM_MN_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MN_RESET PCIE_NOC_ROUTER_1_6_6_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MN_GET PCIE_NOC_ROUTER_1_6_6_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 146422 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_1_6_6_REM_ME_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_ME_MSB PCIE_NOC_ROUTER_1_6_6_REM_ME_LSB PCIE_NOC_ROUTER_1_6_6_REM_ME_RANGE PCIE_NOC_ROUTER_1_6_6_REM_ME_RESET PCIE_NOC_ROUTER_1_6_6_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_ME_GET PCIE_NOC_ROUTER_1_6_6_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 146433 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_1_6_6_REM_MW_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MW_MSB PCIE_NOC_ROUTER_1_6_6_REM_MW_LSB PCIE_NOC_ROUTER_1_6_6_REM_MW_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MW_RESET PCIE_NOC_ROUTER_1_6_6_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MW_GET PCIE_NOC_ROUTER_1_6_6_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 146444 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_1_6_6_REM_MS_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MS_MSB PCIE_NOC_ROUTER_1_6_6_REM_MS_LSB PCIE_NOC_ROUTER_1_6_6_REM_MS_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MS_RESET PCIE_NOC_ROUTER_1_6_6_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MS_GET PCIE_NOC_ROUTER_1_6_6_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 146455 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_1_6_6_REM_MH_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MH_MSB PCIE_NOC_ROUTER_1_6_6_REM_MH_LSB PCIE_NOC_ROUTER_1_6_6_REM_MH_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MH_RESET PCIE_NOC_ROUTER_1_6_6_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MH_GET PCIE_NOC_ROUTER_1_6_6_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 146466 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_1_6_6_REM_MI_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MI_MSB PCIE_NOC_ROUTER_1_6_6_REM_MI_LSB PCIE_NOC_ROUTER_1_6_6_REM_MI_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MI_RESET PCIE_NOC_ROUTER_1_6_6_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MI_GET PCIE_NOC_ROUTER_1_6_6_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 146477 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_1_6_6_REM_MJ_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MJ_MSB PCIE_NOC_ROUTER_1_6_6_REM_MJ_LSB PCIE_NOC_ROUTER_1_6_6_REM_MJ_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MJ_RESET PCIE_NOC_ROUTER_1_6_6_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MJ_GET PCIE_NOC_ROUTER_1_6_6_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 146488 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_1_6_6_REM_MK_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_MK_MSB PCIE_NOC_ROUTER_1_6_6_REM_MK_LSB PCIE_NOC_ROUTER_1_6_6_REM_MK_RANGE PCIE_NOC_ROUTER_1_6_6_REM_MK_RESET PCIE_NOC_ROUTER_1_6_6_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_MK_GET PCIE_NOC_ROUTER_1_6_6_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 146499 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 146510 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_1_6_6_recc router_1_6_6_recc PCIE_NOC_ROUTER_1_6_6_RECC_ADDRESS PCIE_NOC_ROUTER_1_6_6_RECC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RECC_OFFSET PCIE_NOC_ROUTER_1_6_6_RECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146596 R1_6 register recc 0x44090 R/W 0x00000000 Pcie_noc_router_1_6_6_recc This register is used to select which hardware events will increment the event counter. false false false false IVC PCIE_NOC_ROUTER_1_6_6_RECC_IVC_WIDTH PCIE_NOC_ROUTER_1_6_6_RECC_IVC_MSB PCIE_NOC_ROUTER_1_6_6_RECC_IVC_LSB PCIE_NOC_ROUTER_1_6_6_RECC_IVC_RANGE PCIE_NOC_ROUTER_1_6_6_RECC_IVC_RESET PCIE_NOC_ROUTER_1_6_6_RECC_IVC_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RECC_IVC_GET PCIE_NOC_ROUTER_1_6_6_RECC_IVC_SET ns_noc_io_pcie_soc_ip.csr 146532 IVC 11: Input VC 3 10: Input VC 2 01: Input VC 1 00: Input VC 0 1 0 0x0 R/W UNSD_3_2 PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_WIDTH PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_MSB PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_LSB PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_RANGE PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_RESET PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_GET PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_SET ns_noc_io_pcie_soc_ip.csr 146543 UNSD_3_2 3 2 0x0 R INP PCIE_NOC_ROUTER_1_6_6_RECC_INP_WIDTH PCIE_NOC_ROUTER_1_6_6_RECC_INP_MSB PCIE_NOC_ROUTER_1_6_6_RECC_INP_LSB PCIE_NOC_ROUTER_1_6_6_RECC_INP_RANGE PCIE_NOC_ROUTER_1_6_6_RECC_INP_RESET PCIE_NOC_ROUTER_1_6_6_RECC_INP_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RECC_INP_GET PCIE_NOC_ROUTER_1_6_6_RECC_INP_SET ns_noc_io_pcie_soc_ip.csr 146554 INP Input port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_GET PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 146565 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_1_6_6_RECC_EVT_WIDTH PCIE_NOC_ROUTER_1_6_6_RECC_EVT_MSB PCIE_NOC_ROUTER_1_6_6_RECC_EVT_LSB PCIE_NOC_ROUTER_1_6_6_RECC_EVT_RANGE PCIE_NOC_ROUTER_1_6_6_RECC_EVT_RESET PCIE_NOC_ROUTER_1_6_6_RECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RECC_EVT_GET PCIE_NOC_ROUTER_1_6_6_RECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 146584 EVT 11: Generates count event when VC has valid data, but is stalled 10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port 01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port 00: Disable 9 8 0x0 R/W UNSD_31_10 PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_WIDTH PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_MSB PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_LSB PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_RANGE PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_RESET PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_GET PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_SET ns_noc_io_pcie_soc_ip.csr 146595 UNSD_31_10 31 10 0x000000 R register pcie_noc.router_1_6_6_rec router_1_6_6_rec PCIE_NOC_ROUTER_1_6_6_REC_ADDRESS PCIE_NOC_ROUTER_1_6_6_REC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_REC_OFFSET PCIE_NOC_ROUTER_1_6_6_REC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146621 R1_6 register rec 0x44098 R/W 0x00000000 Pcie_noc_router_1_6_6_rec This register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_GET PCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 146620 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_1_6_6_id router_1_6_6_id PCIE_NOC_ROUTER_1_6_6_ID_ADDRESS PCIE_NOC_ROUTER_1_6_6_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ID_OFFSET PCIE_NOC_ROUTER_1_6_6_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146690 R1_6 register id 0x440A0 R 0x010000c1 Pcie_noc_router_1_6_6_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_1_6_6_ID_LAYER_WIDTH PCIE_NOC_ROUTER_1_6_6_ID_LAYER_MSB PCIE_NOC_ROUTER_1_6_6_ID_LAYER_LSB PCIE_NOC_ROUTER_1_6_6_ID_LAYER_RANGE PCIE_NOC_ROUTER_1_6_6_ID_LAYER_RESET PCIE_NOC_ROUTER_1_6_6_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ID_LAYER_GET PCIE_NOC_ROUTER_1_6_6_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 146646 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x01 R POS PCIE_NOC_ROUTER_1_6_6_ID_POS_WIDTH PCIE_NOC_ROUTER_1_6_6_ID_POS_MSB PCIE_NOC_ROUTER_1_6_6_ID_POS_LSB PCIE_NOC_ROUTER_1_6_6_ID_POS_RANGE PCIE_NOC_ROUTER_1_6_6_ID_POS_RESET PCIE_NOC_ROUTER_1_6_6_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ID_POS_GET PCIE_NOC_ROUTER_1_6_6_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 146657 POS 16-bit position ID of this router in the NoC 20 5 0x0006 R ZERO PCIE_NOC_ROUTER_1_6_6_ID_ZERO_WIDTH PCIE_NOC_ROUTER_1_6_6_ID_ZERO_MSB PCIE_NOC_ROUTER_1_6_6_ID_ZERO_LSB PCIE_NOC_ROUTER_1_6_6_ID_ZERO_RANGE PCIE_NOC_ROUTER_1_6_6_ID_ZERO_RESET PCIE_NOC_ROUTER_1_6_6_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ID_ZERO_GET PCIE_NOC_ROUTER_1_6_6_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 146668 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_1_6_6_ID_ONE_WIDTH PCIE_NOC_ROUTER_1_6_6_ID_ONE_MSB PCIE_NOC_ROUTER_1_6_6_ID_ONE_LSB PCIE_NOC_ROUTER_1_6_6_ID_ONE_RANGE PCIE_NOC_ROUTER_1_6_6_ID_ONE_RESET PCIE_NOC_ROUTER_1_6_6_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ID_ONE_GET PCIE_NOC_ROUTER_1_6_6_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 146679 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 146689 UNSD_31_25 31 25 0x00 R register pcie_noc.router_1_6_6_rcgc router_1_6_6_rcgc PCIE_NOC_ROUTER_1_6_6_RCGC_ADDRESS PCIE_NOC_ROUTER_1_6_6_RCGC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RCGC_OFFSET PCIE_NOC_ROUTER_1_6_6_RCGC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146716 R1_6 register rcgc 0x440A8 R/W 0x00000064 Pcie_noc_router_1_6_6_rcgc Programmable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port. false false false false HYSTERESIS_COUNTER PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_WIDTH PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_MSB PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_LSB PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_RANGE PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_RESET PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_GET PCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_SET ns_noc_io_pcie_soc_ip.csr 146715 HYSTERESIS_COUNTER Hysteresis counter 31 0 0x00000064 R/W register pcie_noc.router_1_6_6_rcgo router_1_6_6_rcgo PCIE_NOC_ROUTER_1_6_6_RCGO_ADDRESS PCIE_NOC_ROUTER_1_6_6_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_RCGO_OFFSET PCIE_NOC_ROUTER_1_6_6_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 146755 R1_6 register rcgo 0x440B0 R/W 0x00000000 Pcie_noc_router_1_6_6_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_MSB PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_LSB PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_RANGE PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_RESET PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_GET PCIE_NOC_ROUTER_1_6_6_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 146743 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 146754 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_1_6_6_p0_rperr router_1_6_6_p0_rperr PCIE_NOC_ROUTER_1_6_6_P0_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P0_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P0_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 147046 R1_6 register p0_rperr 0x440B8 R/W 0x00000000 Pcie_noc_router_1_6_6_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 146798 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 146809 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 146820 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 146831 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 146842 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 146853 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 146864 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 146875 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 146887 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 146898 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 146910 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 146922 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 146935 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 146947 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 146959 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 146971 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 146984 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 146996 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 147008 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 147020 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 147033 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 147045 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p1_rperr router_1_6_6_p1_rperr PCIE_NOC_ROUTER_1_6_6_P1_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P1_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P1_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 147333 R1_6 register p1_rperr 0x440C0 R/W 0x00000000 Pcie_noc_router_1_6_6_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 147089 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 147100 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 147111 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 147122 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 147133 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 147144 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 147155 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 147166 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 147178 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 147189 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 147200 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 147211 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 147223 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 147234 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 147246 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 147258 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 147271 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 147283 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 147295 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 147307 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 147320 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 147332 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p2_rperr router_1_6_6_p2_rperr PCIE_NOC_ROUTER_1_6_6_P2_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P2_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P2_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 147624 R1_6 register p2_rperr 0x440C8 R/W 0x00000000 Pcie_noc_router_1_6_6_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 147376 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 147387 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 147398 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 147409 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 147420 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 147431 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 147442 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 147453 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 147465 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 147476 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 147488 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 147500 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 147513 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 147525 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 147537 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 147549 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 147562 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 147574 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 147586 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 147598 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 147611 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 147623 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p3_rperr router_1_6_6_p3_rperr PCIE_NOC_ROUTER_1_6_6_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P3_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 147915 R1_6 register p3_rperr 0x440D0 R/W 0x00000000 Pcie_noc_router_1_6_6_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 147667 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 147678 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 147689 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 147700 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 147711 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 147722 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 147733 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 147744 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 147756 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 147767 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 147779 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 147791 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 147804 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 147816 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 147828 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 147840 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 147853 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 147865 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 147877 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 147889 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 147902 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 147914 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p4_rperr router_1_6_6_p4_rperr PCIE_NOC_ROUTER_1_6_6_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P4_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 148206 R1_6 register p4_rperr 0x440D8 R/W 0x00000000 Pcie_noc_router_1_6_6_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 147958 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 147969 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 147980 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 147991 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 148002 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 148013 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 148025 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R SB_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 148037 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R PK_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 148050 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R RI_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 148062 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R D_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 148073 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 148084 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 148096 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 148107 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 148119 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 148131 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 148144 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 148156 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 148168 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 148180 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 148193 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 148205 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p5_rperr router_1_6_6_p5_rperr PCIE_NOC_ROUTER_1_6_6_P5_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P5_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P5_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 148497 R1_6 register p5_rperr 0x440E0 R/W 0x00000000 Pcie_noc_router_1_6_6_p5_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 148249 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 148260 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 148271 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 148282 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 148293 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 148304 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 148316 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R SB_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 148328 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R PK_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 148341 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R RI_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 148353 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R D_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 148364 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 148375 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 148387 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 148398 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 148410 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 148422 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 148435 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 148447 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 148459 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 148471 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 148484 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 148496 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p6_rperr router_1_6_6_p6_rperr PCIE_NOC_ROUTER_1_6_6_P6_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P6_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P6_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 148788 R1_6 register p6_rperr 0x440E8 R/W 0x00000000 Pcie_noc_router_1_6_6_p6_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 148540 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 148551 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 148562 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 148573 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 148584 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 148595 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 148606 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 148617 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 148629 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 148640 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 148652 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 148664 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 148677 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 148689 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 148701 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 148713 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 148726 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 148738 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 148750 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 148762 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 148775 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 148787 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p7_rperr router_1_6_6_p7_rperr PCIE_NOC_ROUTER_1_6_6_P7_RPERR_ADDRESS PCIE_NOC_ROUTER_1_6_6_P7_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P7_RPERR_OFFSET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 149079 R1_6 register p7_rperr 0x440F0 R/W 0x00000000 Pcie_noc_router_1_6_6_p7_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 148831 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 148842 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 148853 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 148864 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 148875 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 148886 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 148897 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 148908 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 148920 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 148931 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 148943 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 148955 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 148968 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 148980 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 148992 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 149004 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 149017 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 149029 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 149041 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 149053 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 149066 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 149078 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_1_6_6_p0_rperrm router_1_6_6_p0_rperrm PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 149337 R1_6 register p0_rperrm 0x440F8 R/W 0x00000000 Pcie_noc_router_1_6_6_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 149101 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 149112 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 149123 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 149134 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 149145 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 149156 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 149167 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 149178 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 149190 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 149201 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 149212 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 149223 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 149235 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 149246 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 149257 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 149268 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 149280 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 149291 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 149302 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 149313 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 149325 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 149336 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p1_rperrm router_1_6_6_p1_rperrm PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 149595 R1_6 register p1_rperrm 0x44100 R/W 0x00000000 Pcie_noc_router_1_6_6_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 149359 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 149370 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 149381 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 149392 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 149403 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 149414 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 149425 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 149436 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 149448 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 149459 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 149470 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 149481 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 149493 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 149504 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 149515 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 149526 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 149538 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 149549 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 149560 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 149571 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 149583 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 149594 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p2_rperrm router_1_6_6_p2_rperrm PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 149853 R1_6 register p2_rperrm 0x44108 R/W 0x00000000 Pcie_noc_router_1_6_6_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 149617 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 149628 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 149639 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 149650 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 149661 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 149672 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 149683 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 149694 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 149706 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 149717 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 149728 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 149739 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 149751 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 149762 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 149773 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 149784 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 149796 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 149807 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 149818 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 149829 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 149841 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 149852 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p3_rperrm router_1_6_6_p3_rperrm PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 150111 R1_6 register p3_rperrm 0x44110 R/W 0x00000000 Pcie_noc_router_1_6_6_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 149875 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 149886 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 149897 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 149908 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 149919 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 149930 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 149941 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 149952 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 149964 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 149975 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 149986 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 149997 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 150009 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 150020 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 150031 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 150042 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 150054 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 150065 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 150076 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 150087 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 150099 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 150110 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p4_rperrm router_1_6_6_p4_rperrm PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 150369 R1_6 register p4_rperrm 0x44118 R/W 0x00000000 Pcie_noc_router_1_6_6_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 150133 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 150144 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 150155 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 150166 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 150177 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 150188 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 150199 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 150210 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 150222 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 150233 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 150244 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 150255 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 150267 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 150278 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 150289 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 150300 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 150312 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 150323 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 150334 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 150345 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 150357 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 150368 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p5_rperrm router_1_6_6_p5_rperrm PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 150627 R1_6 register p5_rperrm 0x44120 R/W 0x00000000 Pcie_noc_router_1_6_6_p5_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 150391 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 150402 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 150413 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 150424 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 150435 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 150446 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 150457 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 150468 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 150480 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 150491 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 150502 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 150513 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 150525 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 150536 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 150547 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 150558 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 150570 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 150581 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 150592 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 150603 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 150615 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 150626 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p6_rperrm router_1_6_6_p6_rperrm PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 150885 R1_6 register p6_rperrm 0x44128 R/W 0x00000000 Pcie_noc_router_1_6_6_p6_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 150649 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 150660 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 150671 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 150682 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 150693 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 150704 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 150715 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 150726 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 150738 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 150749 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 150760 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 150771 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 150783 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 150794 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 150805 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 150816 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 150828 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 150839 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 150850 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 150861 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 150873 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 150884 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_p7_rperrm router_1_6_6_p7_rperrm PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_ADDRESS PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_OFFSET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151143 R1_6 register p7_rperrm 0x44130 R/W 0x00000000 Pcie_noc_router_1_6_6_p7_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 150907 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 150918 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 150929 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 150940 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 150951 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 150962 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 150973 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 150984 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 150996 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 151007 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 151018 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 151029 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 151041 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 151052 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 151063 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 151074 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 151086 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 151097 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 151108 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 151119 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 151131 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_GET PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 151142 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_1_6_6_roecc router_1_6_6_roecc PCIE_NOC_ROUTER_1_6_6_ROECC_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROECC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROECC_OFFSET PCIE_NOC_ROUTER_1_6_6_ROECC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151216 R1_6 register roecc 0x44138 R/W 0x00000000 Pcie_noc_router_1_6_6_roecc This register is used to select which hardware events will increment the output event counter. false false false false OVC PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_WIDTH PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_MSB PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_LSB PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_RANGE PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_RESET PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_GET PCIE_NOC_ROUTER_1_6_6_ROECC_OVC_SET ns_noc_io_pcie_soc_ip.csr 151161 OVC Bit map to select output VCs to monitor events on 3 0 0x0 R/W OP PCIE_NOC_ROUTER_1_6_6_ROECC_OP_WIDTH PCIE_NOC_ROUTER_1_6_6_ROECC_OP_MSB PCIE_NOC_ROUTER_1_6_6_ROECC_OP_LSB PCIE_NOC_ROUTER_1_6_6_ROECC_OP_RANGE PCIE_NOC_ROUTER_1_6_6_ROECC_OP_RESET PCIE_NOC_ROUTER_1_6_6_ROECC_OP_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROECC_OP_GET PCIE_NOC_ROUTER_1_6_6_ROECC_OP_SET ns_noc_io_pcie_soc_ip.csr 151172 OP Output port on which the event is captured 6 4 0x0 R/W UNSD_7_7 PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_WIDTH PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_MSB PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_LSB PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_RANGE PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_RESET PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_GET PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_SET ns_noc_io_pcie_soc_ip.csr 151183 UNSD_7_7 7 7 0x0 R EVT PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_WIDTH PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_MSB PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_LSB PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_RANGE PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_RESET PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_GET PCIE_NOC_ROUTER_1_6_6_ROECC_EVT_SET ns_noc_io_pcie_soc_ip.csr 151204 EVT 100: Port stalled. Input flits are available for the port, but no output VC has credit 011: Generates count event when flits are available to be sent to output VC, but the VC has no credit 010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port 001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port 000: Disable 10 8 0x0 R/W UNSD_31_11 PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_WIDTH PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_MSB PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_LSB PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_RANGE PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_RESET PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_GET PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_SET ns_noc_io_pcie_soc_ip.csr 151215 UNSD_31_11 31 11 0x000000 R register pcie_noc.router_1_6_6_roec router_1_6_6_roec PCIE_NOC_ROUTER_1_6_6_ROEC_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROEC_BYTE_ADDRESS PCIE_NOC_ROUTER_1_6_6_ROEC_OFFSET PCIE_NOC_ROUTER_1_6_6_ROEC_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151241 R1_6 register roec 0x44140 R/W 0x00000000 Pcie_noc_router_1_6_6_roec This register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt. false false false false EVENT_CNTR PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_WIDTH PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_MSB PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_LSB PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_RANGE PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_RESET PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_FIELD_MASK PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_GET PCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_SET ns_noc_io_pcie_soc_ip.csr 151240 EVENT_CNTR 32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE 31 0 0x00000000 R/W register pcie_noc.router_2_1_1_re router_2_1_1_re PCIE_NOC_ROUTER_2_1_1_RE_ADDRESS PCIE_NOC_ROUTER_2_1_1_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_RE_OFFSET PCIE_NOC_ROUTER_2_1_1_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151415 R2_1 register re 0x48080 R/W 0x00000000 Pcie_noc_router_2_1_1_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_2_1_1_RE_OVFI_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_OVFI_MSB PCIE_NOC_ROUTER_2_1_1_RE_OVFI_LSB PCIE_NOC_ROUTER_2_1_1_RE_OVFI_RANGE PCIE_NOC_ROUTER_2_1_1_RE_OVFI_RESET PCIE_NOC_ROUTER_2_1_1_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_OVFI_GET PCIE_NOC_ROUTER_2_1_1_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 151267 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 151278 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_2_1_1_RE_OVFO_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_OVFO_MSB PCIE_NOC_ROUTER_2_1_1_RE_OVFO_LSB PCIE_NOC_ROUTER_2_1_1_RE_OVFO_RANGE PCIE_NOC_ROUTER_2_1_1_RE_OVFO_RESET PCIE_NOC_ROUTER_2_1_1_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_OVFO_GET PCIE_NOC_ROUTER_2_1_1_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 151292 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 151303 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_2_1_1_RE_PGE_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_PGE_MSB PCIE_NOC_ROUTER_2_1_1_RE_PGE_LSB PCIE_NOC_ROUTER_2_1_1_RE_PGE_RANGE PCIE_NOC_ROUTER_2_1_1_RE_PGE_RESET PCIE_NOC_ROUTER_2_1_1_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_PGE_GET PCIE_NOC_ROUTER_2_1_1_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 151315 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_2_1_1_RE_NLU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_NLU_MSB PCIE_NOC_ROUTER_2_1_1_RE_NLU_LSB PCIE_NOC_ROUTER_2_1_1_RE_NLU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_NLU_RESET PCIE_NOC_ROUTER_2_1_1_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_NLU_GET PCIE_NOC_ROUTER_2_1_1_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 151326 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_2_1_1_RE_ELU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_ELU_MSB PCIE_NOC_ROUTER_2_1_1_RE_ELU_LSB PCIE_NOC_ROUTER_2_1_1_RE_ELU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_ELU_RESET PCIE_NOC_ROUTER_2_1_1_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_ELU_GET PCIE_NOC_ROUTER_2_1_1_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 151337 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_2_1_1_RE_WLU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_WLU_MSB PCIE_NOC_ROUTER_2_1_1_RE_WLU_LSB PCIE_NOC_ROUTER_2_1_1_RE_WLU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_WLU_RESET PCIE_NOC_ROUTER_2_1_1_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_WLU_GET PCIE_NOC_ROUTER_2_1_1_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 151348 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_2_1_1_RE_SLU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_SLU_MSB PCIE_NOC_ROUTER_2_1_1_RE_SLU_LSB PCIE_NOC_ROUTER_2_1_1_RE_SLU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_SLU_RESET PCIE_NOC_ROUTER_2_1_1_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_SLU_GET PCIE_NOC_ROUTER_2_1_1_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 151359 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_2_1_1_RE_HLU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_HLU_MSB PCIE_NOC_ROUTER_2_1_1_RE_HLU_LSB PCIE_NOC_ROUTER_2_1_1_RE_HLU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_HLU_RESET PCIE_NOC_ROUTER_2_1_1_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_HLU_GET PCIE_NOC_ROUTER_2_1_1_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 151370 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_2_1_1_RE_ILU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_ILU_MSB PCIE_NOC_ROUTER_2_1_1_RE_ILU_LSB PCIE_NOC_ROUTER_2_1_1_RE_ILU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_ILU_RESET PCIE_NOC_ROUTER_2_1_1_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_ILU_GET PCIE_NOC_ROUTER_2_1_1_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 151381 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_2_1_1_RE_JLU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_JLU_MSB PCIE_NOC_ROUTER_2_1_1_RE_JLU_LSB PCIE_NOC_ROUTER_2_1_1_RE_JLU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_JLU_RESET PCIE_NOC_ROUTER_2_1_1_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_JLU_GET PCIE_NOC_ROUTER_2_1_1_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 151392 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_2_1_1_RE_KLU_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_KLU_MSB PCIE_NOC_ROUTER_2_1_1_RE_KLU_LSB PCIE_NOC_ROUTER_2_1_1_RE_KLU_RANGE PCIE_NOC_ROUTER_2_1_1_RE_KLU_RESET PCIE_NOC_ROUTER_2_1_1_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_KLU_GET PCIE_NOC_ROUTER_2_1_1_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 151403 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 151414 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_1_1_rem router_2_1_1_rem PCIE_NOC_ROUTER_2_1_1_REM_ADDRESS PCIE_NOC_ROUTER_2_1_1_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_REM_OFFSET PCIE_NOC_ROUTER_2_1_1_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151588 R2_1 register rem 0x48088 R/W 0x0001fe00 Pcie_noc_router_2_1_1_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_MSB PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_LSB PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_RANGE PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_RESET PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_GET PCIE_NOC_ROUTER_2_1_1_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 151441 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 151452 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_MSB PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_LSB PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_RANGE PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_RESET PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_GET PCIE_NOC_ROUTER_2_1_1_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 151466 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 151477 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_2_1_1_REM_PGM_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_PGM_MSB PCIE_NOC_ROUTER_2_1_1_REM_PGM_LSB PCIE_NOC_ROUTER_2_1_1_REM_PGM_RANGE PCIE_NOC_ROUTER_2_1_1_REM_PGM_RESET PCIE_NOC_ROUTER_2_1_1_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_PGM_GET PCIE_NOC_ROUTER_2_1_1_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 151488 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_2_1_1_REM_MN_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MN_MSB PCIE_NOC_ROUTER_2_1_1_REM_MN_LSB PCIE_NOC_ROUTER_2_1_1_REM_MN_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MN_RESET PCIE_NOC_ROUTER_2_1_1_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MN_GET PCIE_NOC_ROUTER_2_1_1_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 151499 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_2_1_1_REM_ME_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_ME_MSB PCIE_NOC_ROUTER_2_1_1_REM_ME_LSB PCIE_NOC_ROUTER_2_1_1_REM_ME_RANGE PCIE_NOC_ROUTER_2_1_1_REM_ME_RESET PCIE_NOC_ROUTER_2_1_1_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_ME_GET PCIE_NOC_ROUTER_2_1_1_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 151510 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_2_1_1_REM_MW_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MW_MSB PCIE_NOC_ROUTER_2_1_1_REM_MW_LSB PCIE_NOC_ROUTER_2_1_1_REM_MW_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MW_RESET PCIE_NOC_ROUTER_2_1_1_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MW_GET PCIE_NOC_ROUTER_2_1_1_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 151521 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_2_1_1_REM_MS_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MS_MSB PCIE_NOC_ROUTER_2_1_1_REM_MS_LSB PCIE_NOC_ROUTER_2_1_1_REM_MS_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MS_RESET PCIE_NOC_ROUTER_2_1_1_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MS_GET PCIE_NOC_ROUTER_2_1_1_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 151532 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_2_1_1_REM_MH_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MH_MSB PCIE_NOC_ROUTER_2_1_1_REM_MH_LSB PCIE_NOC_ROUTER_2_1_1_REM_MH_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MH_RESET PCIE_NOC_ROUTER_2_1_1_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MH_GET PCIE_NOC_ROUTER_2_1_1_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 151543 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_2_1_1_REM_MI_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MI_MSB PCIE_NOC_ROUTER_2_1_1_REM_MI_LSB PCIE_NOC_ROUTER_2_1_1_REM_MI_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MI_RESET PCIE_NOC_ROUTER_2_1_1_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MI_GET PCIE_NOC_ROUTER_2_1_1_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 151554 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_2_1_1_REM_MJ_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MJ_MSB PCIE_NOC_ROUTER_2_1_1_REM_MJ_LSB PCIE_NOC_ROUTER_2_1_1_REM_MJ_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MJ_RESET PCIE_NOC_ROUTER_2_1_1_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MJ_GET PCIE_NOC_ROUTER_2_1_1_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 151565 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_2_1_1_REM_MK_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_MK_MSB PCIE_NOC_ROUTER_2_1_1_REM_MK_LSB PCIE_NOC_ROUTER_2_1_1_REM_MK_RANGE PCIE_NOC_ROUTER_2_1_1_REM_MK_RESET PCIE_NOC_ROUTER_2_1_1_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_MK_GET PCIE_NOC_ROUTER_2_1_1_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 151576 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 151587 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_1_1_id router_2_1_1_id PCIE_NOC_ROUTER_2_1_1_ID_ADDRESS PCIE_NOC_ROUTER_2_1_1_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_ID_OFFSET PCIE_NOC_ROUTER_2_1_1_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151657 R2_1 register id 0x480A0 R 0x01000022 Pcie_noc_router_2_1_1_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_2_1_1_ID_LAYER_WIDTH PCIE_NOC_ROUTER_2_1_1_ID_LAYER_MSB PCIE_NOC_ROUTER_2_1_1_ID_LAYER_LSB PCIE_NOC_ROUTER_2_1_1_ID_LAYER_RANGE PCIE_NOC_ROUTER_2_1_1_ID_LAYER_RESET PCIE_NOC_ROUTER_2_1_1_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_ID_LAYER_GET PCIE_NOC_ROUTER_2_1_1_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 151613 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS PCIE_NOC_ROUTER_2_1_1_ID_POS_WIDTH PCIE_NOC_ROUTER_2_1_1_ID_POS_MSB PCIE_NOC_ROUTER_2_1_1_ID_POS_LSB PCIE_NOC_ROUTER_2_1_1_ID_POS_RANGE PCIE_NOC_ROUTER_2_1_1_ID_POS_RESET PCIE_NOC_ROUTER_2_1_1_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_ID_POS_GET PCIE_NOC_ROUTER_2_1_1_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 151624 POS 16-bit position ID of this router in the NoC 20 5 0x0001 R ZERO PCIE_NOC_ROUTER_2_1_1_ID_ZERO_WIDTH PCIE_NOC_ROUTER_2_1_1_ID_ZERO_MSB PCIE_NOC_ROUTER_2_1_1_ID_ZERO_LSB PCIE_NOC_ROUTER_2_1_1_ID_ZERO_RANGE PCIE_NOC_ROUTER_2_1_1_ID_ZERO_RESET PCIE_NOC_ROUTER_2_1_1_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_ID_ZERO_GET PCIE_NOC_ROUTER_2_1_1_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 151635 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_2_1_1_ID_ONE_WIDTH PCIE_NOC_ROUTER_2_1_1_ID_ONE_MSB PCIE_NOC_ROUTER_2_1_1_ID_ONE_LSB PCIE_NOC_ROUTER_2_1_1_ID_ONE_RANGE PCIE_NOC_ROUTER_2_1_1_ID_ONE_RESET PCIE_NOC_ROUTER_2_1_1_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_ID_ONE_GET PCIE_NOC_ROUTER_2_1_1_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 151646 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 151656 UNSD_31_25 31 25 0x00 R register pcie_noc.router_2_1_1_rcgo router_2_1_1_rcgo PCIE_NOC_ROUTER_2_1_1_RCGO_ADDRESS PCIE_NOC_ROUTER_2_1_1_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_RCGO_OFFSET PCIE_NOC_ROUTER_2_1_1_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151696 R2_1 register rcgo 0x480B0 R/W 0x00000000 Pcie_noc_router_2_1_1_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_MSB PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_LSB PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_RANGE PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_RESET PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_GET PCIE_NOC_ROUTER_2_1_1_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 151684 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 151695 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_2_1_1_p1_rperr router_2_1_1_p1_rperr PCIE_NOC_ROUTER_2_1_1_P1_RPERR_ADDRESS PCIE_NOC_ROUTER_2_1_1_P1_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P1_RPERR_OFFSET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 151987 R2_1 register p1_rperr 0x480C0 R/W 0x00000000 Pcie_noc_router_2_1_1_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 151739 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 151750 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 151761 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 151772 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 151783 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 151794 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 151805 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 151816 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 151828 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 151839 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 151851 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 151863 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 151876 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 151888 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 151900 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 151912 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 151925 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 151937 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 151949 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 151961 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 151974 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 151986 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_1_1_p2_rperr router_2_1_1_p2_rperr PCIE_NOC_ROUTER_2_1_1_P2_RPERR_ADDRESS PCIE_NOC_ROUTER_2_1_1_P2_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P2_RPERR_OFFSET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 152278 R2_1 register p2_rperr 0x480C8 R/W 0x00000000 Pcie_noc_router_2_1_1_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 152030 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 152041 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 152052 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 152063 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 152074 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 152085 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 152096 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 152107 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 152119 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 152130 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 152142 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 152154 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 152167 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 152179 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 152191 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 152203 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 152216 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 152228 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 152240 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 152252 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 152265 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 152277 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_1_1_p3_rperr router_2_1_1_p3_rperr PCIE_NOC_ROUTER_2_1_1_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_2_1_1_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P3_RPERR_OFFSET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 152569 R2_1 register p3_rperr 0x480D0 R/W 0x00000000 Pcie_noc_router_2_1_1_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 152321 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 152332 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 152343 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 152354 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 152365 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 152376 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 152387 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 152398 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 152410 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 152421 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 152433 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 152445 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 152458 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 152470 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 152482 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 152494 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 152507 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 152519 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 152531 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 152543 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 152556 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 152568 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_1_1_p4_rperr router_2_1_1_p4_rperr PCIE_NOC_ROUTER_2_1_1_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_2_1_1_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P4_RPERR_OFFSET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 152860 R2_1 register p4_rperr 0x480D8 R/W 0x00000000 Pcie_noc_router_2_1_1_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 152612 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 152623 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 152634 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 152645 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 152656 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 152667 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 152678 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 152689 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 152701 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 152712 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 152724 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 152736 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 152749 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 152761 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 152773 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 152785 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 152798 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 152810 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 152822 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 152834 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 152847 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 152859 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_1_1_p1_rperrm router_2_1_1_p1_rperrm PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_OFFSET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 153118 R2_1 register p1_rperrm 0x48100 R/W 0x00000000 Pcie_noc_router_2_1_1_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 152882 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 152893 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 152904 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 152915 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 152926 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 152937 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 152948 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 152959 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 152971 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 152982 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 152993 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 153004 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 153016 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 153027 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 153038 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 153049 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 153061 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 153072 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 153083 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 153094 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 153106 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 153117 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_1_1_p2_rperrm router_2_1_1_p2_rperrm PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_OFFSET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 153376 R2_1 register p2_rperrm 0x48108 R/W 0x00000000 Pcie_noc_router_2_1_1_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 153140 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 153151 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 153162 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 153173 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 153184 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 153195 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 153206 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 153217 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 153229 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 153240 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 153251 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 153262 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 153274 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 153285 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 153296 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 153307 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 153319 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 153330 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 153341 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 153352 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 153364 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 153375 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_1_1_p3_rperrm router_2_1_1_p3_rperrm PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 153634 R2_1 register p3_rperrm 0x48110 R/W 0x00000000 Pcie_noc_router_2_1_1_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 153398 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 153409 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 153420 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 153431 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 153442 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 153453 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 153464 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 153475 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 153487 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 153498 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 153509 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 153520 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 153532 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 153543 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 153554 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 153565 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 153577 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 153588 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 153599 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 153610 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 153622 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 153633 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_1_1_p4_rperrm router_2_1_1_p4_rperrm PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 153892 R2_1 register p4_rperrm 0x48118 R/W 0x00000000 Pcie_noc_router_2_1_1_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 153656 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 153667 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 153678 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 153689 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 153700 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 153711 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 153722 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 153733 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 153745 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 153756 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 153767 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 153778 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 153790 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 153801 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 153812 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 153823 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 153835 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 153846 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 153857 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 153868 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 153880 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 153891 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_3_3_re router_2_3_3_re PCIE_NOC_ROUTER_2_3_3_RE_ADDRESS PCIE_NOC_ROUTER_2_3_3_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_RE_OFFSET PCIE_NOC_ROUTER_2_3_3_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 154066 R2_3 register re 0x4C080 R/W 0x00000000 Pcie_noc_router_2_3_3_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_2_3_3_RE_OVFI_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_OVFI_MSB PCIE_NOC_ROUTER_2_3_3_RE_OVFI_LSB PCIE_NOC_ROUTER_2_3_3_RE_OVFI_RANGE PCIE_NOC_ROUTER_2_3_3_RE_OVFI_RESET PCIE_NOC_ROUTER_2_3_3_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_OVFI_GET PCIE_NOC_ROUTER_2_3_3_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 153918 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 153929 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_2_3_3_RE_OVFO_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_OVFO_MSB PCIE_NOC_ROUTER_2_3_3_RE_OVFO_LSB PCIE_NOC_ROUTER_2_3_3_RE_OVFO_RANGE PCIE_NOC_ROUTER_2_3_3_RE_OVFO_RESET PCIE_NOC_ROUTER_2_3_3_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_OVFO_GET PCIE_NOC_ROUTER_2_3_3_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 153943 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 153954 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_2_3_3_RE_PGE_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_PGE_MSB PCIE_NOC_ROUTER_2_3_3_RE_PGE_LSB PCIE_NOC_ROUTER_2_3_3_RE_PGE_RANGE PCIE_NOC_ROUTER_2_3_3_RE_PGE_RESET PCIE_NOC_ROUTER_2_3_3_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_PGE_GET PCIE_NOC_ROUTER_2_3_3_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 153966 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_2_3_3_RE_NLU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_NLU_MSB PCIE_NOC_ROUTER_2_3_3_RE_NLU_LSB PCIE_NOC_ROUTER_2_3_3_RE_NLU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_NLU_RESET PCIE_NOC_ROUTER_2_3_3_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_NLU_GET PCIE_NOC_ROUTER_2_3_3_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 153977 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_2_3_3_RE_ELU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_ELU_MSB PCIE_NOC_ROUTER_2_3_3_RE_ELU_LSB PCIE_NOC_ROUTER_2_3_3_RE_ELU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_ELU_RESET PCIE_NOC_ROUTER_2_3_3_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_ELU_GET PCIE_NOC_ROUTER_2_3_3_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 153988 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_2_3_3_RE_WLU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_WLU_MSB PCIE_NOC_ROUTER_2_3_3_RE_WLU_LSB PCIE_NOC_ROUTER_2_3_3_RE_WLU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_WLU_RESET PCIE_NOC_ROUTER_2_3_3_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_WLU_GET PCIE_NOC_ROUTER_2_3_3_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 153999 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_2_3_3_RE_SLU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_SLU_MSB PCIE_NOC_ROUTER_2_3_3_RE_SLU_LSB PCIE_NOC_ROUTER_2_3_3_RE_SLU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_SLU_RESET PCIE_NOC_ROUTER_2_3_3_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_SLU_GET PCIE_NOC_ROUTER_2_3_3_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 154010 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_2_3_3_RE_HLU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_HLU_MSB PCIE_NOC_ROUTER_2_3_3_RE_HLU_LSB PCIE_NOC_ROUTER_2_3_3_RE_HLU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_HLU_RESET PCIE_NOC_ROUTER_2_3_3_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_HLU_GET PCIE_NOC_ROUTER_2_3_3_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 154021 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_2_3_3_RE_ILU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_ILU_MSB PCIE_NOC_ROUTER_2_3_3_RE_ILU_LSB PCIE_NOC_ROUTER_2_3_3_RE_ILU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_ILU_RESET PCIE_NOC_ROUTER_2_3_3_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_ILU_GET PCIE_NOC_ROUTER_2_3_3_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 154032 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_2_3_3_RE_JLU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_JLU_MSB PCIE_NOC_ROUTER_2_3_3_RE_JLU_LSB PCIE_NOC_ROUTER_2_3_3_RE_JLU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_JLU_RESET PCIE_NOC_ROUTER_2_3_3_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_JLU_GET PCIE_NOC_ROUTER_2_3_3_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 154043 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_2_3_3_RE_KLU_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_KLU_MSB PCIE_NOC_ROUTER_2_3_3_RE_KLU_LSB PCIE_NOC_ROUTER_2_3_3_RE_KLU_RANGE PCIE_NOC_ROUTER_2_3_3_RE_KLU_RESET PCIE_NOC_ROUTER_2_3_3_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_KLU_GET PCIE_NOC_ROUTER_2_3_3_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 154054 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 154065 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_3_3_rem router_2_3_3_rem PCIE_NOC_ROUTER_2_3_3_REM_ADDRESS PCIE_NOC_ROUTER_2_3_3_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_REM_OFFSET PCIE_NOC_ROUTER_2_3_3_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 154239 R2_3 register rem 0x4C088 R/W 0x0001fe00 Pcie_noc_router_2_3_3_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_MSB PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_LSB PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_RANGE PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_RESET PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_GET PCIE_NOC_ROUTER_2_3_3_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 154092 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 154103 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_MSB PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_LSB PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_RANGE PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_RESET PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_GET PCIE_NOC_ROUTER_2_3_3_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 154117 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 154128 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_2_3_3_REM_PGM_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_PGM_MSB PCIE_NOC_ROUTER_2_3_3_REM_PGM_LSB PCIE_NOC_ROUTER_2_3_3_REM_PGM_RANGE PCIE_NOC_ROUTER_2_3_3_REM_PGM_RESET PCIE_NOC_ROUTER_2_3_3_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_PGM_GET PCIE_NOC_ROUTER_2_3_3_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 154139 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_2_3_3_REM_MN_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MN_MSB PCIE_NOC_ROUTER_2_3_3_REM_MN_LSB PCIE_NOC_ROUTER_2_3_3_REM_MN_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MN_RESET PCIE_NOC_ROUTER_2_3_3_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MN_GET PCIE_NOC_ROUTER_2_3_3_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 154150 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_2_3_3_REM_ME_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_ME_MSB PCIE_NOC_ROUTER_2_3_3_REM_ME_LSB PCIE_NOC_ROUTER_2_3_3_REM_ME_RANGE PCIE_NOC_ROUTER_2_3_3_REM_ME_RESET PCIE_NOC_ROUTER_2_3_3_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_ME_GET PCIE_NOC_ROUTER_2_3_3_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 154161 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_2_3_3_REM_MW_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MW_MSB PCIE_NOC_ROUTER_2_3_3_REM_MW_LSB PCIE_NOC_ROUTER_2_3_3_REM_MW_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MW_RESET PCIE_NOC_ROUTER_2_3_3_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MW_GET PCIE_NOC_ROUTER_2_3_3_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 154172 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_2_3_3_REM_MS_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MS_MSB PCIE_NOC_ROUTER_2_3_3_REM_MS_LSB PCIE_NOC_ROUTER_2_3_3_REM_MS_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MS_RESET PCIE_NOC_ROUTER_2_3_3_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MS_GET PCIE_NOC_ROUTER_2_3_3_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 154183 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_2_3_3_REM_MH_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MH_MSB PCIE_NOC_ROUTER_2_3_3_REM_MH_LSB PCIE_NOC_ROUTER_2_3_3_REM_MH_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MH_RESET PCIE_NOC_ROUTER_2_3_3_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MH_GET PCIE_NOC_ROUTER_2_3_3_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 154194 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_2_3_3_REM_MI_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MI_MSB PCIE_NOC_ROUTER_2_3_3_REM_MI_LSB PCIE_NOC_ROUTER_2_3_3_REM_MI_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MI_RESET PCIE_NOC_ROUTER_2_3_3_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MI_GET PCIE_NOC_ROUTER_2_3_3_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 154205 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_2_3_3_REM_MJ_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MJ_MSB PCIE_NOC_ROUTER_2_3_3_REM_MJ_LSB PCIE_NOC_ROUTER_2_3_3_REM_MJ_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MJ_RESET PCIE_NOC_ROUTER_2_3_3_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MJ_GET PCIE_NOC_ROUTER_2_3_3_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 154216 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_2_3_3_REM_MK_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_MK_MSB PCIE_NOC_ROUTER_2_3_3_REM_MK_LSB PCIE_NOC_ROUTER_2_3_3_REM_MK_RANGE PCIE_NOC_ROUTER_2_3_3_REM_MK_RESET PCIE_NOC_ROUTER_2_3_3_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_MK_GET PCIE_NOC_ROUTER_2_3_3_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 154227 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 154238 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_3_3_id router_2_3_3_id PCIE_NOC_ROUTER_2_3_3_ID_ADDRESS PCIE_NOC_ROUTER_2_3_3_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_ID_OFFSET PCIE_NOC_ROUTER_2_3_3_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 154308 R2_3 register id 0x4C0A0 R 0x01000062 Pcie_noc_router_2_3_3_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_2_3_3_ID_LAYER_WIDTH PCIE_NOC_ROUTER_2_3_3_ID_LAYER_MSB PCIE_NOC_ROUTER_2_3_3_ID_LAYER_LSB PCIE_NOC_ROUTER_2_3_3_ID_LAYER_RANGE PCIE_NOC_ROUTER_2_3_3_ID_LAYER_RESET PCIE_NOC_ROUTER_2_3_3_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_ID_LAYER_GET PCIE_NOC_ROUTER_2_3_3_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 154264 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS PCIE_NOC_ROUTER_2_3_3_ID_POS_WIDTH PCIE_NOC_ROUTER_2_3_3_ID_POS_MSB PCIE_NOC_ROUTER_2_3_3_ID_POS_LSB PCIE_NOC_ROUTER_2_3_3_ID_POS_RANGE PCIE_NOC_ROUTER_2_3_3_ID_POS_RESET PCIE_NOC_ROUTER_2_3_3_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_ID_POS_GET PCIE_NOC_ROUTER_2_3_3_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 154275 POS 16-bit position ID of this router in the NoC 20 5 0x0003 R ZERO PCIE_NOC_ROUTER_2_3_3_ID_ZERO_WIDTH PCIE_NOC_ROUTER_2_3_3_ID_ZERO_MSB PCIE_NOC_ROUTER_2_3_3_ID_ZERO_LSB PCIE_NOC_ROUTER_2_3_3_ID_ZERO_RANGE PCIE_NOC_ROUTER_2_3_3_ID_ZERO_RESET PCIE_NOC_ROUTER_2_3_3_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_ID_ZERO_GET PCIE_NOC_ROUTER_2_3_3_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 154286 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_2_3_3_ID_ONE_WIDTH PCIE_NOC_ROUTER_2_3_3_ID_ONE_MSB PCIE_NOC_ROUTER_2_3_3_ID_ONE_LSB PCIE_NOC_ROUTER_2_3_3_ID_ONE_RANGE PCIE_NOC_ROUTER_2_3_3_ID_ONE_RESET PCIE_NOC_ROUTER_2_3_3_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_ID_ONE_GET PCIE_NOC_ROUTER_2_3_3_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 154297 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 154307 UNSD_31_25 31 25 0x00 R register pcie_noc.router_2_3_3_rcgo router_2_3_3_rcgo PCIE_NOC_ROUTER_2_3_3_RCGO_ADDRESS PCIE_NOC_ROUTER_2_3_3_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_RCGO_OFFSET PCIE_NOC_ROUTER_2_3_3_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 154347 R2_3 register rcgo 0x4C0B0 R/W 0x00000000 Pcie_noc_router_2_3_3_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_MSB PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_LSB PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_RANGE PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_RESET PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_GET PCIE_NOC_ROUTER_2_3_3_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 154335 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 154346 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_2_3_3_p2_rperr router_2_3_3_p2_rperr PCIE_NOC_ROUTER_2_3_3_P2_RPERR_ADDRESS PCIE_NOC_ROUTER_2_3_3_P2_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_P2_RPERR_OFFSET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 154638 R2_3 register p2_rperr 0x4C0C8 R/W 0x00000000 Pcie_noc_router_2_3_3_p2_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 154390 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 154401 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 154412 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 154423 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 154434 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 154445 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 154456 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 154467 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 154479 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 154490 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 154502 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 154514 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 154527 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 154539 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 154551 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 154563 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 154576 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 154588 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 154600 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 154612 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 154625 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 154637 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_3_3_p3_rperr router_2_3_3_p3_rperr PCIE_NOC_ROUTER_2_3_3_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_2_3_3_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_P3_RPERR_OFFSET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 154929 R2_3 register p3_rperr 0x4C0D0 R/W 0x00000000 Pcie_noc_router_2_3_3_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 154681 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 154692 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 154703 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 154714 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 154725 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 154736 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 154747 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 154758 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 154770 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 154781 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 154793 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 154805 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 154818 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 154830 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 154842 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 154854 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 154867 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 154879 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 154891 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 154903 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 154916 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 154928 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_3_3_p4_rperr router_2_3_3_p4_rperr PCIE_NOC_ROUTER_2_3_3_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_2_3_3_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_P4_RPERR_OFFSET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 155220 R2_3 register p4_rperr 0x4C0D8 R/W 0x00000000 Pcie_noc_router_2_3_3_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 154972 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 154983 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 154994 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 155005 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 155016 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 155027 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 155038 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 155049 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 155061 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 155072 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 155084 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 155096 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 155109 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 155121 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 155133 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 155145 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 155158 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 155170 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 155182 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 155194 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 155207 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 155219 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_3_3_p2_rperrm router_2_3_3_p2_rperrm PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_OFFSET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 155478 R2_3 register p2_rperrm 0x4C108 R/W 0x00000000 Pcie_noc_router_2_3_3_p2_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 155242 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 155253 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 155264 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 155275 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 155286 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 155297 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 155308 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 155319 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 155331 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 155342 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 155353 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 155364 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 155376 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 155387 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 155398 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 155409 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 155421 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 155432 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 155443 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 155454 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 155466 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 155477 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_3_3_p3_rperrm router_2_3_3_p3_rperrm PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 155736 R2_3 register p3_rperrm 0x4C110 R/W 0x00000000 Pcie_noc_router_2_3_3_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 155500 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 155511 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 155522 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 155533 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 155544 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 155555 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 155566 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 155577 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 155589 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 155600 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 155611 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 155622 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 155634 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 155645 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 155656 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 155667 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 155679 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 155690 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 155701 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 155712 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 155724 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 155735 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_3_3_p4_rperrm router_2_3_3_p4_rperrm PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 155994 R2_3 register p4_rperrm 0x4C118 R/W 0x00000000 Pcie_noc_router_2_3_3_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 155758 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 155769 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 155780 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 155791 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 155802 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 155813 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 155824 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 155835 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 155847 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 155858 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 155869 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 155880 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 155892 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 155903 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 155914 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 155925 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 155937 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 155948 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 155959 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 155970 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 155982 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 155993 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_5_5_re router_2_5_5_re PCIE_NOC_ROUTER_2_5_5_RE_ADDRESS PCIE_NOC_ROUTER_2_5_5_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_RE_OFFSET PCIE_NOC_ROUTER_2_5_5_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 156168 R2_5 register re 0x50080 R/W 0x00000000 Pcie_noc_router_2_5_5_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_2_5_5_RE_OVFI_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_OVFI_MSB PCIE_NOC_ROUTER_2_5_5_RE_OVFI_LSB PCIE_NOC_ROUTER_2_5_5_RE_OVFI_RANGE PCIE_NOC_ROUTER_2_5_5_RE_OVFI_RESET PCIE_NOC_ROUTER_2_5_5_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_OVFI_GET PCIE_NOC_ROUTER_2_5_5_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 156020 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 156031 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_2_5_5_RE_OVFO_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_OVFO_MSB PCIE_NOC_ROUTER_2_5_5_RE_OVFO_LSB PCIE_NOC_ROUTER_2_5_5_RE_OVFO_RANGE PCIE_NOC_ROUTER_2_5_5_RE_OVFO_RESET PCIE_NOC_ROUTER_2_5_5_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_OVFO_GET PCIE_NOC_ROUTER_2_5_5_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 156045 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 156056 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_2_5_5_RE_PGE_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_PGE_MSB PCIE_NOC_ROUTER_2_5_5_RE_PGE_LSB PCIE_NOC_ROUTER_2_5_5_RE_PGE_RANGE PCIE_NOC_ROUTER_2_5_5_RE_PGE_RESET PCIE_NOC_ROUTER_2_5_5_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_PGE_GET PCIE_NOC_ROUTER_2_5_5_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 156068 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_2_5_5_RE_NLU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_NLU_MSB PCIE_NOC_ROUTER_2_5_5_RE_NLU_LSB PCIE_NOC_ROUTER_2_5_5_RE_NLU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_NLU_RESET PCIE_NOC_ROUTER_2_5_5_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_NLU_GET PCIE_NOC_ROUTER_2_5_5_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 156079 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_2_5_5_RE_ELU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_ELU_MSB PCIE_NOC_ROUTER_2_5_5_RE_ELU_LSB PCIE_NOC_ROUTER_2_5_5_RE_ELU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_ELU_RESET PCIE_NOC_ROUTER_2_5_5_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_ELU_GET PCIE_NOC_ROUTER_2_5_5_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 156090 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_2_5_5_RE_WLU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_WLU_MSB PCIE_NOC_ROUTER_2_5_5_RE_WLU_LSB PCIE_NOC_ROUTER_2_5_5_RE_WLU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_WLU_RESET PCIE_NOC_ROUTER_2_5_5_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_WLU_GET PCIE_NOC_ROUTER_2_5_5_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 156101 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_2_5_5_RE_SLU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_SLU_MSB PCIE_NOC_ROUTER_2_5_5_RE_SLU_LSB PCIE_NOC_ROUTER_2_5_5_RE_SLU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_SLU_RESET PCIE_NOC_ROUTER_2_5_5_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_SLU_GET PCIE_NOC_ROUTER_2_5_5_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 156112 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_2_5_5_RE_HLU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_HLU_MSB PCIE_NOC_ROUTER_2_5_5_RE_HLU_LSB PCIE_NOC_ROUTER_2_5_5_RE_HLU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_HLU_RESET PCIE_NOC_ROUTER_2_5_5_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_HLU_GET PCIE_NOC_ROUTER_2_5_5_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 156123 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_2_5_5_RE_ILU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_ILU_MSB PCIE_NOC_ROUTER_2_5_5_RE_ILU_LSB PCIE_NOC_ROUTER_2_5_5_RE_ILU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_ILU_RESET PCIE_NOC_ROUTER_2_5_5_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_ILU_GET PCIE_NOC_ROUTER_2_5_5_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 156134 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_2_5_5_RE_JLU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_JLU_MSB PCIE_NOC_ROUTER_2_5_5_RE_JLU_LSB PCIE_NOC_ROUTER_2_5_5_RE_JLU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_JLU_RESET PCIE_NOC_ROUTER_2_5_5_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_JLU_GET PCIE_NOC_ROUTER_2_5_5_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 156145 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_2_5_5_RE_KLU_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_KLU_MSB PCIE_NOC_ROUTER_2_5_5_RE_KLU_LSB PCIE_NOC_ROUTER_2_5_5_RE_KLU_RANGE PCIE_NOC_ROUTER_2_5_5_RE_KLU_RESET PCIE_NOC_ROUTER_2_5_5_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_KLU_GET PCIE_NOC_ROUTER_2_5_5_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 156156 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 156167 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_5_5_rem router_2_5_5_rem PCIE_NOC_ROUTER_2_5_5_REM_ADDRESS PCIE_NOC_ROUTER_2_5_5_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_REM_OFFSET PCIE_NOC_ROUTER_2_5_5_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 156341 R2_5 register rem 0x50088 R/W 0x0001fe00 Pcie_noc_router_2_5_5_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_MSB PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_LSB PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_RANGE PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_RESET PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_GET PCIE_NOC_ROUTER_2_5_5_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 156194 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 156205 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_MSB PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_LSB PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_RANGE PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_RESET PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_GET PCIE_NOC_ROUTER_2_5_5_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 156219 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 156230 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_2_5_5_REM_PGM_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_PGM_MSB PCIE_NOC_ROUTER_2_5_5_REM_PGM_LSB PCIE_NOC_ROUTER_2_5_5_REM_PGM_RANGE PCIE_NOC_ROUTER_2_5_5_REM_PGM_RESET PCIE_NOC_ROUTER_2_5_5_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_PGM_GET PCIE_NOC_ROUTER_2_5_5_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 156241 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_2_5_5_REM_MN_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MN_MSB PCIE_NOC_ROUTER_2_5_5_REM_MN_LSB PCIE_NOC_ROUTER_2_5_5_REM_MN_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MN_RESET PCIE_NOC_ROUTER_2_5_5_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MN_GET PCIE_NOC_ROUTER_2_5_5_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 156252 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_2_5_5_REM_ME_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_ME_MSB PCIE_NOC_ROUTER_2_5_5_REM_ME_LSB PCIE_NOC_ROUTER_2_5_5_REM_ME_RANGE PCIE_NOC_ROUTER_2_5_5_REM_ME_RESET PCIE_NOC_ROUTER_2_5_5_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_ME_GET PCIE_NOC_ROUTER_2_5_5_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 156263 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_2_5_5_REM_MW_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MW_MSB PCIE_NOC_ROUTER_2_5_5_REM_MW_LSB PCIE_NOC_ROUTER_2_5_5_REM_MW_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MW_RESET PCIE_NOC_ROUTER_2_5_5_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MW_GET PCIE_NOC_ROUTER_2_5_5_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 156274 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_2_5_5_REM_MS_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MS_MSB PCIE_NOC_ROUTER_2_5_5_REM_MS_LSB PCIE_NOC_ROUTER_2_5_5_REM_MS_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MS_RESET PCIE_NOC_ROUTER_2_5_5_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MS_GET PCIE_NOC_ROUTER_2_5_5_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 156285 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_2_5_5_REM_MH_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MH_MSB PCIE_NOC_ROUTER_2_5_5_REM_MH_LSB PCIE_NOC_ROUTER_2_5_5_REM_MH_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MH_RESET PCIE_NOC_ROUTER_2_5_5_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MH_GET PCIE_NOC_ROUTER_2_5_5_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 156296 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_2_5_5_REM_MI_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MI_MSB PCIE_NOC_ROUTER_2_5_5_REM_MI_LSB PCIE_NOC_ROUTER_2_5_5_REM_MI_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MI_RESET PCIE_NOC_ROUTER_2_5_5_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MI_GET PCIE_NOC_ROUTER_2_5_5_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 156307 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_2_5_5_REM_MJ_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MJ_MSB PCIE_NOC_ROUTER_2_5_5_REM_MJ_LSB PCIE_NOC_ROUTER_2_5_5_REM_MJ_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MJ_RESET PCIE_NOC_ROUTER_2_5_5_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MJ_GET PCIE_NOC_ROUTER_2_5_5_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 156318 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_2_5_5_REM_MK_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_MK_MSB PCIE_NOC_ROUTER_2_5_5_REM_MK_LSB PCIE_NOC_ROUTER_2_5_5_REM_MK_RANGE PCIE_NOC_ROUTER_2_5_5_REM_MK_RESET PCIE_NOC_ROUTER_2_5_5_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_MK_GET PCIE_NOC_ROUTER_2_5_5_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 156329 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 156340 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_5_5_id router_2_5_5_id PCIE_NOC_ROUTER_2_5_5_ID_ADDRESS PCIE_NOC_ROUTER_2_5_5_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_ID_OFFSET PCIE_NOC_ROUTER_2_5_5_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 156410 R2_5 register id 0x500A0 R 0x010000a2 Pcie_noc_router_2_5_5_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_2_5_5_ID_LAYER_WIDTH PCIE_NOC_ROUTER_2_5_5_ID_LAYER_MSB PCIE_NOC_ROUTER_2_5_5_ID_LAYER_LSB PCIE_NOC_ROUTER_2_5_5_ID_LAYER_RANGE PCIE_NOC_ROUTER_2_5_5_ID_LAYER_RESET PCIE_NOC_ROUTER_2_5_5_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_ID_LAYER_GET PCIE_NOC_ROUTER_2_5_5_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 156366 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS PCIE_NOC_ROUTER_2_5_5_ID_POS_WIDTH PCIE_NOC_ROUTER_2_5_5_ID_POS_MSB PCIE_NOC_ROUTER_2_5_5_ID_POS_LSB PCIE_NOC_ROUTER_2_5_5_ID_POS_RANGE PCIE_NOC_ROUTER_2_5_5_ID_POS_RESET PCIE_NOC_ROUTER_2_5_5_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_ID_POS_GET PCIE_NOC_ROUTER_2_5_5_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 156377 POS 16-bit position ID of this router in the NoC 20 5 0x0005 R ZERO PCIE_NOC_ROUTER_2_5_5_ID_ZERO_WIDTH PCIE_NOC_ROUTER_2_5_5_ID_ZERO_MSB PCIE_NOC_ROUTER_2_5_5_ID_ZERO_LSB PCIE_NOC_ROUTER_2_5_5_ID_ZERO_RANGE PCIE_NOC_ROUTER_2_5_5_ID_ZERO_RESET PCIE_NOC_ROUTER_2_5_5_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_ID_ZERO_GET PCIE_NOC_ROUTER_2_5_5_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 156388 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_2_5_5_ID_ONE_WIDTH PCIE_NOC_ROUTER_2_5_5_ID_ONE_MSB PCIE_NOC_ROUTER_2_5_5_ID_ONE_LSB PCIE_NOC_ROUTER_2_5_5_ID_ONE_RANGE PCIE_NOC_ROUTER_2_5_5_ID_ONE_RESET PCIE_NOC_ROUTER_2_5_5_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_ID_ONE_GET PCIE_NOC_ROUTER_2_5_5_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 156399 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 156409 UNSD_31_25 31 25 0x00 R register pcie_noc.router_2_5_5_rcgo router_2_5_5_rcgo PCIE_NOC_ROUTER_2_5_5_RCGO_ADDRESS PCIE_NOC_ROUTER_2_5_5_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_RCGO_OFFSET PCIE_NOC_ROUTER_2_5_5_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 156449 R2_5 register rcgo 0x500B0 R/W 0x00000000 Pcie_noc_router_2_5_5_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_MSB PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_LSB PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_RANGE PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_RESET PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_GET PCIE_NOC_ROUTER_2_5_5_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 156437 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 156448 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_2_5_5_p0_rperr router_2_5_5_p0_rperr PCIE_NOC_ROUTER_2_5_5_P0_RPERR_ADDRESS PCIE_NOC_ROUTER_2_5_5_P0_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_P0_RPERR_OFFSET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 156740 R2_5 register p0_rperr 0x500B8 R/W 0x00000000 Pcie_noc_router_2_5_5_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 156492 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 156503 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 156514 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 156525 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 156536 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 156547 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 156558 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 156569 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 156581 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 156592 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 156604 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 156616 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 156629 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 156641 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 156653 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 156665 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 156678 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 156690 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 156702 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 156714 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 156727 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 156739 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_5_5_p1_rperr router_2_5_5_p1_rperr PCIE_NOC_ROUTER_2_5_5_P1_RPERR_ADDRESS PCIE_NOC_ROUTER_2_5_5_P1_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_P1_RPERR_OFFSET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 157031 R2_5 register p1_rperr 0x500C0 R/W 0x00000000 Pcie_noc_router_2_5_5_p1_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 156783 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 156794 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 156805 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 156816 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 156827 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 156838 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 156849 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 156860 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 156872 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 156883 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 156895 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 156907 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 156920 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 156932 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 156944 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 156956 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 156969 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 156981 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 156993 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 157005 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 157018 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 157030 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_5_5_p4_rperr router_2_5_5_p4_rperr PCIE_NOC_ROUTER_2_5_5_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_2_5_5_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_P4_RPERR_OFFSET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 157322 R2_5 register p4_rperr 0x500D8 R/W 0x00000000 Pcie_noc_router_2_5_5_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 157074 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 157085 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 157096 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 157107 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 157118 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 157129 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 157140 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 157151 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 157163 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 157174 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 157186 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 157198 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 157211 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 157223 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 157235 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 157247 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 157260 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 157272 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 157284 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 157296 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 157309 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 157321 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_5_5_p0_rperrm router_2_5_5_p0_rperrm PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_OFFSET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 157580 R2_5 register p0_rperrm 0x500F8 R/W 0x00000000 Pcie_noc_router_2_5_5_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 157344 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 157355 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 157366 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 157377 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 157388 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 157399 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 157410 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 157421 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 157433 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 157444 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 157455 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 157466 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 157478 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 157489 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 157500 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 157511 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 157523 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 157534 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 157545 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 157556 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 157568 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 157579 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_5_5_p1_rperrm router_2_5_5_p1_rperrm PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_OFFSET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 157838 R2_5 register p1_rperrm 0x50100 R/W 0x00000000 Pcie_noc_router_2_5_5_p1_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 157602 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 157613 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 157624 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 157635 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 157646 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 157657 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 157668 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 157679 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 157691 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 157702 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 157713 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 157724 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 157736 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 157747 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 157758 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 157769 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 157781 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 157792 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 157803 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 157814 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 157826 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 157837 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_5_5_p4_rperrm router_2_5_5_p4_rperrm PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 158096 R2_5 register p4_rperrm 0x50118 R/W 0x00000000 Pcie_noc_router_2_5_5_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 157860 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 157871 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 157882 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 157893 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 157904 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 157915 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 157926 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 157937 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 157949 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 157960 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 157971 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 157982 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 157994 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 158005 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 158016 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 158027 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 158039 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 158050 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 158061 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 158072 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 158084 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 158095 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_7_7_re router_2_7_7_re PCIE_NOC_ROUTER_2_7_7_RE_ADDRESS PCIE_NOC_ROUTER_2_7_7_RE_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_RE_OFFSET PCIE_NOC_ROUTER_2_7_7_RE_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 158270 R2_7 register re 0x54080 R/W 0x00000000 Pcie_noc_router_2_7_7_re This register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared. false false false false OVFI PCIE_NOC_ROUTER_2_7_7_RE_OVFI_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_OVFI_MSB PCIE_NOC_ROUTER_2_7_7_RE_OVFI_LSB PCIE_NOC_ROUTER_2_7_7_RE_OVFI_RANGE PCIE_NOC_ROUTER_2_7_7_RE_OVFI_RESET PCIE_NOC_ROUTER_2_7_7_RE_OVFI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_OVFI_GET PCIE_NOC_ROUTER_2_7_7_RE_OVFI_SET ns_noc_io_pcie_soc_ip.csr 158122 OVFI 1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 0 0 0x0 R/W CSR_PARERR PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_MSB PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_LSB PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_RANGE PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_RESET PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_GET PCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_SET ns_noc_io_pcie_soc_ip.csr 158133 CSR_PARERR 1'b1: Parity error in config/status registers 1 1 0x0 R/W OVFO PCIE_NOC_ROUTER_2_7_7_RE_OVFO_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_OVFO_MSB PCIE_NOC_ROUTER_2_7_7_RE_OVFO_LSB PCIE_NOC_ROUTER_2_7_7_RE_OVFO_RANGE PCIE_NOC_ROUTER_2_7_7_RE_OVFO_RESET PCIE_NOC_ROUTER_2_7_7_RE_OVFO_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_OVFO_GET PCIE_NOC_ROUTER_2_7_7_RE_OVFO_SET ns_noc_io_pcie_soc_ip.csr 158147 OVFO 1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit 1'b0: To clear 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_GET PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 158158 UNSD_7_3 7 3 0x00 R PGE PCIE_NOC_ROUTER_2_7_7_RE_PGE_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_PGE_MSB PCIE_NOC_ROUTER_2_7_7_RE_PGE_LSB PCIE_NOC_ROUTER_2_7_7_RE_PGE_RANGE PCIE_NOC_ROUTER_2_7_7_RE_PGE_RESET PCIE_NOC_ROUTER_2_7_7_RE_PGE_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_PGE_GET PCIE_NOC_ROUTER_2_7_7_RE_PGE_SET ns_noc_io_pcie_soc_ip.csr 158170 PGE 1'b1: Power gating error, traffic received after router commited to power down 8 8 0x0 R/W NLU PCIE_NOC_ROUTER_2_7_7_RE_NLU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_NLU_MSB PCIE_NOC_ROUTER_2_7_7_RE_NLU_LSB PCIE_NOC_ROUTER_2_7_7_RE_NLU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_NLU_RESET PCIE_NOC_ROUTER_2_7_7_RE_NLU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_NLU_GET PCIE_NOC_ROUTER_2_7_7_RE_NLU_SET ns_noc_io_pcie_soc_ip.csr 158181 NLU 1'b1: Traffic destined for North link which is unavailable 9 9 0x0 R/W ELU PCIE_NOC_ROUTER_2_7_7_RE_ELU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_ELU_MSB PCIE_NOC_ROUTER_2_7_7_RE_ELU_LSB PCIE_NOC_ROUTER_2_7_7_RE_ELU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_ELU_RESET PCIE_NOC_ROUTER_2_7_7_RE_ELU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_ELU_GET PCIE_NOC_ROUTER_2_7_7_RE_ELU_SET ns_noc_io_pcie_soc_ip.csr 158192 ELU 1'b1: Traffic destined for East link which is unavailable 10 10 0x0 R/W WLU PCIE_NOC_ROUTER_2_7_7_RE_WLU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_WLU_MSB PCIE_NOC_ROUTER_2_7_7_RE_WLU_LSB PCIE_NOC_ROUTER_2_7_7_RE_WLU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_WLU_RESET PCIE_NOC_ROUTER_2_7_7_RE_WLU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_WLU_GET PCIE_NOC_ROUTER_2_7_7_RE_WLU_SET ns_noc_io_pcie_soc_ip.csr 158203 WLU 1'b1: Traffic destined for West link which is unavailable 11 11 0x0 R/W SLU PCIE_NOC_ROUTER_2_7_7_RE_SLU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_SLU_MSB PCIE_NOC_ROUTER_2_7_7_RE_SLU_LSB PCIE_NOC_ROUTER_2_7_7_RE_SLU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_SLU_RESET PCIE_NOC_ROUTER_2_7_7_RE_SLU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_SLU_GET PCIE_NOC_ROUTER_2_7_7_RE_SLU_SET ns_noc_io_pcie_soc_ip.csr 158214 SLU 1'b1: Traffic destined for South link which is unavailable 12 12 0x0 R/W HLU PCIE_NOC_ROUTER_2_7_7_RE_HLU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_HLU_MSB PCIE_NOC_ROUTER_2_7_7_RE_HLU_LSB PCIE_NOC_ROUTER_2_7_7_RE_HLU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_HLU_RESET PCIE_NOC_ROUTER_2_7_7_RE_HLU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_HLU_GET PCIE_NOC_ROUTER_2_7_7_RE_HLU_SET ns_noc_io_pcie_soc_ip.csr 158225 HLU 1'b1: Traffic destined for H link which is unavailable 13 13 0x0 R/W ILU PCIE_NOC_ROUTER_2_7_7_RE_ILU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_ILU_MSB PCIE_NOC_ROUTER_2_7_7_RE_ILU_LSB PCIE_NOC_ROUTER_2_7_7_RE_ILU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_ILU_RESET PCIE_NOC_ROUTER_2_7_7_RE_ILU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_ILU_GET PCIE_NOC_ROUTER_2_7_7_RE_ILU_SET ns_noc_io_pcie_soc_ip.csr 158236 ILU 1'b1: Traffic destined for I link which is unavailable 14 14 0x0 R/W JLU PCIE_NOC_ROUTER_2_7_7_RE_JLU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_JLU_MSB PCIE_NOC_ROUTER_2_7_7_RE_JLU_LSB PCIE_NOC_ROUTER_2_7_7_RE_JLU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_JLU_RESET PCIE_NOC_ROUTER_2_7_7_RE_JLU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_JLU_GET PCIE_NOC_ROUTER_2_7_7_RE_JLU_SET ns_noc_io_pcie_soc_ip.csr 158247 JLU 1'b1: Traffic destined for J link which is unavailable 15 15 0x0 R/W KLU PCIE_NOC_ROUTER_2_7_7_RE_KLU_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_KLU_MSB PCIE_NOC_ROUTER_2_7_7_RE_KLU_LSB PCIE_NOC_ROUTER_2_7_7_RE_KLU_RANGE PCIE_NOC_ROUTER_2_7_7_RE_KLU_RESET PCIE_NOC_ROUTER_2_7_7_RE_KLU_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_KLU_GET PCIE_NOC_ROUTER_2_7_7_RE_KLU_SET ns_noc_io_pcie_soc_ip.csr 158258 KLU 1'b1: Traffic destined for K link which is unavailable 16 16 0x0 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_GET PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 158269 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_7_7_rem router_2_7_7_rem PCIE_NOC_ROUTER_2_7_7_REM_ADDRESS PCIE_NOC_ROUTER_2_7_7_REM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_REM_OFFSET PCIE_NOC_ROUTER_2_7_7_REM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 158443 R2_7 register rem 0x54088 R/W 0x0001fe00 Pcie_noc_router_2_7_7_rem This register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to. false false false false OVFIM PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_MSB PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_LSB PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_RANGE PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_RESET PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_GET PCIE_NOC_ROUTER_2_7_7_REM_OVFIM_SET ns_noc_io_pcie_soc_ip.csr 158296 OVFIM 1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 0 0 0x0 R/W CSR_PARERRM PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_MSB PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_LSB PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_RANGE PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_RESET PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_GET PCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_SET ns_noc_io_pcie_soc_ip.csr 158307 CSR_PARERRM 1'b1: Mask CSR parity error interrupt 1 1 0x0 R/W OVFOM PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_MSB PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_LSB PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_RANGE PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_RESET PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_GET PCIE_NOC_ROUTER_2_7_7_REM_OVFOM_SET ns_noc_io_pcie_soc_ip.csr 158321 OVFOM 1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE) 1'b0: Enables an interrupt to be generated when event counter status bit is set 2 2 0x0 R/W UNSD_7_3 PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_MSB PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_LSB PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_RANGE PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_RESET PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_GET PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_SET ns_noc_io_pcie_soc_ip.csr 158332 UNSD_7_3 7 3 0x00 R PGM PCIE_NOC_ROUTER_2_7_7_REM_PGM_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_PGM_MSB PCIE_NOC_ROUTER_2_7_7_REM_PGM_LSB PCIE_NOC_ROUTER_2_7_7_REM_PGM_RANGE PCIE_NOC_ROUTER_2_7_7_REM_PGM_RESET PCIE_NOC_ROUTER_2_7_7_REM_PGM_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_PGM_GET PCIE_NOC_ROUTER_2_7_7_REM_PGM_SET ns_noc_io_pcie_soc_ip.csr 158343 PGM 1'b1: Mask PGE error interrupt 8 8 0x0 R/W MN PCIE_NOC_ROUTER_2_7_7_REM_MN_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MN_MSB PCIE_NOC_ROUTER_2_7_7_REM_MN_LSB PCIE_NOC_ROUTER_2_7_7_REM_MN_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MN_RESET PCIE_NOC_ROUTER_2_7_7_REM_MN_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MN_GET PCIE_NOC_ROUTER_2_7_7_REM_MN_SET ns_noc_io_pcie_soc_ip.csr 158354 MN 1'b1: Mask NLU error interrupt 9 9 0x1 R/W ME PCIE_NOC_ROUTER_2_7_7_REM_ME_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_ME_MSB PCIE_NOC_ROUTER_2_7_7_REM_ME_LSB PCIE_NOC_ROUTER_2_7_7_REM_ME_RANGE PCIE_NOC_ROUTER_2_7_7_REM_ME_RESET PCIE_NOC_ROUTER_2_7_7_REM_ME_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_ME_GET PCIE_NOC_ROUTER_2_7_7_REM_ME_SET ns_noc_io_pcie_soc_ip.csr 158365 ME 1'b1: Mask ELU error interrupt 10 10 0x1 R/W MW PCIE_NOC_ROUTER_2_7_7_REM_MW_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MW_MSB PCIE_NOC_ROUTER_2_7_7_REM_MW_LSB PCIE_NOC_ROUTER_2_7_7_REM_MW_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MW_RESET PCIE_NOC_ROUTER_2_7_7_REM_MW_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MW_GET PCIE_NOC_ROUTER_2_7_7_REM_MW_SET ns_noc_io_pcie_soc_ip.csr 158376 MW 1'b1: Mask WLU error interrupt 11 11 0x1 R/W MS PCIE_NOC_ROUTER_2_7_7_REM_MS_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MS_MSB PCIE_NOC_ROUTER_2_7_7_REM_MS_LSB PCIE_NOC_ROUTER_2_7_7_REM_MS_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MS_RESET PCIE_NOC_ROUTER_2_7_7_REM_MS_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MS_GET PCIE_NOC_ROUTER_2_7_7_REM_MS_SET ns_noc_io_pcie_soc_ip.csr 158387 MS 1'b1: Mask SLU error interrupt 12 12 0x1 R/W MH PCIE_NOC_ROUTER_2_7_7_REM_MH_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MH_MSB PCIE_NOC_ROUTER_2_7_7_REM_MH_LSB PCIE_NOC_ROUTER_2_7_7_REM_MH_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MH_RESET PCIE_NOC_ROUTER_2_7_7_REM_MH_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MH_GET PCIE_NOC_ROUTER_2_7_7_REM_MH_SET ns_noc_io_pcie_soc_ip.csr 158398 MH 1'b1: Mask HLU error interrupt 13 13 0x1 R/W MI PCIE_NOC_ROUTER_2_7_7_REM_MI_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MI_MSB PCIE_NOC_ROUTER_2_7_7_REM_MI_LSB PCIE_NOC_ROUTER_2_7_7_REM_MI_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MI_RESET PCIE_NOC_ROUTER_2_7_7_REM_MI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MI_GET PCIE_NOC_ROUTER_2_7_7_REM_MI_SET ns_noc_io_pcie_soc_ip.csr 158409 MI 1'b1: Mask ILU error interrupt 14 14 0x1 R/W MJ PCIE_NOC_ROUTER_2_7_7_REM_MJ_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MJ_MSB PCIE_NOC_ROUTER_2_7_7_REM_MJ_LSB PCIE_NOC_ROUTER_2_7_7_REM_MJ_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MJ_RESET PCIE_NOC_ROUTER_2_7_7_REM_MJ_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MJ_GET PCIE_NOC_ROUTER_2_7_7_REM_MJ_SET ns_noc_io_pcie_soc_ip.csr 158420 MJ 1'b1: Mask JLU error interrupt 15 15 0x1 R/W MK PCIE_NOC_ROUTER_2_7_7_REM_MK_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_MK_MSB PCIE_NOC_ROUTER_2_7_7_REM_MK_LSB PCIE_NOC_ROUTER_2_7_7_REM_MK_RANGE PCIE_NOC_ROUTER_2_7_7_REM_MK_RESET PCIE_NOC_ROUTER_2_7_7_REM_MK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_MK_GET PCIE_NOC_ROUTER_2_7_7_REM_MK_SET ns_noc_io_pcie_soc_ip.csr 158431 MK 1'b1: Mask KLU error interrupt 16 16 0x1 R/W UNSD_31_14 PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_WIDTH PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_MSB PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_LSB PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_RANGE PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_RESET PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_GET PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_SET ns_noc_io_pcie_soc_ip.csr 158442 UNSD_31_14 31 17 0x0000 R register pcie_noc.router_2_7_7_id router_2_7_7_id PCIE_NOC_ROUTER_2_7_7_ID_ADDRESS PCIE_NOC_ROUTER_2_7_7_ID_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_ID_OFFSET PCIE_NOC_ROUTER_2_7_7_ID_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 158512 R2_7 register id 0x540A0 R 0x010000e2 Pcie_noc_router_2_7_7_id This register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element. false false false false LAYER PCIE_NOC_ROUTER_2_7_7_ID_LAYER_WIDTH PCIE_NOC_ROUTER_2_7_7_ID_LAYER_MSB PCIE_NOC_ROUTER_2_7_7_ID_LAYER_LSB PCIE_NOC_ROUTER_2_7_7_ID_LAYER_RANGE PCIE_NOC_ROUTER_2_7_7_ID_LAYER_RESET PCIE_NOC_ROUTER_2_7_7_ID_LAYER_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_ID_LAYER_GET PCIE_NOC_ROUTER_2_7_7_ID_LAYER_SET ns_noc_io_pcie_soc_ip.csr 158468 LAYER 5-bit identifier of the NoC layer on which this router is located 4 0 0x02 R POS PCIE_NOC_ROUTER_2_7_7_ID_POS_WIDTH PCIE_NOC_ROUTER_2_7_7_ID_POS_MSB PCIE_NOC_ROUTER_2_7_7_ID_POS_LSB PCIE_NOC_ROUTER_2_7_7_ID_POS_RANGE PCIE_NOC_ROUTER_2_7_7_ID_POS_RESET PCIE_NOC_ROUTER_2_7_7_ID_POS_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_ID_POS_GET PCIE_NOC_ROUTER_2_7_7_ID_POS_SET ns_noc_io_pcie_soc_ip.csr 158479 POS 16-bit position ID of this router in the NoC 20 5 0x0007 R ZERO PCIE_NOC_ROUTER_2_7_7_ID_ZERO_WIDTH PCIE_NOC_ROUTER_2_7_7_ID_ZERO_MSB PCIE_NOC_ROUTER_2_7_7_ID_ZERO_LSB PCIE_NOC_ROUTER_2_7_7_ID_ZERO_RANGE PCIE_NOC_ROUTER_2_7_7_ID_ZERO_RESET PCIE_NOC_ROUTER_2_7_7_ID_ZERO_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_ID_ZERO_GET PCIE_NOC_ROUTER_2_7_7_ID_ZERO_SET ns_noc_io_pcie_soc_ip.csr 158490 ZERO Zeroes 23 21 0x0 R ONE PCIE_NOC_ROUTER_2_7_7_ID_ONE_WIDTH PCIE_NOC_ROUTER_2_7_7_ID_ONE_MSB PCIE_NOC_ROUTER_2_7_7_ID_ONE_LSB PCIE_NOC_ROUTER_2_7_7_ID_ONE_RANGE PCIE_NOC_ROUTER_2_7_7_ID_ONE_RESET PCIE_NOC_ROUTER_2_7_7_ID_ONE_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_ID_ONE_GET PCIE_NOC_ROUTER_2_7_7_ID_ONE_SET ns_noc_io_pcie_soc_ip.csr 158501 ONE One 24 24 0x1 R UNSD_31_25 PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_WIDTH PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_MSB PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_LSB PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_RANGE PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_RESET PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_GET PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_SET ns_noc_io_pcie_soc_ip.csr 158511 UNSD_31_25 31 25 0x00 R register pcie_noc.router_2_7_7_rcgo router_2_7_7_rcgo PCIE_NOC_ROUTER_2_7_7_RCGO_ADDRESS PCIE_NOC_ROUTER_2_7_7_RCGO_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_RCGO_OFFSET PCIE_NOC_ROUTER_2_7_7_RCGO_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 158551 R2_7 register rcgo 0x540B0 R/W 0x00000000 Pcie_noc_router_2_7_7_rcgo This register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC. false false false false FPO PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_WIDTH PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_MSB PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_LSB PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_RANGE PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_RESET PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_GET PCIE_NOC_ROUTER_2_7_7_RCGO_FPO_SET ns_noc_io_pcie_soc_ip.csr 158539 FPO 1'b1: Coarse clock gating is locally disabled (for fast path) 1'b0: Coarse clock gating is locally enabled 0 0 0x0 R/W UNSD_31_1 PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_WIDTH PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_MSB PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_LSB PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_RANGE PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_RESET PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_GET PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_SET ns_noc_io_pcie_soc_ip.csr 158550 UNSD_31_1 31 1 0x00000000 R register pcie_noc.router_2_7_7_p0_rperr router_2_7_7_p0_rperr PCIE_NOC_ROUTER_2_7_7_P0_RPERR_ADDRESS PCIE_NOC_ROUTER_2_7_7_P0_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_P0_RPERR_OFFSET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 158842 R2_7 register p0_rperr 0x540B8 R/W 0x00000000 Pcie_noc_router_2_7_7_p0_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 158594 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 158605 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 158616 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 158627 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 158638 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 158649 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 158660 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 158671 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 158683 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 158694 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 158706 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 158718 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 158731 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 158743 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 158755 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 158767 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 158780 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 158792 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 158804 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 158816 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 158829 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 158841 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_7_7_p3_rperr router_2_7_7_p3_rperr PCIE_NOC_ROUTER_2_7_7_P3_RPERR_ADDRESS PCIE_NOC_ROUTER_2_7_7_P3_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_P3_RPERR_OFFSET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 159133 R2_7 register p3_rperr 0x540D0 R/W 0x00000000 Pcie_noc_router_2_7_7_p3_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 158885 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 158896 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 158907 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 158918 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 158929 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 158940 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 158951 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 158962 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 158974 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 158985 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 158997 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 159009 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 159022 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 159034 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 159046 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 159058 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 159071 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 159083 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 159095 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 159107 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 159120 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 159132 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_7_7_p4_rperr router_2_7_7_p4_rperr PCIE_NOC_ROUTER_2_7_7_P4_RPERR_ADDRESS PCIE_NOC_ROUTER_2_7_7_P4_RPERR_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_P4_RPERR_OFFSET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 159424 R2_7 register p4_rperr 0x540D8 R/W 0x00000000 Pcie_noc_router_2_7_7_p4_rperr There is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose. - Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router. - User sideband parity: Similar to data field above. - Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit. - Routing information parity: Parity over routing information carried in every flit. - Credit parity: Parity monitored over credits returned downstream port. false false false false D PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_SET ns_noc_io_pcie_soc_ip.csr 159176 D 1'b1: Parity Error in Link Data 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_SET ns_noc_io_pcie_soc_ip.csr 159187 SB 1'b1: Parity Error in Link User Sideband 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_SET ns_noc_io_pcie_soc_ip.csr 159198 PK 1'b1: Parity Error in Link Packet Delineation Controls 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_SET ns_noc_io_pcie_soc_ip.csr 159209 RI 1'b1: Parity Error in Link Routing Information 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_SET ns_noc_io_pcie_soc_ip.csr 159220 CR 1'b1: Parity Error in Link Credit From Downstream Router 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 159231 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_SET ns_noc_io_pcie_soc_ip.csr 159242 D_0 1'b1: Parity Error in VC 0 Buffer Data 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_SET ns_noc_io_pcie_soc_ip.csr 159253 SB_0 1'b1: Parity Error in VC 0 Buffer User Sideband 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_SET ns_noc_io_pcie_soc_ip.csr 159265 PK_0 1'b1: Parity Error in VC 0 Buffer Packet Delineation Controls 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_SET ns_noc_io_pcie_soc_ip.csr 159276 RI_0 1'b1: Parity Error in VC 0 Buffer Routing Information 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_SET ns_noc_io_pcie_soc_ip.csr 159288 D_1 1'b1: Parity Error in VC 1 Buffer Data 20 20 0x0 R SB_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_SET ns_noc_io_pcie_soc_ip.csr 159300 SB_1 1'b1: Parity Error in VC 1 Buffer User Sideband 21 21 0x0 R PK_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_SET ns_noc_io_pcie_soc_ip.csr 159313 PK_1 1'b1: Parity Error in VC 1 Buffer Packet Delineation Controls 22 22 0x0 R RI_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_SET ns_noc_io_pcie_soc_ip.csr 159325 RI_1 1'b1: Parity Error in VC 1 Buffer Routing Information 23 23 0x0 R D_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_SET ns_noc_io_pcie_soc_ip.csr 159337 D_2 1'b1: Parity Error in VC 2 Buffer Data 24 24 0x0 R SB_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_SET ns_noc_io_pcie_soc_ip.csr 159349 SB_2 1'b1: Parity Error in VC 2 Buffer User Sideband 25 25 0x0 R PK_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_SET ns_noc_io_pcie_soc_ip.csr 159362 PK_2 1'b1: Parity Error in VC 2 Buffer Packet Delineation Controls 26 26 0x0 R RI_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_SET ns_noc_io_pcie_soc_ip.csr 159374 RI_2 1'b1: Parity Error in VC 2 Buffer Routing Information 27 27 0x0 R D_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_SET ns_noc_io_pcie_soc_ip.csr 159386 D_3 1'b1: Parity Error in VC 3 Buffer Data 28 28 0x0 R SB_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_SET ns_noc_io_pcie_soc_ip.csr 159398 SB_3 1'b1: Parity Error in VC 3 Buffer User Sideband 29 29 0x0 R PK_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_SET ns_noc_io_pcie_soc_ip.csr 159411 PK_3 1'b1: Parity Error in VC 3 Buffer Packet Delineation Controls 30 30 0x0 R RI_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_SET ns_noc_io_pcie_soc_ip.csr 159423 RI_3 1'b1: Parity Error in VC 3 Buffer Routing Information 31 31 0x0 R register pcie_noc.router_2_7_7_p0_rperrm router_2_7_7_p0_rperrm PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_OFFSET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 159682 R2_7 register p0_rperrm 0x540F8 R/W 0x00000000 Pcie_noc_router_2_7_7_p0_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 159446 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 159457 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 159468 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 159479 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 159490 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 159501 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 159512 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 159523 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 159535 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 159546 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 159557 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 159568 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 159580 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 159591 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 159602 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 159613 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 159625 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 159636 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 159647 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 159658 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 159670 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 159681 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_7_7_p3_rperrm router_2_7_7_p3_rperrm PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_OFFSET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 159940 R2_7 register p3_rperrm 0x54110 R/W 0x00000000 Pcie_noc_router_2_7_7_p3_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 159704 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 159715 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 159726 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 159737 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 159748 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 159759 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 159770 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 159781 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 159793 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 159804 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 159815 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 159826 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 159838 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 159849 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 159860 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 159871 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 159883 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 159894 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 159905 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 159916 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 159928 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 159939 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W register pcie_noc.router_2_7_7_p4_rperrm router_2_7_7_p4_rperrm PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_ADDRESS PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_BYTE_ADDRESS PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_OFFSET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_BYTE_OFFSET ns_noc_io_pcie_soc_ip.csr 160198 R2_7 register p4_rperrm 0x54118 R/W 0x00000000 Pcie_noc_router_2_7_7_p4_rperrm One mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event false false false false D PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_SET ns_noc_io_pcie_soc_ip.csr 159962 D MaskParity Error in Link Data. 0 0 0x0 R/W SB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_SET ns_noc_io_pcie_soc_ip.csr 159973 SB Mask Parity Error in Link User Sideband. 1 1 0x0 R/W PK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_SET ns_noc_io_pcie_soc_ip.csr 159984 PK Mask Parity Error in Link Packet Delineation Controls. 2 2 0x0 R/W RI PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_SET ns_noc_io_pcie_soc_ip.csr 159995 RI Mask Parity Error in Link Routing Information. 3 3 0x0 R/W CR PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_SET ns_noc_io_pcie_soc_ip.csr 160006 CR Mask Parity Error in Link Credit From Downstream Router. 4 4 0x0 R/W UNSD_15_5 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_SET ns_noc_io_pcie_soc_ip.csr 160017 UNSD_15_5 15 5 0x000 R D_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_SET ns_noc_io_pcie_soc_ip.csr 160028 D_0 Mask Parity Error in VC 0 Buffer Data. 16 16 0x0 R/W SB_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_SET ns_noc_io_pcie_soc_ip.csr 160039 SB_0 Mask Parity Error in VC 0 Buffer User Sideband. 17 17 0x0 R/W PK_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_SET ns_noc_io_pcie_soc_ip.csr 160051 PK_0 Mask Parity Error in VC 0 Buffer Packet Delineation Controls. 18 18 0x0 R/W RI_0 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_SET ns_noc_io_pcie_soc_ip.csr 160062 RI_0 Mask Parity Error in VC 0 Buffer Routing Information. 19 19 0x0 R/W D_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_SET ns_noc_io_pcie_soc_ip.csr 160073 D_1 Mask Parity Error in VC 1 Buffer Data. 20 20 0x0 R/W SB_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_SET ns_noc_io_pcie_soc_ip.csr 160084 SB_1 Mask Parity Error in VC 1 Buffer User Sideband. 21 21 0x0 R/W PK_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_SET ns_noc_io_pcie_soc_ip.csr 160096 PK_1 Mask Parity Error in VC 1 Buffer Packet Delineation Controls. 22 22 0x0 R/W RI_1 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_SET ns_noc_io_pcie_soc_ip.csr 160107 RI_1 Mask Parity Error in VC 1 Buffer Routing Information. 23 23 0x0 R/W D_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_SET ns_noc_io_pcie_soc_ip.csr 160118 D_2 Mask Parity Error in VC 2 Buffer Data. 24 24 0x0 R/W SB_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_SET ns_noc_io_pcie_soc_ip.csr 160129 SB_2 Mask Parity Error in VC 2 Buffer User Sideband. 25 25 0x0 R/W PK_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_SET ns_noc_io_pcie_soc_ip.csr 160141 PK_2 Mask Parity Error in VC 2 Buffer Packet Delineation Controls. 26 26 0x0 R/W RI_2 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_SET ns_noc_io_pcie_soc_ip.csr 160152 RI_2 Mask Parity Error in VC 2 Buffer Routing Information. 27 27 0x0 R/W D_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_SET ns_noc_io_pcie_soc_ip.csr 160163 D_3 Mask Parity Error in VC 3 Buffer Data. 28 28 0x0 R/W SB_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_SET ns_noc_io_pcie_soc_ip.csr 160174 SB_3 Mask Parity Error in VC 3 Buffer User Sideband. 29 29 0x0 R/W PK_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_SET ns_noc_io_pcie_soc_ip.csr 160186 PK_3 Mask Parity Error in VC 3 Buffer Packet Delineation Controls. 30 30 0x0 R/W RI_3 PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_WIDTH PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_MSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_LSB PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_RANGE PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_RESET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_FIELD_MASK PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_GET PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_SET ns_noc_io_pcie_soc_ip.csr 160197 RI_3 Mask Parity Error in VC 3 Buffer Routing Information. 31 31 0x0 R/W

Addressmap Information for 'ns_noc_io_pcie_soc_ip'

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