ns_noc_io_pcie_soc_ip.csr/project/jenkins/workspace/Esperanto_DV/soc_hal/esperanto-soc/dv/common/scripts/semifore_css/etsoc_esr.csspcie_nocaddressmappcie_nocpcie_nocns_noc_io_pcie_soc_ip.csr160199R/WPcie_nocMemory map for rbm_mregisterpcie_noc.bridge_rbm_m_13_1_p_0registerpcie_noc.bridge_rbm_m_13_1_p_1registerpcie_noc.bridge_rbm_m_13_1_p_2registerpcie_noc.bridge_rbm_m_13_1_p_3registerpcie_noc.bridge_rbm_m_13_1_txeregisterpcie_noc.bridge_rbm_m_13_1_txemregisterpcie_noc.bridge_rbm_m_13_1_btus_0registerpcie_noc.bridge_rbm_m_13_1_btus_1registerpcie_noc.bridge_rbm_m_13_1_btrl_0registerpcie_noc.bridge_rbm_m_13_1_btrl_1registerpcie_noc.bridge_rbm_m_13_1_btrl_2registerpcie_noc.bridge_rbm_m_13_1_btrl_3registerpcie_noc.bridge_rbm_m_13_1_btperrregisterpcie_noc.bridge_rbm_m_13_1_btperrmregisterpcie_noc.bridge_rbm_m_13_1_rxeregisterpcie_noc.bridge_rbm_m_13_1_rxemregisterpcie_noc.bridge_rbm_m_13_1_brs_0registerpcie_noc.bridge_rbm_m_13_1_brs_1registerpcie_noc.bridge_rbm_m_13_1_brusregisterpcie_noc.bridge_rbm_m_13_1_brperr0registerpcie_noc.bridge_rbm_m_13_1_brperr1registerpcie_noc.bridge_rbm_m_13_1_brperrm0registerpcie_noc.bridge_rbm_m_13_1_brperrm1registerpcie_noc.bridge_rbm_m_13_1_am_tocfgregisterpcie_noc.bridge_rbm_m_13_1_am_osslvregisterpcie_noc.bridge_rbm_m_13_1_am_cgcregisterpcie_noc.bridge_rbm_m_13_1_am_cgoregisterpcie_noc.bridge_rbm_m_13_1_am_cfgregisterpcie_noc.bridge_rbm_m_13_1_am_stsregisterpcie_noc.bridge_rbm_m_13_1_am_bridge_idregisterpcie_noc.bridge_rbm_m_13_1_am_nocver_idregisterpcie_noc.bridge_rbm_m_13_1_am_errregisterpcie_noc.bridge_rbm_m_13_1_am_toslvidregisterpcie_noc.bridge_rbm_m_13_1_am_eraregisterpcie_noc.bridge_rbm_m_13_1_am_ewaregisterpcie_noc.bridge_rbm_m_13_1_am_intmregisterpcie_noc.bridge_rbm_m_13_1_am_caddrregisterpcie_noc.bridge_rbm_m_13_1_am_caddrmskregisterpcie_noc.bridge_rbm_m_13_1_am_ccmd0registerpcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0registerpcie_noc.bridge_rbm_m_13_1_am_cntr0registerpcie_noc.bridge_rbm_m_13_1_am_latnum0registerpcie_noc.bridge_rbm_m_13_1_am_ccmd1registerpcie_noc.bridge_rbm_m_13_1_am_ccmdmsk1registerpcie_noc.bridge_rbm_m_13_1_am_cntr1registerpcie_noc.bridge_rbm_m_13_1_am_latnum1registerpcie_noc.bridge_rbm_m_13_1_am_arovrdregisterpcie_noc.bridge_rbm_m_13_1_am_awovrdregisterpcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_versionregisterpcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_idregisterpcie_noc.bridge_main0_apb_s_6_6_apbslv_slvs_sleep_statusregisterpcie_noc.bridge_main0_apb_s_6_6_as_cgcregisterpcie_noc.bridge_main0_apb_s_6_6_as_cgoregisterpcie_noc.bridge_main0_apb_s_6_6_as_stsregisterpcie_noc.bridge_main0_apb_s_6_6_as_bridge_idregisterpcie_noc.bridge_main0_apb_s_6_6_as_errregisterpcie_noc.bridge_main0_apb_s_6_6_as_intmregisterpcie_noc.bridge_main0_apb_s_6_6_as_ccmdregisterpcie_noc.bridge_main0_apb_s_6_6_as_ccmdmskregisterpcie_noc.bridge_main0_apb_s_6_6_as_cntrregisterpcie_noc.bridge_main0_apb_s_6_6_as_arovrdregisterpcie_noc.bridge_main0_apb_s_6_6_as_awovrdregisterpcie_noc.bridge_main0_apb_s_6_6_p_0registerpcie_noc.bridge_main0_apb_s_6_6_p_1registerpcie_noc.bridge_main0_apb_s_6_6_p_2registerpcie_noc.bridge_main0_apb_s_6_6_p_3registerpcie_noc.bridge_main0_apb_s_6_6_txeregisterpcie_noc.bridge_main0_apb_s_6_6_txemregisterpcie_noc.bridge_main0_apb_s_6_6_btus_0registerpcie_noc.bridge_main0_apb_s_6_6_btus_1registerpcie_noc.bridge_main0_apb_s_6_6_btrl_0registerpcie_noc.bridge_main0_apb_s_6_6_btrl_1registerpcie_noc.bridge_main0_apb_s_6_6_btrl_2registerpcie_noc.bridge_main0_apb_s_6_6_btrl_3registerpcie_noc.bridge_main0_apb_s_6_6_btperrregisterpcie_noc.bridge_main0_apb_s_6_6_btperrmregisterpcie_noc.bridge_main0_apb_s_6_6_rxeregisterpcie_noc.bridge_main0_apb_s_6_6_rxemregisterpcie_noc.bridge_main0_apb_s_6_6_brs_0registerpcie_noc.bridge_main0_apb_s_6_6_brs_1registerpcie_noc.bridge_main0_apb_s_6_6_brusregisterpcie_noc.bridge_main0_apb_s_6_6_brperr0registerpcie_noc.bridge_main0_apb_s_6_6_brperr1registerpcie_noc.bridge_main0_apb_s_6_6_brperrm0registerpcie_noc.bridge_main0_apb_s_6_6_brperrm1registerpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0registerpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0registe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rrregisterpcie_noc.router_2_1_1_p3_rperrregisterpcie_noc.router_2_1_1_p4_rperrregisterpcie_noc.router_2_1_1_p1_rperrmregisterpcie_noc.router_2_1_1_p2_rperrmregisterpcie_noc.router_2_1_1_p3_rperrmregisterpcie_noc.router_2_1_1_p4_rperrmregisterpcie_noc.router_2_3_3_reregisterpcie_noc.router_2_3_3_remregisterpcie_noc.router_2_3_3_idregisterpcie_noc.router_2_3_3_rcgoregisterpcie_noc.router_2_3_3_p2_rperrregisterpcie_noc.router_2_3_3_p3_rperrregisterpcie_noc.router_2_3_3_p4_rperrregisterpcie_noc.router_2_3_3_p2_rperrmregisterpcie_noc.router_2_3_3_p3_rperrmregisterpcie_noc.router_2_3_3_p4_rperrmregisterpcie_noc.router_2_5_5_reregisterpcie_noc.router_2_5_5_remregisterpcie_noc.router_2_5_5_idregisterpcie_noc.router_2_5_5_rcgoregisterpcie_noc.router_2_5_5_p0_rperrregisterpcie_noc.router_2_5_5_p1_rperrregisterpcie_noc.router_2_5_5_p4_rperrregisterpcie_noc.router_2_5_5_p0_rperrmregisterpcie_noc.router_2_5_5_p1_rperrmregisterpcie_noc.router_2_5_5_p4_rperrmregisterpcie_noc.router_2_7_7_reregisterpcie_noc.router_2_7_7_remregisterpcie_noc.router_2_7_7_idregisterpcie_noc.router_2_7_7_rcgoregisterpcie_noc.router_2_7_7_p0_rperrregisterpcie_noc.router_2_7_7_p3_rperrregisterpcie_noc.router_2_7_7_p4_rperrregisterpcie_noc.router_2_7_7_p0_rperrmregisterpcie_noc.router_2_7_7_p3_rperrmregisterpcie_noc.router_2_7_7_p4_rperrm0x00x7FFFFpcie_nocpcie_noc0x00x2FFF0x30000x3000pcie_noc.bridge_rbm_m_13_1_p_0pcie_noc.bridge_rbm_m_13_1_p_00x30040x30070x30080x3008pcie_noc.bridge_rbm_m_13_1_p_1pcie_noc.bridge_rbm_m_13_1_p_10x300C0x300F0x30100x3010pcie_noc.bridge_rbm_m_13_1_p_2pcie_noc.bridge_rbm_m_13_1_p_20x30140x30170x30180x3018pcie_noc.bridge_rbm_m_13_1_p_3pcie_noc.bridge_rbm_m_13_1_p_30x301C0x303F0x30400x3040pcie_noc.bridge_rbm_m_13_1_txepcie_noc.bridge_rbm_m_13_1_txe0x30440x30470x30480x3048pcie_noc.bridge_rbm_m_13_1_txempcie_noc.bridge_rbm_m_13_1_txem0x304C0x30570x30580x3058pcie_noc.bridge_rbm_m_13_1_btus_0pcie_noc.bridge_rbm_m_13_1_btus_00x305C0x305F0x30600x3060pcie_noc.bridge_rbm_m_13_1_btus_1pcie_noc.bridge_rbm_m_13_1_btus_10x30640x307F0x30800x3080pcie_noc.bridge_rbm_m_13_1_btrl_0pcie_noc.bridge_rbm_m_13_1_btrl_00x30840x30870x30880x3088pcie_noc.bridge_rbm_m_13_1_btrl_1pcie_noc.bridge_rbm_m_13_1_btrl_10x308C0x308F0x30900x3090pcie_noc.bridge_rbm_m_13_1_btrl_2pcie_noc.bridge_rbm_m_13_1_btrl_20x30940x30970x30980x3098pcie_noc.bridge_rbm_m_13_1_btrl_3pcie_noc.bridge_rbm_m_13_1_btrl_30x309C0x30A70x30A80x30A8pcie_noc.bridge_rbm_m_13_1_btperrpcie_noc.bridge_rbm_m_13_1_btperr0x30AC0x30AF0x30B00x30B0pcie_noc.bridge_rbm_m_13_1_btperrmpcie_noc.bridge_rbm_m_13_1_btperrm0x30B40x311F0x31200x3120pcie_noc.bridge_rbm_m_13_1_rxepcie_noc.bridge_rbm_m_13_1_rxe0x31240x31270x31280x3128pcie_noc.bridge_rbm_m_13_1_rxempcie_noc.bridge_rbm_m_13_1_rxem0x312C0x312F0x31300x3130pcie_noc.bridge_rbm_m_13_1_brs_0pcie_noc.bridge_rbm_m_13_1_brs_00x31340x31370x31380x3138pcie_noc.bridge_rbm_m_13_1_brs_1pcie_noc.bridge_rbm_m_13_1_brs_10x313C0x31AF0x31B00x31B0pcie_noc.bridge_rbm_m_13_1_bruspcie_noc.bridge_rbm_m_13_1_brus0x31B40x31CF0x31D00x31D0pcie_noc.bridge_rbm_m_13_1_brperr0pcie_noc.bridge_rbm_m_13_1_brperr00x31D80x31D8pcie_noc.bridge_rbm_m_13_1_brperr1pcie_noc.bridge_rbm_m_13_1_brperr10x31E00x31E0pcie_noc.bridge_rbm_m_13_1_brperrm0pcie_noc.bridge_rbm_m_13_1_brperrm00x31E80x31E8pcie_noc.bridge_rbm_m_13_1_brperrm1pcie_noc.bridge_rbm_m_13_1_brperrm10x31F00x3BFF0x3C000x3C00pcie_noc.bridge_rbm_m_13_1_am_tocfgpcie_noc.bridge_rbm_m_13_1_am_tocfg0x3C080x3C08pcie_noc.bridge_rbm_m_13_1_am_osslvpcie_noc.bridge_rbm_m_13_1_am_osslv0x3C100x3C10pcie_noc.bridge_rbm_m_13_1_am_cgcpcie_noc.bridge_rbm_m_13_1_am_cgc0x3C180x3C18pcie_noc.bridge_rbm_m_13_1_am_cgopcie_noc.bridge_rbm_m_13_1_am_cgo0x3C200x3C20pcie_noc.bridge_rbm_m_13_1_am_cfgpcie_noc.bridge_rbm_m_13_1_am_cfg0x3C280x3CFF0x3D000x3D00pcie_noc.bridge_rbm_m_13_1_am_stspcie_noc.bridge_rbm_m_13_1_am_sts0x3D080x3D08pcie_noc.bridge_rbm_m_13_1_am_bridge_idpcie_noc.bridge_rbm_m_13_1_am_bridge_id0x3D100x3D10pcie_noc.bridge_rbm_m_13_1_am_nocver_idpcie_noc.bridge_rbm_m_13_1_am_nocver_id0x3D180x3DFF0x3E000x3E00pcie_noc.bridge_rbm_m_13_1_am_errpcie_noc.bridge_rbm_m_13_1_am_err0x3E080x3E08pcie_noc.bridge_rbm_m_13_1_am_toslvidpcie_noc.bridge_rbm_m_13_1_am_toslvid0x3E100x3E10pcie_noc.bridge_rbm_m_13_1_am_erapcie_noc.bridge_rbm_m_13_1_am_era0x3E180x3E18pcie_noc.bridge_rbm_m_13_1_am_ewapcie_noc.bridge_rbm_m_13_1_am_ewa0x3E200x3E3F0x3E400x3E40pcie_noc.bridge_rbm_m_13_1_am_intmpcie_noc.bridge_rbm_m_13_1_am_intm0x3E480x3EFF0x3F000x3F00pcie_noc.bridge_rbm_m_13_1_am_caddrpcie_noc.bridge_rbm_m_13_1_am_caddr0x3F080x3F08pcie_noc.bridge_rbm_m_13_1_am_caddrmskpcie_noc.bridge_rbm_m_13_1_am_caddrmsk0x3F100x3F10pcie_noc.bridge_rbm_m_13_1_am_ccmd0pcie_noc.bridge_rbm_m_13_1_am_ccmd00x3F180x3F18pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0pcie_noc.bridge_rbm_m_13_1_am_ccmdmsk00x3F200x3F20pcie_noc.bridge_rbm_m_13_1_am_cntr0pcie_noc.bridge_rbm_m_13_1_am_cntr00x3F280x3F28pcie_noc.bridge_rbm_m_13_1_am_latnum0pcie_noc.bridge_rbm_m_13_1_am_latnum00x3F300x3F30pcie_noc.bridge_rbm_m_13_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0440xF0470xF0480xF048pcie_noc.bridge_main0_esr_m_1_5_txempcie_noc.bridge_main0_esr_m_1_5_txem0xF04C0xF0570xF0580xF058pcie_noc.bridge_main0_esr_m_1_5_btus_0pcie_noc.bridge_main0_esr_m_1_5_btus_00xF05C0xF05F0xF0600xF060pcie_noc.bridge_main0_esr_m_1_5_btus_1pcie_noc.bridge_main0_esr_m_1_5_btus_10xF0640xF07F0xF0800xF080pcie_noc.bridge_main0_esr_m_1_5_btrl_0pcie_noc.bridge_main0_esr_m_1_5_btrl_00xF0840xF0870xF0880xF088pcie_noc.bridge_main0_esr_m_1_5_btrl_1pcie_noc.bridge_main0_esr_m_1_5_btrl_10xF08C0xF08F0xF0900xF090pcie_noc.bridge_main0_esr_m_1_5_btrl_2pcie_noc.bridge_main0_esr_m_1_5_btrl_20xF0940xF0970xF0980xF098pcie_noc.bridge_main0_esr_m_1_5_btrl_3pcie_noc.bridge_main0_esr_m_1_5_btrl_30xF09C0xF0A70xF0A80xF0A8pcie_noc.bridge_main0_esr_m_1_5_btperrpcie_noc.bridge_main0_esr_m_1_5_btperr0xF0AC0xF0AF0xF0B00xF0B0pcie_noc.bridge_main0_esr_m_1_5_btperrmpcie_noc.bridge_main0_esr_m_1_5_btperrm0xF0B40xF11F0xF1200xF120pcie_noc.bridge_main0_esr_m_1_5_rxepcie_noc.bridge_main0_esr_m_1_5_rxe0xF1240xF1270xF1280xF128pcie_noc.bridge_main0_esr_m_1_5_rxempcie_noc.bridge_main0_esr_m_1_5_rxem0xF12C0xF12F0xF1300xF130pcie_noc.bridge_main0_esr_m_1_5_brs_0pcie_noc.bridge_main0_esr_m_1_5_brs_00xF1340xF1370xF1380xF138pcie_noc.bridge_main0_esr_m_1_5_brs_1pcie_noc.bridge_main0_esr_m_1_5_brs_10xF13C0xF1AF0xF1B00xF1B0pcie_noc.bridge_main0_esr_m_1_5_bruspcie_noc.bridge_main0_esr_m_1_5_brus0xF1B40xF1CF0xF1D00xF1D0pcie_noc.bridge_main0_esr_m_1_5_brperr0pcie_noc.bridge_main0_esr_m_1_5_brperr00xF1D80xF1D8pcie_noc.bridge_main0_esr_m_1_5_brperr1pcie_noc.bridge_main0_esr_m_1_5_brperr10xF1E00xF1E0pcie_noc.bridge_main0_esr_m_1_5_brperrm0pcie_noc.bridge_main0_esr_m_1_5_brperrm00xF1E80xF1E8pcie_noc.bridge_main0_esr_m_1_5_brperrm1pcie_noc.bridge_main0_esr_m_1_5_brperrm10xF1F00xFBFF0xFC000xFC00pcie_noc.bridge_main0_esr_m_1_5_am_tocfgpcie_noc.bridge_main0_esr_m_1_5_am_tocfg0xFC080xFC08pcie_noc.bridge_main0_esr_m_1_5_am_osslvpcie_noc.bridge_main0_esr_m_1_5_am_osslv0xFC100xFC10pcie_noc.bridge_main0_esr_m_1_5_am_cgcpcie_noc.bridge_main0_esr_m_1_5_am_cgc0xFC180xFC18pcie_noc.bridge_main0_esr_m_1_5_am_cgopcie_noc.bridge_main0_esr_m_1_5_am_cgo0xFC200xFC20pcie_noc.bridge_main0_esr_m_1_5_am_cfgpcie_noc.bridge_main0_esr_m_1_5_am_cfg0xFC280xFCFF0xFD000xFD00pcie_noc.bridge_main0_esr_m_1_5_am_stspcie_noc.bridge_main0_esr_m_1_5_am_sts0xFD080xFD08pcie_noc.bridge_main0_esr_m_1_5_am_bridge_idpcie_noc.bridge_main0_esr_m_1_5_am_bridge_id0xFD100xFDFF0xFE000xFE00pcie_noc.bridge_main0_esr_m_1_5_am_errpcie_noc.bridge_main0_esr_m_1_5_am_err0xFE080xFE08pcie_noc.bridge_main0_esr_m_1_5_am_toslvidpcie_noc.bridge_main0_esr_m_1_5_am_toslvid0xFE100xFE10pcie_noc.bridge_main0_esr_m_1_5_am_erapcie_noc.bridge_main0_esr_m_1_5_am_era0xFE180xFE18pcie_noc.bridge_main0_esr_m_1_5_am_ewapcie_noc.bridge_main0_esr_m_1_5_am_ewa0xFE200xFE3F0xFE400xFE40pcie_noc.bridge_main0_esr_m_1_5_am_intmpcie_noc.bridge_main0_esr_m_1_5_am_intm0xFE480xFEFF0xFF000xFF00pcie_noc.bridge_main0_esr_m_1_5_am_caddrpcie_noc.bridge_main0_esr_m_1_5_am_caddr0xFF080xFF08pcie_noc.bridge_main0_esr_m_1_5_am_caddrmskpcie_noc.bridge_main0_esr_m_1_5_am_caddrmsk0xFF100xFF10pcie_noc.bridge_main0_esr_m_1_5_am_ccmd0pcie_noc.bridge_main0_esr_m_1_5_am_ccmd00xFF180xFF18pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk0pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk00xFF200xFF20pcie_noc.bridge_main0_esr_m_1_5_am_cntr0pcie_noc.bridge_main0_esr_m_1_5_am_cntr00xFF280xFF28pcie_noc.bridge_main0_esr_m_1_5_am_latnum0pcie_noc.bridge_main0_esr_m_1_5_am_latnum00xFF300xFF30pcie_noc.bridge_main0_esr_m_1_5_am_ccmd1pcie_noc.bridge_main0_esr_m_1_5_am_ccmd10xFF380xFF38pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk1pcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk10xFF400xFF40pcie_noc.bridge_main0_esr_m_1_5_am_cntr1pcie_noc.bridge_main0_esr_m_1_5_am_cntr10xFF480xFF48pcie_noc.bridge_main0_esr_m_1_5_am_latnum1pcie_noc.bridge_main0_esr_m_1_5_am_latnum10xFF500xFF5F0xFF600xFF60pcie_noc.bridge_main0_esr_m_1_5_am_arovrdpcie_noc.bridge_main0_esr_m_1_5_am_arovrd0xFF680xFF68pcie_noc.bridge_main0_esr_m_1_5_am_awovrdpcie_noc.bridge_main0_esr_m_1_5_am_awovrd0xFF700xFFFF0x100000x10000pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x100080x10008pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x100100x1001F0x100200x10020pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0pcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x100280x10028pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0pcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x100300x10030pcie_noc.bridge_main0_mesh_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1F0A8pcie_noc.bridge_p0_p0_m_3_6_btperrpcie_noc.bridge_p0_p0_m_3_6_btperr0x1F0AC0x1F0AF0x1F0B00x1F0B0pcie_noc.bridge_p0_p0_m_3_6_btperrmpcie_noc.bridge_p0_p0_m_3_6_btperrm0x1F0B40x1F11F0x1F1200x1F120pcie_noc.bridge_p0_p0_m_3_6_rxepcie_noc.bridge_p0_p0_m_3_6_rxe0x1F1240x1F1270x1F1280x1F128pcie_noc.bridge_p0_p0_m_3_6_rxempcie_noc.bridge_p0_p0_m_3_6_rxem0x1F12C0x1F12F0x1F1300x1F130pcie_noc.bridge_p0_p0_m_3_6_brs_0pcie_noc.bridge_p0_p0_m_3_6_brs_00x1F1340x1F1370x1F1380x1F138pcie_noc.bridge_p0_p0_m_3_6_brs_1pcie_noc.bridge_p0_p0_m_3_6_brs_10x1F13C0x1F1AF0x1F1B00x1F1B0pcie_noc.bridge_p0_p0_m_3_6_bruspcie_noc.bridge_p0_p0_m_3_6_brus0x1F1B40x1F1CF0x1F1D00x1F1D0pcie_noc.bridge_p0_p0_m_3_6_brperr0pcie_noc.bridge_p0_p0_m_3_6_brperr00x1F1D80x1F1D8pcie_noc.bridge_p0_p0_m_3_6_brperr1pcie_noc.bridge_p0_p0_m_3_6_brperr10x1F1E00x1F1E0pcie_noc.bridge_p0_p0_m_3_6_brperrm0pcie_noc.bridge_p0_p0_m_3_6_brperrm00x1F1E80x1F1E8pcie_noc.bridge_p0_p0_m_3_6_brperrm1pcie_noc.bridge_p0_p0_m_3_6_brperrm10x1F1F00x1FBFF0x1FC000x1FC00pcie_noc.bridge_p0_p0_m_3_6_am_tocfgpcie_noc.bridge_p0_p0_m_3_6_am_tocfg0x1FC080x1FC08pcie_noc.bridge_p0_p0_m_3_6_am_osslvpcie_noc.bridge_p0_p0_m_3_6_am_osslv0x1FC100x1FC10pcie_noc.bridge_p0_p0_m_3_6_am_cgcpcie_noc.bridge_p0_p0_m_3_6_am_cgc0x1FC180x1FC18pcie_noc.bridge_p0_p0_m_3_6_am_cgopcie_noc.bridge_p0_p0_m_3_6_am_cgo0x1FC200x1FC20pcie_noc.bridge_p0_p0_m_3_6_am_cfgpcie_noc.bridge_p0_p0_m_3_6_am_cfg0x1FC280x1FCFF0x1FD000x1FD00pcie_noc.bridge_p0_p0_m_3_6_am_stspcie_noc.bridge_p0_p0_m_3_6_am_sts0x1FD080x1FD08pcie_noc.bridge_p0_p0_m_3_6_am_bridge_idpcie_noc.bridge_p0_p0_m_3_6_am_bridge_id0x1FD100x1FDFF0x1FE000x1FE00pcie_noc.bridge_p0_p0_m_3_6_am_errpcie_noc.bridge_p0_p0_m_3_6_am_err0x1FE080x1FE08pcie_noc.bridge_p0_p0_m_3_6_am_toslvidpcie_noc.bridge_p0_p0_m_3_6_am_toslvid0x1FE100x1FE10pcie_noc.bridge_p0_p0_m_3_6_am_erapcie_noc.bridge_p0_p0_m_3_6_am_era0x1FE180x1FE18pcie_noc.bridge_p0_p0_m_3_6_am_ewapcie_noc.bridge_p0_p0_m_3_6_am_ewa0x1FE200x1FE3F0x1FE400x1FE40pcie_noc.bridge_p0_p0_m_3_6_am_intmpcie_noc.bridge_p0_p0_m_3_6_am_intm0x1FE480x1FEFF0x1FF000x1FF00pcie_noc.bridge_p0_p0_m_3_6_am_caddrpcie_noc.bridge_p0_p0_m_3_6_am_caddr0x1FF080x1FF08pcie_noc.bridge_p0_p0_m_3_6_am_caddrmskpcie_noc.bridge_p0_p0_m_3_6_am_caddrmsk0x1FF100x1FF10pcie_noc.bridge_p0_p0_m_3_6_am_ccmd0pcie_noc.bridge_p0_p0_m_3_6_am_ccmd00x1FF180x1FF18pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk0pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk00x1FF200x1FF20pcie_noc.bridge_p0_p0_m_3_6_am_cntr0pcie_noc.bridge_p0_p0_m_3_6_am_cntr00x1FF280x1FF28pcie_noc.bridge_p0_p0_m_3_6_am_latnum0pcie_noc.bridge_p0_p0_m_3_6_am_latnum00x1FF300x1FF30pcie_noc.bridge_p0_p0_m_3_6_am_ccmd1pcie_noc.bridge_p0_p0_m_3_6_am_ccmd10x1FF380x1FF38pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk1pcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk10x1FF400x1FF40pcie_noc.bridge_p0_p0_m_3_6_am_cntr1pcie_noc.bridge_p0_p0_m_3_6_am_cntr10x1FF480x1FF48pcie_noc.bridge_p0_p0_m_3_6_am_latnum1pcie_noc.bridge_p0_p0_m_3_6_am_latnum10x1FF500x1FF5F0x1FF600x1FF60pcie_noc.bridge_p0_p0_m_3_6_am_arovrdpcie_noc.bridge_p0_p0_m_3_6_am_arovrd0x1FF680x1FF68pcie_noc.bridge_p0_p0_m_3_6_am_awovrdpcie_noc.bridge_p0_p0_m_3_6_am_awovrd0x1FF700x21C0F0x21C100x21C10pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgcpcie_noc.bridge_p0_p0_reg_s_9_6_as_cgc0x21C180x21C18pcie_noc.bridge_p0_p0_reg_s_9_6_as_cgopcie_noc.bridge_p0_p0_reg_s_9_6_as_cgo0x21C200x21CFF0x21D000x21D00pcie_noc.bridge_p0_p0_reg_s_9_6_as_stspcie_noc.bridge_p0_p0_reg_s_9_6_as_sts0x21D080x21D08pcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_idpcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_id0x21D100x21DFF0x21E000x21E00pcie_noc.bridge_p0_p0_reg_s_9_6_as_errpcie_noc.bridge_p0_p0_reg_s_9_6_as_err0x21E080x21E3F0x21E400x21E40pcie_noc.bridge_p0_p0_reg_s_9_6_as_intmpcie_noc.bridge_p0_p0_reg_s_9_6_as_intm0x21E480x21EFF0x21F000x21F00pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdpcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmd0x21F080x21F08pcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmskpcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmsk0x21F100x21F10pcie_noc.bridge_p0_p0_reg_s_9_6_as_cntrpcie_noc.bridge_p0_p0_reg_s_9_6_as_cntr0x21F180x21F18pcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrdpcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrd0x21F200x21F20pcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrdpcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrd0x21F280x22FFF0x230000x23000pcie_noc.bridge_p0_p0_reg_s_9_6_p_0pcie_noc.bridge_p0_p0_reg_s_9_6_p_00x230040x230070x230080x23008pcie_noc.bridge_p0_p0_reg_s_9_6_p_1pcie_noc.bridge_p0_p0_reg_s_9_6_p_10x2300C0x2300F0x230100x23010pcie_noc.bridge_p0_p0_reg_s_9_6_p_2pcie_noc.bridge_p0_p0_reg_s_9_6_p_20x230140x230170x230180x23018pcie_noc.bridge_p0_p0_reg_s_9_6_p_3pcie_noc.bridge_p0_p0_reg_s_9_6_p_30x2301C0x2303F0x230400x23040pcie_noc.bridge_p0_p0_reg_s_9_6_txepcie_noc.bridge_p0_p0_reg_s_9_6_txe0x230440x230470x230480x23048pcie_noc.bridge_p0_p0_reg_s_9_6_txempcie_noc.bridge_p0_p0_reg_s_9_6_txem0x2304C0x230570x230580x23058pcie_noc.bridge_p0_p0_reg_s_9_6_btus_0pcie_noc.bridge_p0_p0_reg_s_9_6_btus_00x2305C0x2305F0x230600x23060pcie_noc.bridge_p0_p0_reg_s_9_6_b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BE000x2BE00pcie_noc.bridge_p0_p1_m_4_6_am_errpcie_noc.bridge_p0_p1_m_4_6_am_err0x2BE080x2BE08pcie_noc.bridge_p0_p1_m_4_6_am_toslvidpcie_noc.bridge_p0_p1_m_4_6_am_toslvid0x2BE100x2BE10pcie_noc.bridge_p0_p1_m_4_6_am_erapcie_noc.bridge_p0_p1_m_4_6_am_era0x2BE180x2BE18pcie_noc.bridge_p0_p1_m_4_6_am_ewapcie_noc.bridge_p0_p1_m_4_6_am_ewa0x2BE200x2BE3F0x2BE400x2BE40pcie_noc.bridge_p0_p1_m_4_6_am_intmpcie_noc.bridge_p0_p1_m_4_6_am_intm0x2BE480x2BEFF0x2BF000x2BF00pcie_noc.bridge_p0_p1_m_4_6_am_caddrpcie_noc.bridge_p0_p1_m_4_6_am_caddr0x2BF080x2BF08pcie_noc.bridge_p0_p1_m_4_6_am_caddrmskpcie_noc.bridge_p0_p1_m_4_6_am_caddrmsk0x2BF100x2BF10pcie_noc.bridge_p0_p1_m_4_6_am_ccmd0pcie_noc.bridge_p0_p1_m_4_6_am_ccmd00x2BF180x2BF18pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk0pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk00x2BF200x2BF20pcie_noc.bridge_p0_p1_m_4_6_am_cntr0pcie_noc.bridge_p0_p1_m_4_6_am_cntr00x2BF280x2BF28pcie_noc.bridge_p0_p1_m_4_6_am_latnum0pcie_noc.bridge_p0_p1_m_4_6_am_latnum00x2BF300x2BF30pcie_noc.bridge_p0_p1_m_4_6_am_ccmd1pcie_noc.bridge_p0_p1_m_4_6_am_ccmd10x2BF380x2BF38pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk1pcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk10x2BF400x2BF40pcie_noc.bridge_p0_p1_m_4_6_am_cntr1pcie_noc.bridge_p0_p1_m_4_6_am_cntr10x2BF480x2BF48pcie_noc.bridge_p0_p1_m_4_6_am_latnum1pcie_noc.bridge_p0_p1_m_4_6_am_latnum10x2BF500x2BF5F0x2BF600x2BF60pcie_noc.bridge_p0_p1_m_4_6_am_arovrdpcie_noc.bridge_p0_p1_m_4_6_am_arovrd0x2BF680x2BF68pcie_noc.bridge_p0_p1_m_4_6_am_awovrdpcie_noc.bridge_p0_p1_m_4_6_am_awovrd0x2BF700x2DC0F0x2DC100x2DC10pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgcpcie_noc.bridge_p0_p1_reg_s_11_6_as_cgc0x2DC180x2DC18pcie_noc.bridge_p0_p1_reg_s_11_6_as_cgopcie_noc.bridge_p0_p1_reg_s_11_6_as_cgo0x2DC200x2DCFF0x2DD000x2DD00pcie_noc.bridge_p0_p1_reg_s_11_6_as_stspcie_noc.bridge_p0_p1_reg_s_11_6_as_sts0x2DD080x2DD08pcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_idpcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_id0x2DD100x2DDFF0x2DE000x2DE00pcie_noc.bridge_p0_p1_reg_s_11_6_as_errpcie_noc.bridge_p0_p1_reg_s_11_6_as_err0x2DE080x2DE3F0x2DE400x2DE40pcie_noc.bridge_p0_p1_reg_s_11_6_as_intmpcie_noc.bridge_p0_p1_reg_s_11_6_as_intm0x2DE480x2DEFF0x2DF000x2DF00pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdpcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmd0x2DF080x2DF08pcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmskpcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmsk0x2DF100x2DF10pcie_noc.bridge_p0_p1_reg_s_11_6_as_cntrpcie_noc.bridge_p0_p1_reg_s_11_6_as_cntr0x2DF180x2DF18pcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrdpcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrd0x2DF200x2DF20pcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrdpcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrd0x2DF280x2EFFF0x2F0000x2F000pcie_noc.bridge_p0_p1_reg_s_11_6_p_0pcie_noc.bridge_p0_p1_reg_s_11_6_p_00x2F0040x2F0070x2F0080x2F008pcie_noc.bridge_p0_p1_reg_s_11_6_p_1pcie_noc.bridge_p0_p1_reg_s_11_6_p_10x2F00C0x2F00F0x2F0100x2F010pcie_noc.bridge_p0_p1_reg_s_11_6_p_2pcie_noc.bridge_p0_p1_reg_s_11_6_p_20x2F0140x2F0170x2F0180x2F018pcie_noc.bridge_p0_p1_reg_s_11_6_p_3pcie_noc.bridge_p0_p1_reg_s_11_6_p_30x2F01C0x2F03F0x2F0400x2F040pcie_noc.bridge_p0_p1_reg_s_11_6_txepcie_noc.bridge_p0_p1_reg_s_11_6_txe0x2F0440x2F0470x2F0480x2F048pcie_noc.bridge_p0_p1_reg_s_11_6_txempcie_noc.bridge_p0_p1_reg_s_11_6_txem0x2F04C0x2F0570x2F0580x2F058pcie_noc.bridge_p0_p1_reg_s_11_6_btus_0pcie_noc.bridge_p0_p1_reg_s_11_6_btus_00x2F05C0x2F05F0x2F0600x2F060pcie_noc.bridge_p0_p1_reg_s_11_6_btus_1pcie_noc.bridge_p0_p1_reg_s_11_6_btus_10x2F0640x2F07F0x2F0800x2F080pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_0pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_00x2F0840x2F0870x2F0880x2F088pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_1pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_10x2F08C0x2F08F0x2F0900x2F090pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_2pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_20x2F0940x2F0970x2F0980x2F098pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_3pcie_noc.bridge_p0_p1_reg_s_11_6_btrl_30x2F09C0x2F0A70x2F0A80x2F0A8pcie_noc.bridge_p0_p1_reg_s_11_6_btperrpcie_noc.bridge_p0_p1_reg_s_11_6_btperr0x2F0AC0x2F0AF0x2F0B00x2F0B0pcie_noc.bridge_p0_p1_reg_s_11_6_btperrmpcie_noc.bridge_p0_p1_reg_s_11_6_btperrm0x2F0B40x2F11F0x2F1200x2F120pcie_noc.bridge_p0_p1_reg_s_11_6_rxepcie_noc.bridge_p0_p1_reg_s_11_6_rxe0x2F1240x2F1270x2F1280x2F128pcie_noc.bridge_p0_p1_reg_s_11_6_rxempcie_noc.bridge_p0_p1_reg_s_11_6_rxem0x2F12C0x2F12F0x2F1300x2F130pcie_noc.bridge_p0_p1_reg_s_11_6_brs_0pcie_noc.bridge_p0_p1_reg_s_11_6_brs_00x2F1340x2F1370x2F1380x2F138pcie_noc.bridge_p0_p1_reg_s_11_6_brs_1pcie_noc.bridge_p0_p1_reg_s_11_6_brs_10x2F13C0x2F1AF0x2F1B00x2F1B0pcie_noc.bridge_p0_p1_reg_s_11_6_bruspcie_noc.bridge_p0_p1_reg_s_11_6_brus0x2F1B40x2F1CF0x2F1D00x2F1D0pcie_noc.bridge_p0_p1_reg_s_11_6_brperr0pcie_noc.bridge_p0_p1_reg_s_11_6_brperr00x2F1D80x2F1D8pcie_noc.bridge_p0_p1_reg_s_11_6_brperr1pcie_noc.bridge_p0_p1_reg_s_11_6_brperr10x2F1E00x2F1E0pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm0pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm00x2F1E80x2F1E8pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm1pcie_noc.bridge_p0_p1_reg_s_11_6_brperrm10x2F1F00x31C0F0x31C100x31C10pcie_noc.bridge_p0_p1_s_12_10_as_cgcpcie_noc.bridge_p0_p1_s_12_10_as_cgc0x31C180x31C18pcie_noc.bridge_p0_p1_s_12_10_as_cgopcie_noc.bridge_p0_p1_s_12_10_as_cgo0x31C200x31CFF0x31D000x31D00pcie_noc.bridge_p0_p1_s_12_10_as_stspcie_noc.bridge_p0_p1_s_12_10_as_sts0x31D080x31D08pcie_noc.bridge_p0_p1_s_12_10_as_bridge_idpcie_noc.bridge_p0_p1_s_12_10_as_bridge_id0x31D100x31DFF0x31E000x31E00pcie_noc.bridge_p0_p1_s_12_10_as_errpcie_noc.bridge_p0_p1_s_12_10_as_err0x31E080x31E3F0x31E400x31E40pcie_noc.bridge_p0_p1_s_12_10_as_intmpcie_noc.bridge_p0_p1_s_12_10_as_intm0x31E480x31EFF0x31F000x31F00pcie_noc.bridge_p0_p1_s_12_10_as_ccmdpcie_noc.bridge_p0_p1_s_12_10_as_ccmd0x31F080x31F08pcie_noc.bridge_p0_p1_s_12_10_as_ccmdmskpcie_noc.bridge_p0_p1_s_12_10_as_ccmdmsk0x31F100x31F10pcie_noc.bridge_p0_p1_s_12_10_as_cntrpcie_noc.bridge_p0_p1_s_12_10_as_cntr0x31F180x31F18pcie_noc.bridge_p0_p1_s_12_10_as_arovrdpcie_noc.bridge_p0_p1_s_12_10_as_arovrd0x31F200x31F20pcie_noc.bridge_p0_p1_s_12_10_as_awovrdpcie_noc.bridge_p0_p1_s_12_10_as_awovrd0x31F280x32FFF0x330000x33000pcie_noc.bridge_p0_p1_s_12_10_p_0pcie_noc.bridge_p0_p1_s_12_10_p_00x330040x330070x330080x33008pcie_noc.bridge_p0_p1_s_12_10_p_1pcie_noc.bridge_p0_p1_s_12_10_p_10x3300C0x3300F0x330100x33010pcie_noc.bridge_p0_p1_s_12_10_p_2pcie_noc.bridge_p0_p1_s_12_10_p_20x330140x330170x330180x33018pcie_noc.bridge_p0_p1_s_12_10_p_3pcie_noc.bridge_p0_p1_s_12_10_p_30x3301C0x3303F0x330400x33040pcie_noc.bridge_p0_p1_s_12_10_txepcie_noc.bridge_p0_p1_s_12_10_txe0x330440x330470x330480x33048pcie_noc.bridge_p0_p1_s_12_10_txempcie_noc.bridge_p0_p1_s_12_10_txem0x3304C0x330570x330580x33058pcie_noc.bridge_p0_p1_s_12_10_btus_0pcie_noc.bridge_p0_p1_s_12_10_btus_00x3305C0x3305F0x330600x33060pcie_noc.bridge_p0_p1_s_12_10_btus_1pcie_noc.bridge_p0_p1_s_12_10_btus_10x330640x3307F0x330800x33080pcie_noc.bridge_p0_p1_s_12_10_btrl_0pcie_noc.bridge_p0_p1_s_12_10_btrl_00x330840x330870x330880x33088pcie_noc.bridge_p0_p1_s_12_10_btrl_1pcie_noc.bridge_p0_p1_s_12_10_btrl_10x3308C0x3308F0x330900x33090pcie_noc.bridge_p0_p1_s_12_10_btrl_2pcie_noc.bridge_p0_p1_s_12_10_btrl_20x330940x330970x330980x33098pcie_noc.bridge_p0_p1_s_12_10_btrl_3pcie_noc.bridge_p0_p1_s_12_10_btrl_30x3309C0x330A70x330A80x330A8pcie_noc.bridge_p0_p1_s_12_10_btperrpcie_noc.bridge_p0_p1_s_12_10_btperr0x330AC0x330AF0x330B00x330B0pcie_noc.bridge_p0_p1_s_12_10_btperrmpcie_noc.bridge_p0_p1_s_12_10_btperrm0x330B40x3311F0x331200x33120pcie_noc.bridge_p0_p1_s_12_10_rxepcie_noc.bridge_p0_p1_s_12_10_rxe0x331240x331270x331280x33128pcie_noc.bridge_p0_p1_s_12_10_rxempcie_noc.bridge_p0_p1_s_12_10_rxem0x3312C0x3312F0x331300x33130pcie_noc.bridge_p0_p1_s_12_10_brs_0pcie_noc.bridge_p0_p1_s_12_10_brs_00x331340x331370x331380x33138pcie_noc.bridge_p0_p1_s_12_10_brs_1pcie_noc.bridge_p0_p1_s_12_10_brs_10x3313C0x331AF0x331B00x331B0pcie_noc.bridge_p0_p1_s_12_10_bruspcie_noc.bridge_p0_p1_s_12_10_brus0x331B40x331CF0x331D00x331D0pcie_noc.bridge_p0_p1_s_12_10_brperr0pcie_noc.bridge_p0_p1_s_12_10_brperr00x331D80x331D8pcie_noc.bridge_p0_p1_s_12_10_brperr1pcie_noc.bridge_p0_p1_s_12_10_brperr10x331E00x331E0pcie_noc.bridge_p0_p1_s_12_10_brperrm0pcie_noc.bridge_p0_p1_s_12_10_brperrm00x331E80x331E8pcie_noc.bridge_p0_p1_s_12_10_brperrm1pcie_noc.bridge_p0_p1_s_12_10_brperrm10x331F00x33FFF0x340000x34000pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x340080x34008pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x340100x3401F0x340200x34020pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_00x340280x34028pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_00x340300x3403F0x340400x34040pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_00x340480x34048pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_00x340500x3405F0x340600x34060pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0pcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x340680x34068pcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0pcie_noc.bridge_p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_p1_rperrmpcie_noc.router_0_6_6_p1_rperrm0x3C1040x3C1070x3C1080x3C108pcie_noc.router_0_6_6_p2_rperrmpcie_noc.router_0_6_6_p2_rperrm0x3C10C0x3C10F0x3C1100x3C110pcie_noc.router_0_6_6_p3_rperrmpcie_noc.router_0_6_6_p3_rperrm0x3C1140x3C1170x3C1180x3C118pcie_noc.router_0_6_6_p4_rperrmpcie_noc.router_0_6_6_p4_rperrm0x3C11C0x3C11F0x3C1200x3C120pcie_noc.router_0_6_6_p5_rperrmpcie_noc.router_0_6_6_p5_rperrm0x3C1240x3C1270x3C1280x3C128pcie_noc.router_0_6_6_p6_rperrmpcie_noc.router_0_6_6_p6_rperrm0x3C12C0x3C12F0x3C1300x3C130pcie_noc.router_0_6_6_p7_rperrmpcie_noc.router_0_6_6_p7_rperrm0x3C1340x3C1370x3C1380x3C138pcie_noc.router_0_6_6_roeccpcie_noc.router_0_6_6_roecc0x3C13C0x3C13F0x3C1400x3C140pcie_noc.router_0_6_6_roecpcie_noc.router_0_6_6_roec0x3C1440x3FFFF0x400000x40000pcie_noc.router_1_5_5_rivcs_hpcie_noc.router_1_5_5_rivcs_h0x400040x400070x400080x40008pcie_noc.router_1_5_5_rivcs_epcie_noc.router_1_5_5_rivcs_e0x4000C0x4000F0x400100x40010pcie_noc.router_1_5_5_rivcs_spcie_noc.router_1_5_5_rivcs_s0x400140x400170x400180x40018pcie_noc.router_1_5_5_rivcs_wpcie_noc.router_1_5_5_rivcs_w0x4001C0x400270x400280x40028pcie_noc.router_1_5_5_rivcs_ipcie_noc.router_1_5_5_rivcs_i0x4002C0x4002F0x400300x40030pcie_noc.router_1_5_5_rivcs_jpcie_noc.router_1_5_5_rivcs_j0x400340x400370x400380x40038pcie_noc.router_1_5_5_rivcs_kpcie_noc.router_1_5_5_rivcs_k0x4003C0x4003F0x400400x40040pcie_noc.router_1_5_5_rovcs_hpcie_noc.router_1_5_5_rovcs_h0x400440x400470x400480x40048pcie_noc.router_1_5_5_rovcs_epcie_noc.router_1_5_5_rovcs_e0x4004C0x4004F0x400500x40050pcie_noc.router_1_5_5_rovcs_spcie_noc.router_1_5_5_rovcs_s0x400540x400570x400580x40058pcie_noc.router_1_5_5_rovcs_wpcie_noc.router_1_5_5_rovcs_w0x4005C0x400670x400680x40068pcie_noc.router_1_5_5_rovcs_ipcie_noc.router_1_5_5_rovcs_i0x4006C0x4006F0x400700x40070pcie_noc.router_1_5_5_rovcs_jpcie_noc.router_1_5_5_rovcs_j0x400740x400770x400780x40078pcie_noc.router_1_5_5_rovcs_kpcie_noc.router_1_5_5_rovcs_k0x4007C0x4007F0x400800x40080pcie_noc.router_1_5_5_repcie_noc.router_1_5_5_re0x400840x400870x400880x40088pcie_noc.router_1_5_5_rempcie_noc.router_1_5_5_rem0x4008C0x4008F0x400900x40090pcie_noc.router_1_5_5_reccpcie_noc.router_1_5_5_recc0x400940x400970x400980x40098pcie_noc.router_1_5_5_recpcie_noc.router_1_5_5_rec0x4009C0x4009F0x400A00x400A0pcie_noc.router_1_5_5_idpcie_noc.router_1_5_5_id0x400A40x400A70x400A80x400A8pcie_noc.router_1_5_5_rcgcpcie_noc.router_1_5_5_rcgc0x400AC0x400AF0x400B00x400B0pcie_noc.router_1_5_5_rcgopcie_noc.router_1_5_5_rcgo0x400B40x400BF0x400C00x400C0pcie_noc.router_1_5_5_p1_rperrpcie_noc.router_1_5_5_p1_rperr0x400C40x400C70x400C80x400C8pcie_noc.router_1_5_5_p2_rperrpcie_noc.router_1_5_5_p2_rperr0x400CC0x400CF0x400D00x400D0pcie_noc.router_1_5_5_p3_rperrpcie_noc.router_1_5_5_p3_rperr0x400D40x400D70x400D80x400D8pcie_noc.router_1_5_5_p4_rperrpcie_noc.router_1_5_5_p4_rperr0x400DC0x400DF0x400E00x400E0pcie_noc.router_1_5_5_p5_rperrpcie_noc.router_1_5_5_p5_rperr0x400E40x400E70x400E80x400E8pcie_noc.router_1_5_5_p6_rperrpcie_noc.router_1_5_5_p6_rperr0x400EC0x400EF0x400F00x400F0pcie_noc.router_1_5_5_p7_rperrpcie_noc.router_1_5_5_p7_rperr0x400F40x400FF0x401000x40100pcie_noc.router_1_5_5_p1_rperrmpcie_noc.router_1_5_5_p1_rperrm0x401040x401070x401080x40108pcie_noc.router_1_5_5_p2_rperrmpcie_noc.router_1_5_5_p2_rperrm0x4010C0x4010F0x401100x40110pcie_noc.router_1_5_5_p3_rperrmpcie_noc.router_1_5_5_p3_rperrm0x401140x401170x401180x40118pcie_noc.router_1_5_5_p4_rperrmpcie_noc.router_1_5_5_p4_rperrm0x4011C0x4011F0x401200x40120pcie_noc.router_1_5_5_p5_rperrmpcie_noc.router_1_5_5_p5_rperrm0x401240x401270x401280x40128pcie_noc.router_1_5_5_p6_rperrmpcie_noc.router_1_5_5_p6_rperrm0x4012C0x4012F0x401300x40130pcie_noc.router_1_5_5_p7_rperrmpcie_noc.router_1_5_5_p7_rperrm0x401340x401370x401380x40138pcie_noc.router_1_5_5_roeccpcie_noc.router_1_5_5_roecc0x4013C0x4013F0x401400x40140pcie_noc.router_1_5_5_roecpcie_noc.router_1_5_5_roec0x401440x43FFF0x440000x44000pcie_noc.router_1_6_6_rivcs_hpcie_noc.router_1_6_6_rivcs_h0x440040x440070x440080x44008pcie_noc.router_1_6_6_rivcs_epcie_noc.router_1_6_6_rivcs_e0x4400C0x4400F0x440100x44010pcie_noc.router_1_6_6_rivcs_spcie_noc.router_1_6_6_rivcs_s0x440140x440170x440180x44018pcie_noc.router_1_6_6_rivcs_wpcie_noc.router_1_6_6_rivcs_w0x4401C0x4401F0x440200x44020pcie_noc.router_1_6_6_rivcs_npcie_noc.router_1_6_6_rivcs_n0x440240x440270x440280x44028pcie_noc.router_1_6_6_rivcs_ipcie_noc.router_1_6_6_rivcs_i0x4402C0x4402F0x440300x44030pcie_noc.router_1_6_6_rivcs_jpcie_noc.router_1_6_6_rivcs_j0x440340x440370x440380x44038pcie_noc.router_1_6_6_rivcs_kpcie_noc.router_1_6_6_rivcs_k0x4403C0x4403F0x440400x44040pcie_noc.router_1_6_6_rovcs_hpcie_noc.router_1_6_6_rovcs_h0x440440x440470x440480x44048pcie_noc.router_1_6_6_rovcs_epcie_noc.router_1_6_6_rovcs_e0x4404C0x4404F0x440500x44050pcie_noc.router_1_6_6_rovcs_spcie_noc.router_1_6_6_rovcs_s0x440540x440570x440580x44058pcie_noc.router_1_6_6_rovcs_wpcie_noc.router_1_6_6_rovcs_w0x4405C0x4405F0x440600x44060pcie_noc.router_1_6_6_rovcs_npcie_noc.router_1_6_6_rovcs_n0x440640x440670x440680x44068pcie_noc.router_1_6_6_rovcs_ipcie_noc.router_1_6_6_rovcs_i0x4406C0x4406F0x440700x44070pcie_noc.router_1_6_6_rovcs_jpcie_noc.router_1_6_6_rovcs_j0x440740x440770x440780x44078pcie_noc.router_1_6_6_rovcs_kpcie_noc.router_1_6_6_rovcs_k0x4407C0x4407F0x440800x44080pcie_noc.router_1_6_6_repcie_noc.router_1_6_6_re0x440840x440870x440880x44088pcie_noc.router_1_6_6_rempcie_noc.router_1_6_6_rem0x4408C0x4408F0x440900x44090pcie_noc.router_1_6_6_reccpcie_noc.router_1_6_6_recc0x440940x440970x440980x44098pcie_noc.router_1_6_6_recpcie_noc.router_1_6_6_rec0x4409C0x4409F0x440A00x440A0pcie_noc.router_1_6_6_idpcie_noc.router_1_6_6_id0x440A40x440A70x440A80x440A8pcie_noc.router_1_6_6_rcgcpcie_noc.router_1_6_6_rcgc0x440AC0x440AF0x440B00x440B0pcie_noc.router_1_6_6_rcgopcie_noc.router_1_6_6_rcgo0x440B40x440B70x440B80x440B8pcie_noc.router_1_6_6_p0_rperrpcie_noc.router_1_6_6_p0_rperr0x440BC0x440BF0x440C00x440C0pcie_noc.router_1_6_6_p1_rperrpcie_noc.router_1_6_6_p1_rperr0x440C40x440C70x440C80x440C8pcie_noc.router_1_6_6_p2_rperrpcie_noc.router_1_6_6_p2_rperr0x440CC0x440CF0x440D00x440D0pcie_noc.router_1_6_6_p3_rperrpcie_noc.router_1_6_6_p3_rperr0x440D40x440D70x440D80x440D8pcie_noc.router_1_6_6_p4_rperrpcie_noc.router_1_6_6_p4_rperr0x440DC0x440DF0x440E00x440E0pcie_noc.router_1_6_6_p5_rperrpcie_noc.router_1_6_6_p5_rperr0x440E40x440E70x440E80x440E8pcie_noc.router_1_6_6_p6_rperrpcie_noc.router_1_6_6_p6_rperr0x440EC0x440EF0x440F00x440F0pcie_noc.router_1_6_6_p7_rperrpcie_noc.router_1_6_6_p7_rperr0x440F40x440F70x440F80x440F8pcie_noc.router_1_6_6_p0_rperrmpcie_noc.router_1_6_6_p0_rperrm0x440FC0x440FF0x441000x44100pcie_noc.router_1_6_6_p1_rperrmpcie_noc.router_1_6_6_p1_rperrm0x441040x441070x441080x44108pcie_noc.router_1_6_6_p2_rperrmpcie_noc.router_1_6_6_p2_rperrm0x4410C0x4410F0x441100x44110pcie_noc.router_1_6_6_p3_rperrmpcie_noc.router_1_6_6_p3_rperrm0x441140x441170x441180x44118pcie_noc.router_1_6_6_p4_rperrmpcie_noc.router_1_6_6_p4_rperrm0x4411C0x4411F0x441200x44120pcie_noc.router_1_6_6_p5_rperrmpcie_noc.router_1_6_6_p5_rperrm0x441240x441270x441280x44128pcie_noc.router_1_6_6_p6_rperrmpcie_noc.router_1_6_6_p6_rperrm0x4412C0x4412F0x441300x44130pcie_noc.router_1_6_6_p7_rperrmpcie_noc.router_1_6_6_p7_rperrm0x441340x441370x441380x44138pcie_noc.router_1_6_6_roeccpcie_noc.router_1_6_6_roecc0x4413C0x4413F0x441400x44140pcie_noc.router_1_6_6_roecpcie_noc.router_1_6_6_roec0x441440x4807F0x480800x48080pcie_noc.router_2_1_1_repcie_noc.router_2_1_1_re0x480840x480870x480880x48088pcie_noc.router_2_1_1_rempcie_noc.router_2_1_1_rem0x4808C0x4809F0x480A00x480A0pcie_noc.router_2_1_1_idpcie_noc.router_2_1_1_id0x480A40x480AF0x480B00x480B0pcie_noc.router_2_1_1_rcgopcie_noc.router_2_1_1_rcgo0x480B40x480BF0x480C00x480C0pcie_noc.router_2_1_1_p1_rperrpcie_noc.router_2_1_1_p1_rperr0x480C40x480C70x480C80x480C8pcie_noc.router_2_1_1_p2_rperrpcie_noc.router_2_1_1_p2_rperr0x480CC0x480CF0x480D00x480D0pcie_noc.router_2_1_1_p3_rperrpcie_noc.router_2_1_1_p3_rperr0x480D40x480D70x480D80x480D8pcie_noc.router_2_1_1_p4_rperrpcie_noc.router_2_1_1_p4_rperr0x480DC0x480FF0x481000x48100pcie_noc.router_2_1_1_p1_rperrmpcie_noc.router_2_1_1_p1_rperrm0x481040x481070x481080x48108pcie_noc.router_2_1_1_p2_rperrmpcie_noc.router_2_1_1_p2_rperrm0x4810C0x4810F0x481100x48110pcie_noc.router_2_1_1_p3_rperrmpcie_noc.router_2_1_1_p3_rperrm0x481140x481170x481180x48118pcie_noc.router_2_1_1_p4_rperrmpcie_noc.router_2_1_1_p4_rperrm0x4811C0x4C07F0x4C0800x4C080pcie_noc.router_2_3_3_repcie_noc.router_2_3_3_re0x4C0840x4C0870x4C0880x4C088pcie_noc.router_2_3_3_rempcie_noc.router_2_3_3_rem0x4C08C0x4C09F0x4C0A00x4C0A0pcie_noc.router_2_3_3_idpcie_noc.router_2_3_3_id0x4C0A40x4C0AF0x4C0B00x4C0B0pcie_noc.router_2_3_3_rcgopcie_noc.router_2_3_3_rcgo0x4C0B40x4C0C70x4C0C80x4C0C8pcie_noc.router_2_3_3_p2_rperrpcie_noc.router_2_3_3_p2_rperr0x4C0CC0x4C0CF0x4C0D00x4C0D0pcie_noc.router_2_3_3_p3_rperrpcie_noc.router_2_3_3_p3_rperr0x4C0D40x4C0D70x4C0D80x4C0D8pcie_noc.router_2_3_3_p4_rperrpcie_noc.router_2_3_3_p4_rperr0x4C0DC0x4C1070x4C1080x4C108pcie_noc.router_2_3_3_p2_rperrmpcie_noc.router_2_3_3_p2_rperrm0x4C10C0x4C10F0x4C1100x4C110pcie_noc.router_2_3_3_p3_rperrmpcie_noc.router_2_3_3_p3_rperrm0x4C1140x4C1170x4C1180x4C118pcie_noc.router_2_3_3_p4_rperrmpcie_noc.router_2_3_3_p4_rperrm0x4C11C0x5007F0x500800x50080pcie_noc.router_2_5_5_repcie_noc.router_2_5_5_re0x500840x500870x500880x50088pcie_noc.router_2_5_5_rempcie_noc.router_2_5_5_rem0x5008C0x5009F0x500A00x500A0pcie_noc.router_2_5_5_idpcie_noc.router_2_5_5_id0x500A40x500AF0x500B00x500B0pcie_noc.router_2_5_5_rcgopcie_noc.router_2_5_5_rcgo0x500B40x500B70x500B80x500B8pcie_noc.router_2_5_5_p0_rperrpcie_noc.router_2_5_5_p0_rperr0x500BC0x500BF0x500C00x500C0pcie_noc.router_2_5_5_p1_rperrpcie_noc.router_2_5_5_p1_rperr0x500C40x500D70x500D80x500D8pcie_noc.router_2_5_5_p4_rperrpcie_noc.router_2_5_5_p4_rperr0x500DC0x500F70x500F80x500F8pcie_noc.router_2_5_5_p0_rperrmpcie_noc.router_2_5_5_p0_rperrm0x500FC0x500FF0x501000x50100pcie_noc.router_2_5_5_p1_rperrmpcie_noc.router_2_5_5_p1_rperrm0x501040x501170x501180x50118pcie_noc.router_2_5_5_p4_rperrmpcie_noc.router_2_5_5_p4_rperrm0x5011C0x5407F0x540800x54080pcie_noc.router_2_7_7_repcie_noc.router_2_7_7_re0x540840x540870x540880x54088pcie_noc.router_2_7_7_rempcie_noc.router_2_7_7_rem0x5408C0x5409F0x540A00x540A0pcie_noc.router_2_7_7_idpcie_noc.router_2_7_7_id0x540A40x540AF0x540B00x540B0pcie_noc.router_2_7_7_rcgopcie_noc.router_2_7_7_rcgo0x540B40x540B70x540B80x540B8pcie_noc.router_2_7_7_p0_rperrpcie_noc.router_2_7_7_p0_rperr0x540BC0x540CF0x540D00x540D0pcie_noc.router_2_7_7_p3_rperrpcie_noc.router_2_7_7_p3_rperr0x540D40x540D70x540D80x540D8pcie_noc.router_2_7_7_p4_rperrpcie_noc.router_2_7_7_p4_rperr0x540DC0x540F70x540F80x540F8pcie_noc.router_2_7_7_p0_rperrmpcie_noc.router_2_7_7_p0_rperrm0x540FC0x5410F0x541100x54110pcie_noc.router_2_7_7_p3_rperrmpcie_noc.router_2_7_7_p3_rperrm0x541140x541170x541180x54118pcie_noc.router_2_7_7_p4_rperrmpcie_noc.router_2_7_7_p4_rperrm0x5411C0x7FFFFregisterpcie_noc.bridge_rbm_m_13_1_p_0bridge_rbm_m_13_1_p_0PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72rbm_m register p_00x3000R0x00000000Pcie_noc_bridge_rbm_m_13_1_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr35WT_QOS_0Weight of QoS profile 0700x00RWT_QOS_1PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr47WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr59WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr71WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_rbm_m_13_1_p_1bridge_rbm_m_13_1_p_1PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr138rbm_m register p_10x3008R0x00000000Pcie_noc_bridge_rbm_m_13_1_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr101WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr113WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr125WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr137WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_rbm_m_13_1_p_2bridge_rbm_m_13_1_p_2PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr204rbm_m register p_20x3010R0x00000000Pcie_noc_bridge_rbm_m_13_1_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr167WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr179WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr191WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr203WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_rbm_m_13_1_p_3bridge_rbm_m_13_1_p_3PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr270rbm_m register p_30x3018R0x00000000Pcie_noc_bridge_rbm_m_13_1_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr233WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr245WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr257WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_RBM_M_13_1_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr269WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_rbm_m_13_1_txebridge_rbm_m_13_1_txePCIE_NOC_BRIDGE_RBM_M_13_1_TXE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr416rbm_m register txe0x3040R/W0x00000000Pcie_noc_bridge_rbm_m_13_1_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr297TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr309SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr324TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr337EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr351FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr365FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr379FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr393FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr404PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr415UNSD_31_93190x000000Rregisterpcie_noc.bridge_rbm_m_13_1_txembridge_rbm_m_13_1_txemPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr495rbm_m register txem0x3048R/W0x00000008Pcie_noc_bridge_rbm_m_13_1_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr439UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr450TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr461EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr472UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr483PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr494UNSD_31_93190x000000Rregisterpcie_noc.bridge_rbm_m_13_1_btus_0bridge_rbm_m_13_1_btus_0PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr863rbm_m register btus_00x3058R0x00000000Pcie_noc_bridge_rbm_m_13_1_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr521L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr532L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr543L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr554L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr565L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr576L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr587L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr598L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr609L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr620L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr631L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr642L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr653L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr664L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr675L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr686L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr697L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr708L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr719L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr730L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr741L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr752L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr763L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr774L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr785L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr796L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr807L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr818L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr829L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr840L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr851L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr862L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_rbm_m_13_1_btus_1bridge_rbm_m_13_1_btus_1PCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1231rbm_m register btus_10x3060R0x00000000Pcie_noc_bridge_rbm_m_13_1_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr889L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr900L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr911L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr922L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr933L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr944L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr955L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr966L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr977L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr988L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr999L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr1010L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr1021L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr1032L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr1043L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr1054L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr1065L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr1076L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr1087L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr1098L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr1109L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr1120L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr1131L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr1142L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr1153L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr1164L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr1175L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr1186L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr1197L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr1208L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr1219L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr1230L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_rbm_m_13_1_btrl_0bridge_rbm_m_13_1_btrl_0PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1307rbm_m register btrl_00x3080R0x00000000Pcie_noc_bridge_rbm_m_13_1_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr1255WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr1266RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr1281CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr1295EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr1306UNSD_31_2131210x000Rregisterpcie_noc.bridge_rbm_m_13_1_btrl_1bridge_rbm_m_13_1_btrl_1PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1383rbm_m register btrl_10x3088R0x00000000Pcie_noc_bridge_rbm_m_13_1_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr1331WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr1342RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr1357CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr1371EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr1382UNSD_31_2131210x000Rregisterpcie_noc.bridge_rbm_m_13_1_btrl_2bridge_rbm_m_13_1_btrl_2PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1459rbm_m register btrl_20x3090R0x00000000Pcie_noc_bridge_rbm_m_13_1_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr1407WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr1418RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr1433CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr1447EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr1458UNSD_31_2131210x000Rregisterpcie_noc.bridge_rbm_m_13_1_btrl_3bridge_rbm_m_13_1_btrl_3PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1535rbm_m register btrl_30x3098R0x00000000Pcie_noc_bridge_rbm_m_13_1_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr1483WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr1494RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr1509CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr1523EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr1534UNSD_31_2131210x000Rregisterpcie_noc.bridge_rbm_m_13_1_btperrbridge_rbm_m_13_1_btperrPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1737rbm_m register btperr0x30A8R/W0x00000000Pcie_noc_bridge_rbm_m_13_1_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr1560L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr1571L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr1582L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr1593L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr1604L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr1615L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr1626L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr1637L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr1648L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr1659L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr1670L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr1681L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr1692L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr1703L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr1714L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr1725L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr1736UNSD31160x0000Rregisterpcie_noc.bridge_rbm_m_13_1_btperrmbridge_rbm_m_13_1_btperrmPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr1937rbm_m register btperrm0x30B0R/W0x00000000Pcie_noc_bridge_rbm_m_13_1_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr1760L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr1771L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr1782L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr1793L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr1804L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr1815L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr1826L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr1837L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr1848L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr1859L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr1870L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr1881L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr1892L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr1903L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr1914L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr1925L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr1936UNSD31160x0000Rregisterpcie_noc.bridge_rbm_m_13_1_rxebridge_rbm_m_13_1_rxePCIE_NOC_BRIDGE_RBM_M_13_1_RXE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr2045rbm_m register rxe0x3120R/W0x00000000Pcie_noc_bridge_rbm_m_13_1_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr1965CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr1976CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr1987CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr1998CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr2010EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr2021PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr2033EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr2044UNSD_31_73170x0000000Rregisterpcie_noc.bridge_rbm_m_13_1_rxembridge_rbm_m_13_1_rxemPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr2117rbm_m register rxem0x3128R/W0x00000050Pcie_noc_bridge_rbm_m_13_1_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr2066UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr2080EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr2091PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr2105EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr2116UNSD_31_73170x0000000Rregisterpcie_noc.bridge_rbm_m_13_1_brs_0bridge_rbm_m_13_1_brs_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr2391rbm_m register brs_00x3130R0x00000000Pcie_noc_bridge_rbm_m_13_1_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr2141OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr2152V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr2163S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr2174B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr2185F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr2195UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr2206OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr2217V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr2228S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr2239B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr2250F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr2260UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr2271OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr2282V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr2293S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr2304B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr2315F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr2325UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr2336OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr2347V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr2358S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr2369B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr2380F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr2390UNSD_31_3031300x0Rregisterpcie_noc.bridge_rbm_m_13_1_brs_1bridge_rbm_m_13_1_brs_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr2665rbm_m register brs_10x3138R0x00000000Pcie_noc_bridge_rbm_m_13_1_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr2415OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr2426V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr2437S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr2448B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr2459F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr2469UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr2480OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr2491V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr2502S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr2513B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr2524F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr2534UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr2545OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr2556V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr2567S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr2578B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr2589F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr2599UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr2610OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr2621V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr2632S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr2643B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr2654F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr2664UNSD_31_3031300x0Rregisterpcie_noc.bridge_rbm_m_13_1_brusbridge_rbm_m_13_1_brusPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr2734rbm_m register brus0x31B0R0x00000000Pcie_noc_bridge_rbm_m_13_1_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr2690V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr2701V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr2712V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr2723V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr2733UNSD_31_43140x0000000Rregisterpcie_noc.bridge_rbm_m_13_1_brperr0bridge_rbm_m_13_1_brperr0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr2962rbm_m register brperr00x31D0R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr2772D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr2783DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr2794SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr2806SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr2817PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr2828UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr2839D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr2850DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr2861SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr2873SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr2884PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr2895UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr2906UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr2917UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr2928UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr2939UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr2950UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr2961UNSD_63_5663560x00Rregisterpcie_noc.bridge_rbm_m_13_1_brperr1bridge_rbm_m_13_1_brperr1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3078rbm_m register brperr10x31D8R0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr3000UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr3011UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr3022UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr3033UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr3044UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr3055UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr3066UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr3077UNSD_63_5663560x00Rregisterpcie_noc.bridge_rbm_m_13_1_brperrm0bridge_rbm_m_13_1_brperrm0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3299rbm_m register brperrm00x31E0R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr3105D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr3117DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr3128SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr3140SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr3152PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr3163UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr3174D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr3186DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr3197SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr3209SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr3221PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr3232UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr3243UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr3254UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr3265UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr3276UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr3287UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr3298UNSD_63_5663560x00Rregisterpcie_noc.bridge_rbm_m_13_1_brperrm1bridge_rbm_m_13_1_brperrm1PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3404rbm_m register brperrm10x31E8R0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr3326UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr3337UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr3348UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr3359UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr3370UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr3381UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr3392UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_RBM_M_13_1_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr3403UNSD_63_5663560x00Rregisterpcie_noc.bridge_rbm_m_13_1_am_tocfgbridge_rbm_m_13_1_am_tocfgPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3478rbm_m register am_tocfg0x3C00R/W0x000000000000001fPcie_noc_bridge_rbm_m_13_1_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr3441TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr3452UNSD_7_6760x0RENPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr3466EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr3477UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_osslvbridge_rbm_m_13_1_am_osslvPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3513rbm_m register am_osslv0x3C08R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr3501SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr3512UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_cgcbridge_rbm_m_13_1_am_cgcPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3550rbm_m register am_cgc0x3C10R/W0x0000000000000064Pcie_noc_bridge_rbm_m_13_1_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr3538HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr3549UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_cgobridge_rbm_m_13_1_am_cgoPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3585rbm_m register am_cgo0x3C18R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr3573FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr3584UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_cfgbridge_rbm_m_13_1_am_cfgPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3622rbm_m register am_cfg0x3C20R/W0x0000000000000001Pcie_noc_bridge_rbm_m_13_1_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr3610AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr3621UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_stsbridge_rbm_m_13_1_am_stsPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3750rbm_m register am_sts0x3D00R0x000000000000000cPcie_noc_bridge_rbm_m_13_1_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr3655ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr3669WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr3681ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr3693WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr3704ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr3715AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr3727ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr3739AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr3749UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_bridge_idbridge_rbm_m_13_1_am_bridge_idPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3780rbm_m register am_bridge_id0x3D08R0x000000000000000dPcie_noc_bridge_rbm_m_13_1_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr3769IDUnique bridge ID1500x000dRUNSD_63_16PCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr3779UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_nocver_idbridge_rbm_m_13_1_am_nocver_idPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr3813rbm_m register am_nocver_id0x3D10R0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_nocver_idVersion identifier for the NoC. This read-only register is available only on the regbus master. This register is not available on pother master bridges and access will result in decode error response.falsefalsefalsefalseNOC_VERSION_IDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_NOC_VERSION_ID_SETns_noc_io_pcie_soc_ip.csr3802NOC_VERSION_IDNoC version ID3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_NOCVER_ID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr3812UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_errbridge_rbm_m_13_1_am_errPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4309rbm_m register am_err0x3E00R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr3835E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr3847E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr3859E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr3871E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr3883E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr3895E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr3908E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr3921E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr3932E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr3943UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr3954E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr3965E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr3976E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr3987E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr3998E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr4009E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr4020E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr4032E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr4043E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr4054UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr4065E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr4076E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr4088E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr4100E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr4111UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr4123E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr4134E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr4145E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr4156E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr4167E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr4178E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr4189E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr4201E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr4213E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr4225E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr4237E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr4249E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr4261E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr4273E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr4285E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr4297E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr4308UNSD_63_5663560x00Rregisterpcie_noc.bridge_rbm_m_13_1_am_toslvidbridge_rbm_m_13_1_am_toslvidPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4354rbm_m register am_toslvid0x3E08R0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr4332AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr4343AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr4353UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_erabridge_rbm_m_13_1_am_eraPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4376rbm_m register am_era0x3E10R0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr4375READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_ewabridge_rbm_m_13_1_am_ewaPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4398rbm_m register am_ewa0x3E18R0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr4397WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_intmbridge_rbm_m_13_1_am_intmPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4882rbm_m register am_intm0x3E40R/W0x00007e07004f004fPcie_noc_bridge_rbm_m_13_1_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr4420M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr4431M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr4442M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr4453M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr4464M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr4475M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr4486M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr4497M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr4508M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr4519UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr4530M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr4541M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr4552M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr4563M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr4574M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr4585M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr4596M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr4607M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr4618M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr4629UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr4640M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr4651M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr4662M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr4673M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr4684UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr4696M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr4707M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr4718M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr4729M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr4740M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr4751M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr4762M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr4774E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr4786E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr4798E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr4810E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr4822E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr4834E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr4846E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr4858E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr4870E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr4881UNSD_63_5663560x00Rregisterpcie_noc.bridge_rbm_m_13_1_am_caddrbridge_rbm_m_13_1_am_caddrPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4904rbm_m register am_caddr0x3F00R/W0xffffffffffffffffPcie_noc_bridge_rbm_m_13_1_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr4903CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_rbm_m_13_1_am_caddrmskbridge_rbm_m_13_1_am_caddrmskPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr4927rbm_m register am_caddrmsk0x3F08R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr4926CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_rbm_m_13_1_am_ccmd0bridge_rbm_m_13_1_am_ccmd0PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5117rbm_m register am_ccmd00x3F10R/W0x0000000003fff33fPcie_noc_bridge_rbm_m_13_1_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr4949SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr4960DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr4971UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr4982BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr4993UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr5004CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr5015QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr5026PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr5037LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr5048RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr5059VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr5070UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr5082INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr5093UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr5105TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr5116UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_ccmdmsk0bridge_rbm_m_13_1_am_ccmdmsk0PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5261rbm_m register am_ccmdmsk00x3F18R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr5139SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr5150DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr5161UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr5172BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr5183UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr5194CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr5205QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr5216PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr5227LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr5238RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr5249VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr5260UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_cntr0bridge_rbm_m_13_1_am_cntr0PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5296rbm_m register am_cntr00x3F20R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr5284CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr5295UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_latnum0bridge_rbm_m_13_1_am_latnum0PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5335rbm_m register am_latnum00x3F28R/W0x0000000000000007Pcie_noc_bridge_rbm_m_13_1_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr5323CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr5334UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_ccmd1bridge_rbm_m_13_1_am_ccmd1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5525rbm_m register am_ccmd10x3F30R/W0x0000000003fff33fPcie_noc_bridge_rbm_m_13_1_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr5357SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr5368DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr5379UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr5390BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr5401UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr5412CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr5423QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr5434PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr5445LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr5456RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr5467VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr5478UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr5490INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr5501UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr5513TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr5524UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_ccmdmsk1bridge_rbm_m_13_1_am_ccmdmsk1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5669rbm_m register am_ccmdmsk10x3F38R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr5547SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr5558DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr5569UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr5580BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr5591UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr5602CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr5613QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr5624PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr5635LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr5646RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr5657VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr5668UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_cntr1bridge_rbm_m_13_1_am_cntr1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5704rbm_m register am_cntr10x3F40R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr5692CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr5703UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_latnum1bridge_rbm_m_13_1_am_latnum1PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5743rbm_m register am_latnum10x3F48R/W0x0000000000000007Pcie_noc_bridge_rbm_m_13_1_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr5731CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr5742UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_arovrdbridge_rbm_m_13_1_am_arovrdPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5856rbm_m register am_arovrd0x3F60R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr5761arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr5774arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr5785arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr5796UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr5809arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr5820UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr5831arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr5844arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr5855UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_rbm_m_13_1_am_awovrdbridge_rbm_m_13_1_am_awovrdPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5969rbm_m register am_awovrd0x3F68R/W0x0000000000000000Pcie_noc_bridge_rbm_m_13_1_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr5874awcache_valValue to override incoming ARCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr5887awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr5898awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr5909UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr5922awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr5933UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr5944awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr5957awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_RBM_M_13_1_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr5968UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_versionbridge_main0_apb_s_6_6_apbslv_bridge_versionPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr5997main0_apb_s register apbslv_bridge_version0x4200R0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_apbslv_bridge_versionBridge version register.falsefalsefalsefalseVERPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_VER_SETns_noc_io_pcie_soc_ip.csr5986VERBridge version.300x0RUNSD_63_4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_VERSION_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr5996UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_apbslv_bridge_idbridge_main0_apb_s_6_6_apbslv_bridge_idPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6037main0_apb_s register apbslv_bridge_id0x4208R0x0000000000000006Pcie_noc_bridge_main0_apb_s_6_6_apbslv_bridge_idBridge ID register.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr6014IDUnique bridge id.900x006RZEROESPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_ZEROES_SETns_noc_io_pcie_soc_ip.csr6025ZEROESZeroes15100x00RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr6036UNSD_63_16Unused63160x000000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_apbslv_slvs_sleep_statusbridge_main0_apb_s_6_6_apbslv_slvs_sleep_statusPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6246main0_apb_s register apbslv_slvs_sleep_status0x4210R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_apbslv_slvs_sleep_statusSlave sleep status register.falsefalsefalsefalseSTS_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_0_SETns_noc_io_pcie_soc_ip.csr6054STS_01'b1: Slave is in sleep mode1'b0: Slave is active000x0R/WSTS_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_1_SETns_noc_io_pcie_soc_ip.csr6066STS_11'b1: Slave is in sleep mode1'b0: Slave is active110x0R/WSTS_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_2_SETns_noc_io_pcie_soc_ip.csr6078STS_21'b1: Slave is in sleep mode1'b0: Slave is active220x0R/WSTS_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_3_SETns_noc_io_pcie_soc_ip.csr6090STS_31'b1: Slave is in sleep mode1'b0: Slave is active330x0R/WSTS_4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_4_SETns_noc_io_pcie_soc_ip.csr6102STS_41'b1: Slave is in sleep mode1'b0: Slave is active440x0R/WSTS_5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_5_SETns_noc_io_pcie_soc_ip.csr6114STS_51'b1: Slave is in sleep mode1'b0: Slave is active550x0R/WSTS_6PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_6_SETns_noc_io_pcie_soc_ip.csr6126STS_61'b1: Slave is in sleep mode1'b0: Slave is active660x0R/WSTS_7PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_7_SETns_noc_io_pcie_soc_ip.csr6138STS_71'b1: Slave is in sleep mode1'b0: Slave is active770x0R/WSTS_8PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_8_SETns_noc_io_pcie_soc_ip.csr6150STS_81'b1: Slave is in sleep mode1'b0: Slave is active880x0R/WSTS_9PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_9_SETns_noc_io_pcie_soc_ip.csr6162STS_91'b1: Slave is in sleep mode1'b0: Slave is active990x0R/WSTS_10PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_10_SETns_noc_io_pcie_soc_ip.csr6174STS_101'b1: Slave is in sleep mode1'b0: Slave is active10100x0R/WSTS_11PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_11_SETns_noc_io_pcie_soc_ip.csr6186STS_111'b1: Slave is in sleep mode1'b0: Slave is active11110x0R/WSTS_12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_12_SETns_noc_io_pcie_soc_ip.csr6198STS_121'b1: Slave is in sleep mode1'b0: Slave is active12120x0R/WSTS_13PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_13_SETns_noc_io_pcie_soc_ip.csr6210STS_131'b1: Slave is in sleep mode1'b0: Slave is active13130x0R/WSTS_14PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_14_SETns_noc_io_pcie_soc_ip.csr6222STS_141'b1: Slave is in sleep mode1'b0: Slave is active14140x0R/WSTS_15PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_STS_15_SETns_noc_io_pcie_soc_ip.csr6234STS_151'b1: Slave is in sleep mode1'b0: Slave is active15150x0R/WUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_APBSLV_SLVS_SLEEP_STATUS_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr6245UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_cgcbridge_main0_apb_s_6_6_as_cgcPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6283main0_apb_s register as_cgc0x5C10R/W0x0000000000000064Pcie_noc_bridge_main0_apb_s_6_6_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr6271HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr6282UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_cgobridge_main0_apb_s_6_6_as_cgoPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6318main0_apb_s register as_cgo0x5C18R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr6306FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr6317UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_stsbridge_main0_apb_s_6_6_as_stsPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6392main0_apb_s register as_sts0x5D00R0x000000000000000cPcie_noc_bridge_main0_apb_s_6_6_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr6341WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr6357ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr6369WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr6381ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr6391UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_bridge_idbridge_main0_apb_s_6_6_as_bridge_idPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6422main0_apb_s register as_bridge_id0x5D08R0x0000000000000006Pcie_noc_bridge_main0_apb_s_6_6_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr6411IDUnique bridge ID1500x0006RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr6421UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_errbridge_main0_apb_s_6_6_as_errPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr6775main0_apb_s register as_err0x5E00R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr6443E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr6455E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr6468E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr6482E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr6494E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr6505UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr6517E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr6529E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr6542E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr6554E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr6565UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr6577E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr6588E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr6599E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr6610E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr6621E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr6632E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr6643E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr6655E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr6667E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr6679E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr6691E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr6703E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr6715E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr6727E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr6739E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr6751E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr6763E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr6774UNSD_63_4963490x0000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_intmbridge_main0_apb_s_6_6_as_intmPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7115main0_apb_s register as_intm0x5E40R/W0x0000007d000b0013Pcie_noc_bridge_main0_apb_s_6_6_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr6796M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr6807M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr6818M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr6829M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr6840M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr6851UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr6862M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr6873M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr6884M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr6895M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr6906UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr6917M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr6928M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr6939M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr6950M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr6961M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr6972M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr6983M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr6995E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr7007E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr7019E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr7031E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr7043E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr7055E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr7067E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr7079E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr7091E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr7103E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr7114UNSD_63_4963490x0000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_ccmdbridge_main0_apb_s_6_6_as_ccmdPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7190main0_apb_s register as_ccmd0x5F00R/W0x0000000003000000Pcie_noc_bridge_main0_apb_s_6_6_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr7133UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr7144rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr7155val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr7166UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr7178intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr7189UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_ccmdmskbridge_main0_apb_s_6_6_as_ccmdmskPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7242main0_apb_s register as_ccmdmsk0x5F08R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr7208UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr7219rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr7230val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr7241UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_cntrbridge_main0_apb_s_6_6_as_cntrPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7272main0_apb_s register as_cntr0x5F10R0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr7261CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr7271UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_arovrdbridge_main0_apb_s_6_6_as_arovrdPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7385main0_apb_s register as_arovrd0x5F18R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr7290arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr7303arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr7314arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr7325UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr7338arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr7349UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr7360arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr7373arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr7384UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_as_awovrdbridge_main0_apb_s_6_6_as_awovrdPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7498main0_apb_s register as_awovrd0x5F20R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr7403awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr7416awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr7427awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr7438UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr7451awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr7462UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr7473awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr7486awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr7497UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_p_0bridge_main0_apb_s_6_6_p_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7563main0_apb_s register p_00x7000R/W0x00000003Pcie_noc_bridge_main0_apb_s_6_6_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr7526WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr7538WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr7550WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr7562WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_p_1bridge_main0_apb_s_6_6_p_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7629main0_apb_s register p_10x7008R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr7592WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr7604WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr7616WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr7628WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_p_2bridge_main0_apb_s_6_6_p_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7695main0_apb_s register p_20x7010R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr7658WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr7670WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr7682WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr7694WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_p_3bridge_main0_apb_s_6_6_p_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7761main0_apb_s register p_30x7018R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr7724WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr7736WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr7748WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr7760WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_txebridge_main0_apb_s_6_6_txePCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7907main0_apb_s register txe0x7040R/W0x00000000Pcie_noc_bridge_main0_apb_s_6_6_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr7788TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr7800SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr7815TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr7828EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr7842FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr7856FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr7870FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr7884FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr7895PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr7906UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_txembridge_main0_apb_s_6_6_txemPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr7986main0_apb_s register txem0x7048R/W0x00000008Pcie_noc_bridge_main0_apb_s_6_6_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr7930UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr7941TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr7952EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr7963UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr7974PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr7985UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_btus_0bridge_main0_apb_s_6_6_btus_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr8354main0_apb_s register btus_00x7058R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr8012L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr8023L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr8034L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr8045L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr8056L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr8067L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr8078L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr8089L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr8100L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr8111L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr8122L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr8133L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr8144L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr8155L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr8166L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr8177L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr8188L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr8199L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr8210L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr8221L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr8232L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr8243L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr8254L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr8265L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr8276L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr8287L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr8298L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr8309L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr8320L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr8331L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr8342L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr8353L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_main0_apb_s_6_6_btus_1bridge_main0_apb_s_6_6_btus_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr8722main0_apb_s register btus_10x7060R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr8380L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr8391L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr8402L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr8413L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr8424L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr8435L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr8446L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr8457L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr8468L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr8479L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr8490L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr8501L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr8512L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr8523L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr8534L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr8545L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr8556L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr8567L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr8578L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr8589L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr8600L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr8611L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr8622L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr8633L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr8644L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr8655L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr8666L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr8677L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr8688L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr8699L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr8710L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr8721L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_main0_apb_s_6_6_btrl_0bridge_main0_apb_s_6_6_btrl_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr8798main0_apb_s register btrl_00x7080R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr8746WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr8757RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr8772CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr8786EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr8797UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_apb_s_6_6_btrl_1bridge_main0_apb_s_6_6_btrl_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr8874main0_apb_s register btrl_10x7088R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr8822WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr8833RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr8848CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr8862EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr8873UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_apb_s_6_6_btrl_2bridge_main0_apb_s_6_6_btrl_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr8950main0_apb_s register btrl_20x7090R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr8898WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr8909RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr8924CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr8938EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr8949UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_apb_s_6_6_btrl_3bridge_main0_apb_s_6_6_btrl_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr9026main0_apb_s register btrl_30x7098R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr8974WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr8985RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr9000CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr9014EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr9025UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_apb_s_6_6_btperrbridge_main0_apb_s_6_6_btperrPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr9228main0_apb_s register btperr0x70A8R/W0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr9051L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr9062L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr9073L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr9084L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr9095L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr9106L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr9117L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr9128L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr9139L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr9150L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr9161L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr9172L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr9183L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr9194L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr9205L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr9216L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr9227UNSD31160x0000Rregisterpcie_noc.bridge_main0_apb_s_6_6_btperrmbridge_main0_apb_s_6_6_btperrmPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr9428main0_apb_s register btperrm0x70B0R/W0x00000000Pcie_noc_bridge_main0_apb_s_6_6_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr9251L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr9262L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr9273L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr9284L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr9295L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr9306L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr9317L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr9328L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr9339L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr9350L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr9361L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr9372L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr9383L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr9394L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr9405L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr9416L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr9427UNSD31160x0000Rregisterpcie_noc.bridge_main0_apb_s_6_6_rxebridge_main0_apb_s_6_6_rxePCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr9536main0_apb_s register rxe0x7120R/W0x00000000Pcie_noc_bridge_main0_apb_s_6_6_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr9456CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr9467CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr9478CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr9489CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr9501EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr9512PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr9524EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr9535UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_rxembridge_main0_apb_s_6_6_rxemPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr9608main0_apb_s register rxem0x7128R/W0x00000050Pcie_noc_bridge_main0_apb_s_6_6_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr9557UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr9571EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr9582PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr9596EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr9607UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_brs_0bridge_main0_apb_s_6_6_brs_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr9882main0_apb_s register brs_00x7130R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr9632OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr9643V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr9654S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr9665B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr9676F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr9686UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr9697OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr9708V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr9719S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr9730B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr9741F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr9751UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr9762OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr9773V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr9784S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr9795B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr9806F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr9816UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr9827OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr9838V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr9849S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr9860B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr9871F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr9881UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_apb_s_6_6_brs_1bridge_main0_apb_s_6_6_brs_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr10156main0_apb_s register brs_10x7138R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr9906OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr9917V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr9928S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr9939B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr9950F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr9960UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr9971OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr9982V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr9993S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr10004B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr10015F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr10025UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr10036OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr10047V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr10058S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr10069B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr10080F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr10090UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr10101OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr10112V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr10123S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr10134B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr10145F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr10155UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_apb_s_6_6_brusbridge_main0_apb_s_6_6_brusPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr10225main0_apb_s register brus0x71B0R0x00000000Pcie_noc_bridge_main0_apb_s_6_6_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr10181V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr10192V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr10203V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr10214V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr10224UNSD_31_43140x0000000Rregisterpcie_noc.bridge_main0_apb_s_6_6_brperr0bridge_main0_apb_s_6_6_brperr0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr10453main0_apb_s register brperr00x71D0R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr10263D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr10274DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr10285SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr10297SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr10308PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr10319UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr10330D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr10341DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr10352SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr10364SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr10375PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr10386UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr10397UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr10408UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr10419UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr10430UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr10441UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr10452UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_brperr1bridge_main0_apb_s_6_6_brperr1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr10569main0_apb_s register brperr10x71D8R0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr10491UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr10502UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr10513UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr10524UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr10535UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr10546UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr10557UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr10568UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_brperrm0bridge_main0_apb_s_6_6_brperrm0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr10790main0_apb_s register brperrm00x71E0R/W0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr10596D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr10608DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr10619SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr10631SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr10643PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr10654UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr10665D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr10677DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr10688SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr10700SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr10712PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr10723UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr10734UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr10745UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr10756UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr10767UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr10778UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr10789UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_apb_s_6_6_brperrm1bridge_main0_apb_s_6_6_brperrm1PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr10895main0_apb_s register brperrm10x71E8R0x0000000000000000Pcie_noc_bridge_main0_apb_s_6_6_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr10817UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr10828UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr10839UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr10850UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr10861UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr10872UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr10883UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_APB_S_6_6_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr10894UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11011main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x8000R/W0x0000000058200000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr10935P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr10946NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr10957I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr10969R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr10980DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr10992LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr11003BASE_ADDRESS_0_33Base address3960x001608000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11010UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11103main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x8008R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr11028P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr11039NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr11050I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr11061VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr11073TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr11084RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr11095MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11102UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11219main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_00x8020R/W0x0000000058201000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr11143P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr11154NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr11165I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr11177R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_SETns_noc_io_pcie_soc_ip.csr11188DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr11200LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr11211BASE_ADDRESS_0_33Base address3960x001608040R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11218UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11311main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_00x8028R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr11236P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr11247NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr11258I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr11269VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_SETns_noc_io_pcie_soc_ip.csr11281TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr11292RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr11303MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11310UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11427main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_00x8040R/W0x0000000058400000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SETns_noc_io_pcie_soc_ip.csr11351P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr11362NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SETns_noc_io_pcie_soc_ip.csr11373I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr11385R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_SETns_noc_io_pcie_soc_ip.csr11396DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr11408LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr11419BASE_ADDRESS_0_33Base address3960x001610000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11426UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11519main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_00x8048R/W0x000000ffffe00000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SETns_noc_io_pcie_soc_ip.csr11444P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr11455NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SETns_noc_io_pcie_soc_ip.csr11466I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr11477VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_SETns_noc_io_pcie_soc_ip.csr11489TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr11500RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr11511MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11518UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11635main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x8060R/W0x0000007f80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr11559P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr11570NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr11581I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr11593R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr11604DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr11616LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr11627BASE_ADDRESS_0_33Base address3960x1fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11634UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11727main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x8068R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr11652P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr11663NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr11674I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr11685VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr11697TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr11708RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr11719MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11726UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11768main0_dbg_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x8070R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr11745UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr11756SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr11767UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11884main0_dbg_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x8080R/W0x0000007f80001000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr11808P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr11819NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr11830I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr11842R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr11853DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr11865LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr11876BASE_ADDRESS_0_33Base address3960x1fe000040R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11883UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr11976main0_dbg_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x8088R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr11901P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr11912NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr11923I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr11934VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr11946TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr11957RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr11968MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr11975UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12017main0_dbg_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x8090R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr11994UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr12005SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SETns_noc_io_pcie_soc_ip.csr12016UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12133main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00x80A0R/W0x0000000080000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr12057P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr12068NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr12079I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr12091R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr12102DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr12114LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr12125BASE_ADDRESS_0_33Base address3960x002000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12132UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12225main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00x80A8R/W0x000000ff80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr12150P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr12161NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr12172I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr12183VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr12195TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr12206RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr12217MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12224UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12341main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00x80C0R/W0x0000008000200000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr12265P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr12276NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr12287I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr12299R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SETns_noc_io_pcie_soc_ip.csr12310DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr12322LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr12333BASE_ADDRESS_0_33Base address3960x200008000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12340UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12433main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00x80C8R/W0x000000ffffe00000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr12358P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr12369NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr12380I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr12391VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SETns_noc_io_pcie_soc_ip.csr12403TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr12414RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr12425MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12432UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12549main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00x80E0R/W0x0000008000400000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr12473P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr12484NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr12495I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr12507R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SETns_noc_io_pcie_soc_ip.csr12518DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr12530LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr12541BASE_ADDRESS_0_33Base address3960x200010000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12548UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12641main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00x80E8R/W0x000000ffffc00000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr12566P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr12577NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr12588I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr12599VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SETns_noc_io_pcie_soc_ip.csr12611TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr12622RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr12633MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12640UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12757main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00x8100R/W0x0000008000800000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr12681P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr12692NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr12703I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr12715R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SETns_noc_io_pcie_soc_ip.csr12726DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr12738LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr12749BASE_ADDRESS_0_33Base address3960x200020000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12756UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12849main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00x8108R/W0x000000ffff800000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr12774P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr12785NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr12796I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr12807VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SETns_noc_io_pcie_soc_ip.csr12819TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr12830RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr12841MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12848UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr12965main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00x8120R/W0x0000008001000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr12889P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr12900NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr12911I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr12923R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SETns_noc_io_pcie_soc_ip.csr12934DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr12946LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr12957BASE_ADDRESS_0_33Base address3960x200040000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr12964UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13057main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00x8128R/W0x000000ffff000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr12982P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr12993NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr13004I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr13015VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SETns_noc_io_pcie_soc_ip.csr13027TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr13038RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr13049MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13056UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13173main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00x8140R/W0x0000008002000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr13097P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr13108NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr13119I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr13131R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SETns_noc_io_pcie_soc_ip.csr13142DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr13154LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr13165BASE_ADDRESS_0_33Base address3960x200080000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13172UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13265main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00x8148R/W0x000000fffe000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr13190P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr13201NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr13212I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr13223VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SETns_noc_io_pcie_soc_ip.csr13235TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr13246RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr13257MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13264UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13381main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00x8160R/W0x0000008004000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr13305P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr13316NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr13327I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr13339R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr13350DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr13362LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr13373BASE_ADDRESS_0_33Base address3960x200100000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13380UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13473main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00x8168R/W0x000000fffc000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr13398P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr13409NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr13420I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr13431VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr13443TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr13454RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr13465MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13472UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13589main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00x8180R/W0x0000008008000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr13513P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr13524NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr13535I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr13547R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr13558DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr13570LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr13581BASE_ADDRESS_0_33Base address3960x200200000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13588UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13681main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00x8188R/W0x000000fff8000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr13606P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr13617NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr13628I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr13639VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr13651TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr13662RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr13673MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13680UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13797main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00x81A0R/W0x0000008010000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr13721P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr13732NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr13743I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr13755R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr13766DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr13778LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr13789BASE_ADDRESS_0_33Base address3960x200400000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13796UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr13889main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00x81A8R/W0x000000fff0000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr13814P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr13825NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr13836I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr13847VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr13859TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr13870RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr13881MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr13888UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14005main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00x81C0R/W0x0000008020000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr13929P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr13940NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr13951I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr13963R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr13974DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr13986LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr13997BASE_ADDRESS_0_33Base address3960x200800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14004UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14097main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00x81C8R/W0x000000ffe0000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr14022P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr14033NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr14044I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr14055VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr14067TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr14078RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr14089MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14096UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14213main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00x81E0R/W0x0000008040000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr14137P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr14148NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr14159I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr14171R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SETns_noc_io_pcie_soc_ip.csr14182DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr14194LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr14205BASE_ADDRESS_0_33Base address3960x201000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14212UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14305main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00x81E8R/W0x000000ffc0000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr14230P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr14241NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr14252I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr14263VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SETns_noc_io_pcie_soc_ip.csr14275TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr14286RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr14297MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14304UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14421main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00x8200R/W0x0000008080000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr14345P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr14356NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr14367I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr14379R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SETns_noc_io_pcie_soc_ip.csr14390DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr14402LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr14413BASE_ADDRESS_0_33Base address3960x202000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14420UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14513main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00x8208R/W0x000000ff80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr14438P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr14449NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr14460I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr14471VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SETns_noc_io_pcie_soc_ip.csr14483TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr14494RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr14505MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14512UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14629main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00x8220R/W0x0000008100000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr14553P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr14564NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr14575I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr14587R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SETns_noc_io_pcie_soc_ip.csr14598DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr14610LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr14621BASE_ADDRESS_0_33Base address3960x204000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14628UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14721main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00x8228R/W0x000000ff00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr14646P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr14657NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr14668I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr14679VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SETns_noc_io_pcie_soc_ip.csr14691TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr14702RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr14713MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14720UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14837main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00x8240R/W0x0000008200000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr14761P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr14772NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr14783I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr14795R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SETns_noc_io_pcie_soc_ip.csr14806DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr14818LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr14829BASE_ADDRESS_0_33Base address3960x208000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14836UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr14929main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00x8248R/W0x000000fe00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr14854P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr14865NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr14876I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr14887VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SETns_noc_io_pcie_soc_ip.csr14899TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr14910RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr14921MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr14928UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15045main0_dbg_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00x8260R/W0x0000008400000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr14969P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr14980NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr14991I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr15003R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SETns_noc_io_pcie_soc_ip.csr15014DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr15026LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr15037BASE_ADDRESS_0_33Base address3960x210000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15044UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15137main0_dbg_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00x8268R/W0x000000fc00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr15062P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr15073NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr15084I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr15095VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SETns_noc_io_pcie_soc_ip.csr15107TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr15118RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr15129MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15136UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15253main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00x8280R/W0x0000000002000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr15177P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr15188NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr15199I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr15211R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr15222DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr15234LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr15245BASE_ADDRESS_0_33Base address3960x000080000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15252UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15345main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00x8288R/W0x000000ffffff0000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr15270P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr15281NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr15292I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr15303VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr15315TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr15326RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr15337MASK_0_33Mask3960x3fffffc00R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15344UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15461main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00x82A0R/W0x0000000020007000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr15385P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr15396NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr15407I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr15419R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr15430DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr15442LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr15453BASE_ADDRESS_0_33Base address3960x0008001c0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15460UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15553main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00x82A8R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr15478P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr15489NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr15500I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr15511VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr15523TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr15534RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr15545MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15552UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15669main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00x82C0R/W0x0000000030001000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr15593P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr15604NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr15615I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr15627R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr15638DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr15650LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr15661BASE_ADDRESS_0_33Base address3960x000c00040R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15668UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15761main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00x82C8R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr15686P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr15697NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr15708I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr15719VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr15731TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr15742RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr15753MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15760UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15877main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00x82E0R/W0x0000000030003000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr15801P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr15812NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr15823I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr15835R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SETns_noc_io_pcie_soc_ip.csr15846DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr15858LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr15869BASE_ADDRESS_0_33Base address3960x000c000c0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15876UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr15969main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00x82E8R/W0x000000fffffff000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr15894P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr15905NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr15916I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr15927VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SETns_noc_io_pcie_soc_ip.csr15939TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr15950RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr15961MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr15968UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16085main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00x8300R/W0x0000000030008000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr16009P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr16020NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr16031I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr16043R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SETns_noc_io_pcie_soc_ip.csr16054DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr16066LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr16077BASE_ADDRESS_0_33Base address3960x000c00200R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16084UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16177main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00x8308R/W0x000000ffffffe000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr16102P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr16113NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr16124I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr16135VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SETns_noc_io_pcie_soc_ip.csr16147TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr16158RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr16169MASK_0_33Mask3960x3ffffff80R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16176UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16293main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00x8320R/W0x0000000100000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr16217P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr16228NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr16239I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr16251R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SETns_noc_io_pcie_soc_ip.csr16262DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr16274LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr16285BASE_ADDRESS_0_33Base address3960x004000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16292UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16385main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00x8328R/W0x000000ff00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr16310P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr16321NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr16332I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr16343VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SETns_noc_io_pcie_soc_ip.csr16355TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr16366RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr16377MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16384UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16501main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00x8340R/W0x000000c000200000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr16425P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr16436NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr16447I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr16459R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr16470DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr16482LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr16493BASE_ADDRESS_0_33Base address3960x300008000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16500UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16593main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00x8348R/W0x000000ffffe00000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr16518P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr16529NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr16540I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr16551VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr16563TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr16574RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr16585MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16592UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16709main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00x8360R/W0x000000c000400000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr16633P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr16644NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr16655I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr16667R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr16678DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr16690LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr16701BASE_ADDRESS_0_33Base address3960x300010000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16708UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16801main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00x8368R/W0x000000ffffc00000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr16726P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr16737NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr16748I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr16759VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr16771TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr16782RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr16793MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16800UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr16917main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00x8380R/W0x000000c000800000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr16841P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr16852NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr16863I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr16875R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr16886DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr16898LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr16909BASE_ADDRESS_0_33Base address3960x300020000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr16916UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17009main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00x8388R/W0x000000ffff800000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr16934P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr16945NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr16956I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr16967VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr16979TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr16990RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr17001MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17008UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17125main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00x83A0R/W0x000000c001000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr17049P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr17060NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr17071I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr17083R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr17094DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr17106LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr17117BASE_ADDRESS_0_33Base address3960x300040000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17124UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17217main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00x83A8R/W0x000000ffff000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr17142P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr17153NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr17164I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr17175VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr17187TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr17198RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr17209MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17216UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17333main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00x83C0R/W0x000000c002000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr17257P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr17268NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr17279I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr17291R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SETns_noc_io_pcie_soc_ip.csr17302DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr17314LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr17325BASE_ADDRESS_0_33Base address3960x300080000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17332UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17425main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00x83C8R/W0x000000fffe000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr17350P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr17361NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr17372I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr17383VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SETns_noc_io_pcie_soc_ip.csr17395TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr17406RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr17417MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17424UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17541main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00x83E0R/W0x000000c004000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr17465P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr17476NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr17487I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr17499R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SETns_noc_io_pcie_soc_ip.csr17510DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr17522LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr17533BASE_ADDRESS_0_33Base address3960x300100000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17540UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17633main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00x83E8R/W0x000000fffc000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr17558P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr17569NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr17580I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr17591VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SETns_noc_io_pcie_soc_ip.csr17603TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr17614RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr17625MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17632UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17749main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00x8400R/W0x000000c008000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr17673P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr17684NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr17695I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr17707R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SETns_noc_io_pcie_soc_ip.csr17718DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr17730LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr17741BASE_ADDRESS_0_33Base address3960x300200000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17748UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17841main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00x8408R/W0x000000fff8000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr17766P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr17777NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr17788I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr17799VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SETns_noc_io_pcie_soc_ip.csr17811TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr17822RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr17833MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17840UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr17957main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00x8420R/W0x000000c010000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr17881P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr17892NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr17903I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr17915R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SETns_noc_io_pcie_soc_ip.csr17926DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr17938LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr17949BASE_ADDRESS_0_33Base address3960x300400000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr17956UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18049main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00x8428R/W0x000000fff0000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr17974P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr17985NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr17996I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr18007VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SETns_noc_io_pcie_soc_ip.csr18019TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr18030RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr18041MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18048UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18165main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00x8440R/W0x000000c020000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr18089P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr18100NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr18111I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr18123R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SETns_noc_io_pcie_soc_ip.csr18134DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr18146LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr18157BASE_ADDRESS_0_33Base address3960x300800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18164UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18257main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00x8448R/W0x000000ffe0000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr18182P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr18193NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr18204I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr18215VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SETns_noc_io_pcie_soc_ip.csr18227TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr18238RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr18249MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18256UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18373main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00x8460R/W0x000000c040000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr18297P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr18308NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr18319I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SETns_noc_io_pcie_soc_ip.csr18331R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SETns_noc_io_pcie_soc_ip.csr18342DI1'b1: Address range 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disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr18365BASE_ADDRESS_0_33Base address3960x301000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18372UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18465main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00x8468R/W0x000000ffc0000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr18390P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr18401NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr18412I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SETns_noc_io_pcie_soc_ip.csr18423VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SETns_noc_io_pcie_soc_ip.csr18435TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SETns_noc_io_pcie_soc_ip.csr18446RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr18457MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18464UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18581main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00x8480R/W0x000000c080000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr18505P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr18516NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr18527I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SETns_noc_io_pcie_soc_ip.csr18539R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SETns_noc_io_pcie_soc_ip.csr18550DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SETns_noc_io_pcie_soc_ip.csr18562LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr18573BASE_ADDRESS_0_33Base address3960x302000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18580UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18673main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00x8488R/W0x000000ff80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr18598P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr18609NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr18620I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SETns_noc_io_pcie_soc_ip.csr18631VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SETns_noc_io_pcie_soc_ip.csr18643TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SETns_noc_io_pcie_soc_ip.csr18654RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr18665MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18672UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18789main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00x84A0R/W0x000000c100000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr18713P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr18724NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr18735I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SETns_noc_io_pcie_soc_ip.csr18747R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SETns_noc_io_pcie_soc_ip.csr18758DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SETns_noc_io_pcie_soc_ip.csr18770LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr18781BASE_ADDRESS_0_33Base address3960x304000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18788UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18881main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00x84A8R/W0x000000ff00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr18806P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr18817NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr18828I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SETns_noc_io_pcie_soc_ip.csr18839VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SETns_noc_io_pcie_soc_ip.csr18851TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SETns_noc_io_pcie_soc_ip.csr18862RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr18873MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18880UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr18997main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00x84C0R/W0x000000c200000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr18921P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr18932NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr18943I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SETns_noc_io_pcie_soc_ip.csr18955R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SETns_noc_io_pcie_soc_ip.csr18966DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SETns_noc_io_pcie_soc_ip.csr18978LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr18989BASE_ADDRESS_0_33Base address3960x308000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr18996UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19089main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00x84C8R/W0x000000fe00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr19014P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr19025NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr19036I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SETns_noc_io_pcie_soc_ip.csr19047VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SETns_noc_io_pcie_soc_ip.csr19059TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SETns_noc_io_pcie_soc_ip.csr19070RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr19081MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19088UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19205main0_dbg_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00x84E0R/W0x000000c400000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr19129P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr19140NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr19151I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SETns_noc_io_pcie_soc_ip.csr19163R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SETns_noc_io_pcie_soc_ip.csr19174DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SETns_noc_io_pcie_soc_ip.csr19186LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr19197BASE_ADDRESS_0_33Base address3960x310000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19204UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19297main0_dbg_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00x84E8R/W0x000000fc00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr19222P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr19233NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr19244I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SETns_noc_io_pcie_soc_ip.csr19255VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SETns_noc_io_pcie_soc_ip.csr19267TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SETns_noc_io_pcie_soc_ip.csr19278RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr19289MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19296UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19413main0_dbg_m register am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x8500R/W0x0000007e80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr19337P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr19348NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr19359I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr19371R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr19382DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr19394LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr19405BASE_ADDRESS_0_33Base address3960x1fa000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19412UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19505main0_dbg_m register am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x8508R/W0x000000ff80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr19430P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr19441NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr19452I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr19463VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr19475TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr19486RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr19497MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19504UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19546main0_dbg_m register am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x8510R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr19523UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr19534SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr19545UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19662main0_dbg_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00x8520R/W0x0000004000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr19586P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr19597NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr19608I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr19620R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr19631DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr19643LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr19654BASE_ADDRESS_0_33Base address3960x100000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19661UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19754main0_dbg_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00x8528R/W0x000000e000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr19679P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr19690NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr19701I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr19712VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr19724TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr19735RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr19746MASK_0_33Mask3960x380000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19753UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19870main0_dbg_m register am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x8540R/W0x0000007f00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr19794P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr19805NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr19816I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr19828R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr19839DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr19851LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr19862BASE_ADDRESS_0_33Base address3960x1fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19869UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr19962main0_dbg_m register am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x8548R/W0x000000ff80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr19887P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr19898NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr19909I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr19920VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr19932TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr19943RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr19954MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr19961UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20003main0_dbg_m register am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x8550R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr19980UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr19991SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr20002UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20119main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00x8560R/W0x0000006000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr20043P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr20054NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr20065I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr20077R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr20088DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr20100LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr20111BASE_ADDRESS_0_33Base address3960x180000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20118UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20211main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00x8568R/W0x000000f000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr20136P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr20147NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr20158I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr20169VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr20181TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr20192RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr20203MASK_0_33Mask3960x3c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20210UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20327main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00x8580R/W0x0000007000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr20251P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr20262NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr20273I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr20285R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SETns_noc_io_pcie_soc_ip.csr20296DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr20308LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr20319BASE_ADDRESS_0_33Base address3960x1c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20326UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20419main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00x8588R/W0x000000f800000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr20344P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr20355NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr20366I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr20377VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SETns_noc_io_pcie_soc_ip.csr20389TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr20400RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr20411MASK_0_33Mask3960x3e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20418UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20535main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00x85A0R/W0x0000007800000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr20459P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr20470NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr20481I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr20493R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SETns_noc_io_pcie_soc_ip.csr20504DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr20516LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr20527BASE_ADDRESS_0_33Base address3960x1e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20534UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20627main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00x85A8R/W0x000000fc00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr20552P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr20563NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr20574I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr20585VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SETns_noc_io_pcie_soc_ip.csr20597TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr20608RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr20619MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20626UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20743main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00x85C0R/W0x0000007c00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr20667P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr20678NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr20689I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr20701R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SETns_noc_io_pcie_soc_ip.csr20712DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr20724LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr20735BASE_ADDRESS_0_33Base address3960x1f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20742UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20835main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00x85C8R/W0x000000fe00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr20760P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr20771NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr20782I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr20793VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SETns_noc_io_pcie_soc_ip.csr20805TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr20816RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr20827MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20834UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr20951main0_dbg_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00x85E0R/W0x0000007e00000000Pcie_noc_bridge_main0_dbg_m_0_9_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr20875P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr20886NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr20897I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr20909R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SETns_noc_io_pcie_soc_ip.csr20920DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr20932LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr20943BASE_ADDRESS_0_33Base address3960x1f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr20950UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21043main0_dbg_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00x85E8R/W0x000000ff80000000Pcie_noc_bridge_main0_dbg_m_0_9_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr20968P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr20979NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr20990I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr21001VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SETns_noc_io_pcie_soc_ip.csr21013TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr21024RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr21035MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr21042UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_p_0bridge_main0_dbg_m_0_9_p_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21108main0_dbg_m register p_00xB000R/W0x00000003Pcie_noc_bridge_main0_dbg_m_0_9_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr21071WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr21083WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr21095WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr21107WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_p_1bridge_main0_dbg_m_0_9_p_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21174main0_dbg_m register p_10xB008R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr21137WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr21149WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr21161WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr21173WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_p_2bridge_main0_dbg_m_0_9_p_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21240main0_dbg_m register p_20xB010R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr21203WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr21215WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr21227WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr21239WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_p_3bridge_main0_dbg_m_0_9_p_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21306main0_dbg_m register p_30xB018R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr21269WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr21281WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr21293WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr21305WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_txebridge_main0_dbg_m_0_9_txePCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21452main0_dbg_m register txe0xB040R/W0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr21333TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr21345SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr21360TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr21373EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr21387FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr21401FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr21415FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr21429FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr21440PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr21451UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_txembridge_main0_dbg_m_0_9_txemPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21531main0_dbg_m register txem0xB048R/W0x00000008Pcie_noc_bridge_main0_dbg_m_0_9_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr21475UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr21486TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr21497EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr21508UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr21519PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr21530UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btus_0bridge_main0_dbg_m_0_9_btus_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr21899main0_dbg_m register btus_00xB058R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr21557L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr21568L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr21579L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr21590L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr21601L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr21612L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr21623L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr21634L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr21645L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr21656L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr21667L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr21678L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr21689L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr21700L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr21711L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr21722L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr21733L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr21744L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr21755L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr21766L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr21777L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr21788L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr21799L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr21810L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr21821L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr21832L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr21843L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr21854L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr21865L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr21876L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr21887L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr21898L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btus_1bridge_main0_dbg_m_0_9_btus_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22267main0_dbg_m register btus_10xB060R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr21925L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr21936L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr21947L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr21958L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr21969L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr21980L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr21991L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr22002L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr22013L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr22024L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr22035L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr22046L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr22057L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr22068L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr22079L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr22090L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr22101L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr22112L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr22123L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr22134L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr22145L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr22156L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr22167L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr22178L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr22189L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr22200L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr22211L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr22222L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr22233L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr22244L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr22255L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr22266L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btrl_0bridge_main0_dbg_m_0_9_btrl_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22343main0_dbg_m register btrl_00xB080R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr22291WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr22302RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr22317CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr22331EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr22342UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btrl_1bridge_main0_dbg_m_0_9_btrl_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22419main0_dbg_m register btrl_10xB088R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr22367WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr22378RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr22393CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr22407EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr22418UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btrl_2bridge_main0_dbg_m_0_9_btrl_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22495main0_dbg_m register btrl_20xB090R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr22443WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr22454RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr22469CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr22483EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr22494UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btrl_3bridge_main0_dbg_m_0_9_btrl_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22571main0_dbg_m register btrl_30xB098R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr22519WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr22530RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr22545CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr22559EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr22570UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btperrbridge_main0_dbg_m_0_9_btperrPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22773main0_dbg_m register btperr0xB0A8R/W0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr22596L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr22607L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr22618L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr22629L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr22640L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr22651L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr22662L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr22673L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr22684L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr22695L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr22706L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr22717L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr22728L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr22739L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr22750L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr22761L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr22772UNSD31160x0000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_btperrmbridge_main0_dbg_m_0_9_btperrmPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr22973main0_dbg_m register btperrm0xB0B0R/W0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr22796L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr22807L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr22818L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr22829L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr22840L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr22851L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr22862L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr22873L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr22884L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr22895L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr22906L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr22917L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr22928L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr22939L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr22950L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr22961L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr22972UNSD31160x0000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_rxebridge_main0_dbg_m_0_9_rxePCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr23081main0_dbg_m register rxe0xB120R/W0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr23001CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr23012CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr23023CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr23034CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr23046EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr23057PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr23069EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr23080UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_rxembridge_main0_dbg_m_0_9_rxemPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr23153main0_dbg_m register rxem0xB128R/W0x00000050Pcie_noc_bridge_main0_dbg_m_0_9_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr23102UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr23116EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr23127PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr23141EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr23152UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brs_0bridge_main0_dbg_m_0_9_brs_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr23427main0_dbg_m register brs_00xB130R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr23177OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr23188V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr23199S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr23210B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr23221F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr23231UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr23242OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr23253V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr23264S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr23275B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr23286F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr23296UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr23307OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr23318V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr23329S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr23340B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr23351F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr23361UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr23372OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr23383V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr23394S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr23405B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr23416F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr23426UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brs_1bridge_main0_dbg_m_0_9_brs_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr23701main0_dbg_m register brs_10xB138R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr23451OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr23462V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr23473S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr23484B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr23495F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr23505UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr23516OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr23527V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr23538S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr23549B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr23560F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr23570UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr23581OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr23592V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr23603S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr23614B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr23625F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr23635UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr23646OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr23657V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr23668S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr23679B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr23690F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr23700UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brusbridge_main0_dbg_m_0_9_brusPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr23770main0_dbg_m register brus0xB1B0R0x00000000Pcie_noc_bridge_main0_dbg_m_0_9_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr23726V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr23737V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr23748V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr23759V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr23769UNSD_31_43140x0000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brperr0bridge_main0_dbg_m_0_9_brperr0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr23998main0_dbg_m register brperr00xB1D0R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr23808D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr23819DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr23830SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr23842SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr23853PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr23864UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr23875D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr23886DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr23897SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr23909SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr23920PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr23931UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr23942UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr23953UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr23964UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr23975UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr23986UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr23997UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brperr1bridge_main0_dbg_m_0_9_brperr1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24114main0_dbg_m register brperr10xB1D8R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr24036UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr24047UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr24058UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr24069UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr24080UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr24091UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr24102UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr24113UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brperrm0bridge_main0_dbg_m_0_9_brperrm0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24335main0_dbg_m register brperrm00xB1E0R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr24141D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr24153DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr24164SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr24176SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr24188PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr24199UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr24210D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr24222DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr24233SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr24245SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr24257PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr24268UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr24279UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr24290UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr24301UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr24312UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr24323UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr24334UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_brperrm1bridge_main0_dbg_m_0_9_brperrm1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24440main0_dbg_m register brperrm10xB1E8R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr24362UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr24373UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr24384UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr24395UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr24406UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr24417UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr24428UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr24439UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_tocfgbridge_main0_dbg_m_0_9_am_tocfgPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24514main0_dbg_m register am_tocfg0xBC00R/W0x000000000000001fPcie_noc_bridge_main0_dbg_m_0_9_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr24477TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr24488UNSD_7_6760x0RENPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr24502EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr24513UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_osslvbridge_main0_dbg_m_0_9_am_osslvPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24549main0_dbg_m register am_osslv0xBC08R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr24537SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr24548UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_cgcbridge_main0_dbg_m_0_9_am_cgcPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24586main0_dbg_m register am_cgc0xBC10R/W0x0000000000000064Pcie_noc_bridge_main0_dbg_m_0_9_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr24574HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr24585UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_cgobridge_main0_dbg_m_0_9_am_cgoPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24621main0_dbg_m register am_cgo0xBC18R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr24609FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr24620UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_cfgbridge_main0_dbg_m_0_9_am_cfgPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24658main0_dbg_m register am_cfg0xBC20R/W0x0000000000000001Pcie_noc_bridge_main0_dbg_m_0_9_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr24646AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr24657UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_stsbridge_main0_dbg_m_0_9_am_stsPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24786main0_dbg_m register am_sts0xBD00R0x000000000000000cPcie_noc_bridge_main0_dbg_m_0_9_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr24691ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr24705WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr24717ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr24729WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr24740ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr24751AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr24763ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr24775AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr24785UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_bridge_idbridge_main0_dbg_m_0_9_am_bridge_idPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr24816main0_dbg_m register am_bridge_id0xBD08R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr24805IDUnique bridge ID1500x0000RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr24815UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_errbridge_main0_dbg_m_0_9_am_errPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25312main0_dbg_m register am_err0xBE00R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr24838E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr24850E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr24862E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr24874E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr24886E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr24898E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr24911E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr24924E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr24935E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr24946UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr24957E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr24968E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr24979E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr24990E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr25001E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr25012E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr25023E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr25035E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr25046E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr25057UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr25068E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr25079E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr25091E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr25103E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr25114UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr25126E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr25137E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr25148E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr25159E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr25170E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr25181E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr25192E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr25204E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr25216E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr25228E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr25240E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr25252E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr25264E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr25276E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr25288E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr25300E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr25311UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_toslvidbridge_main0_dbg_m_0_9_am_toslvidPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25357main0_dbg_m register am_toslvid0xBE08R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr25335AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr25346AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr25356UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_erabridge_main0_dbg_m_0_9_am_eraPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25379main0_dbg_m register am_era0xBE10R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr25378READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_ewabridge_main0_dbg_m_0_9_am_ewaPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25401main0_dbg_m register am_ewa0xBE18R0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr25400WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_intmbridge_main0_dbg_m_0_9_am_intmPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25885main0_dbg_m register am_intm0xBE40R/W0x00007e07004f004fPcie_noc_bridge_main0_dbg_m_0_9_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr25423M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr25434M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr25445M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr25456M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr25467M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr25478M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr25489M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr25500M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr25511M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr25522UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr25533M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr25544M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr25555M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr25566M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr25577M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr25588M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr25599M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr25610M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr25621M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr25632UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr25643M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr25654M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr25665M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr25676M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr25687UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr25699M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr25710M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr25721M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr25732M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr25743M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr25754M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr25765M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr25777E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr25789E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr25801E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr25813E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr25825E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr25837E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr25849E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr25861E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr25873E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr25884UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_caddrbridge_main0_dbg_m_0_9_am_caddrPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25907main0_dbg_m register am_caddr0xBF00R/W0xffffffffffffffffPcie_noc_bridge_main0_dbg_m_0_9_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr25906CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_main0_dbg_m_0_9_am_caddrmskbridge_main0_dbg_m_0_9_am_caddrmskPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr25930main0_dbg_m register am_caddrmsk0xBF08R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr25929CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_main0_dbg_m_0_9_am_ccmd0bridge_main0_dbg_m_0_9_am_ccmd0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26120main0_dbg_m register am_ccmd00xBF10R/W0x0000000003fff33fPcie_noc_bridge_main0_dbg_m_0_9_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr25952SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr25963DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr25974UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr25985BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr25996UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr26007CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr26018QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr26029PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr26040LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr26051RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr26062VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr26073UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr26085INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr26096UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr26108TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr26119UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk0bridge_main0_dbg_m_0_9_am_ccmdmsk0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26264main0_dbg_m register am_ccmdmsk00xBF18R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr26142SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr26153DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr26164UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr26175BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr26186UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr26197CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr26208QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr26219PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr26230LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr26241RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr26252VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr26263UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_cntr0bridge_main0_dbg_m_0_9_am_cntr0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26299main0_dbg_m register am_cntr00xBF20R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr26287CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr26298UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_latnum0bridge_main0_dbg_m_0_9_am_latnum0PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26338main0_dbg_m register am_latnum00xBF28R/W0x0000000000000007Pcie_noc_bridge_main0_dbg_m_0_9_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr26326CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr26337UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_ccmd1bridge_main0_dbg_m_0_9_am_ccmd1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26528main0_dbg_m register am_ccmd10xBF30R/W0x0000000003fff33fPcie_noc_bridge_main0_dbg_m_0_9_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr26360SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr26371DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr26382UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr26393BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr26404UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr26415CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr26426QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr26437PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr26448LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr26459RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr26470VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr26481UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr26493INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr26504UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr26516TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr26527UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_ccmdmsk1bridge_main0_dbg_m_0_9_am_ccmdmsk1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26672main0_dbg_m register am_ccmdmsk10xBF38R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr26550SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr26561DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr26572UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr26583BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr26594UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr26605CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr26616QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr26627PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr26638LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr26649RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr26660VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr26671UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_cntr1bridge_main0_dbg_m_0_9_am_cntr1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26707main0_dbg_m register am_cntr10xBF40R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr26695CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr26706UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_latnum1bridge_main0_dbg_m_0_9_am_latnum1PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26746main0_dbg_m register am_latnum10xBF48R/W0x0000000000000007Pcie_noc_bridge_main0_dbg_m_0_9_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr26734CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr26745UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_arovrdbridge_main0_dbg_m_0_9_am_arovrdPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26859main0_dbg_m register am_arovrd0xBF60R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr26764arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr26777arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr26788arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr26799UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr26812arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr26823UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr26834arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr26847arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr26858UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_dbg_m_0_9_am_awovrdbridge_main0_dbg_m_0_9_am_awovrdPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr26972main0_dbg_m register am_awovrd0xBF68R/W0x0000000000000000Pcie_noc_bridge_main0_dbg_m_0_9_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr26877awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr26890awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr26901awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr26912UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr26925awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr26936UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr26947awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr26960awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_DBG_M_0_9_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr26971UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27088main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00xC000R/W0x0000000080000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr27012P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr27023NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr27034I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr27046R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr27057DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr27069LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr27080BASE_ADDRESS_0_33Base address3960x002000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27087UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27180main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00xC008R/W0x000000ff80000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr27105P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr27116NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr27127I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr27138VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr27150TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr27161RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr27172MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27179UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27296main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00xC020R/W0x0000008000200000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr27220P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr27231NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr27242I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr27254R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SETns_noc_io_pcie_soc_ip.csr27265DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr27277LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr27288BASE_ADDRESS_0_33Base address3960x200008000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27295UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27388main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00xC028R/W0x000000ffffe00000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr27313P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr27324NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr27335I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr27346VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SETns_noc_io_pcie_soc_ip.csr27358TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr27369RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr27380MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27387UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27504main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00xC040R/W0x0000008000400000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr27428P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr27439NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr27450I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr27462R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SETns_noc_io_pcie_soc_ip.csr27473DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr27485LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr27496BASE_ADDRESS_0_33Base address3960x200010000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27503UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27596main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00xC048R/W0x000000ffffc00000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr27521P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr27532NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr27543I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr27554VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SETns_noc_io_pcie_soc_ip.csr27566TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr27577RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr27588MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27595UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27712main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00xC060R/W0x0000008000800000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr27636P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr27647NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr27658I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr27670R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SETns_noc_io_pcie_soc_ip.csr27681DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr27693LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr27704BASE_ADDRESS_0_33Base address3960x200020000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27711UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27804main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00xC068R/W0x000000ffff800000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr27729P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr27740NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr27751I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr27762VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SETns_noc_io_pcie_soc_ip.csr27774TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr27785RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr27796MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27803UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr27920main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00xC080R/W0x0000008001000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr27844P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr27855NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr27866I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr27878R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SETns_noc_io_pcie_soc_ip.csr27889DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr27901LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr27912BASE_ADDRESS_0_33Base address3960x200040000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr27919UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28012main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00xC088R/W0x000000ffff000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr27937P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr27948NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr27959I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr27970VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SETns_noc_io_pcie_soc_ip.csr27982TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr27993RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr28004MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28011UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28128main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00xC0A0R/W0x0000008002000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr28052P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr28063NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr28074I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr28086R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SETns_noc_io_pcie_soc_ip.csr28097DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr28109LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr28120BASE_ADDRESS_0_33Base address3960x200080000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28127UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28220main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00xC0A8R/W0x000000fffe000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr28145P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr28156NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr28167I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr28178VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SETns_noc_io_pcie_soc_ip.csr28190TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr28201RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr28212MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28219UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28336main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00xC0C0R/W0x0000008004000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr28260P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr28271NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr28282I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr28294R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr28305DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr28317LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr28328BASE_ADDRESS_0_33Base address3960x200100000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28335UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28428main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00xC0C8R/W0x000000fffc000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr28353P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr28364NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr28375I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr28386VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr28398TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr28409RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr28420MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28427UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28544main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00xC0E0R/W0x0000008008000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr28468P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr28479NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr28490I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr28502R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr28513DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr28525LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr28536BASE_ADDRESS_0_33Base address3960x200200000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28543UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28636main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00xC0E8R/W0x000000fff8000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr28561P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr28572NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr28583I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr28594VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr28606TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr28617RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr28628MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28635UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28752main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00xC100R/W0x0000008010000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr28676P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr28687NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr28698I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr28710R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr28721DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr28733LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr28744BASE_ADDRESS_0_33Base address3960x200400000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28751UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28844main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00xC108R/W0x000000fff0000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr28769P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr28780NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr28791I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr28802VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr28814TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr28825RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr28836MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28843UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr28960main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00xC120R/W0x0000008020000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr28884P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr28895NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr28906I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr28918R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr28929DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr28941LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr28952BASE_ADDRESS_0_33Base address3960x200800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr28959UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29052main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00xC128R/W0x000000ffe0000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr28977P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr28988NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr28999I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr29010VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr29022TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr29033RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr29044MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29051UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29168main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00xC140R/W0x0000008040000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr29092P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr29103NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr29114I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr29126R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SETns_noc_io_pcie_soc_ip.csr29137DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr29149LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr29160BASE_ADDRESS_0_33Base address3960x201000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29167UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29260main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00xC148R/W0x000000ffc0000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr29185P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr29196NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr29207I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr29218VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SETns_noc_io_pcie_soc_ip.csr29230TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr29241RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr29252MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29259UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29376main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00xC160R/W0x0000008080000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr29300P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr29311NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr29322I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr29334R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SETns_noc_io_pcie_soc_ip.csr29345DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr29357LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr29368BASE_ADDRESS_0_33Base address3960x202000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29375UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29468main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00xC168R/W0x000000ff80000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr29393P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr29404NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr29415I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr29426VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SETns_noc_io_pcie_soc_ip.csr29438TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr29449RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr29460MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29467UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29584main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00xC180R/W0x0000008100000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr29508P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr29519NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr29530I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr29542R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SETns_noc_io_pcie_soc_ip.csr29553DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr29565LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr29576BASE_ADDRESS_0_33Base address3960x204000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29583UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29676main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00xC188R/W0x000000ff00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr29601P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr29612NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr29623I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr29634VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SETns_noc_io_pcie_soc_ip.csr29646TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr29657RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr29668MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29675UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29792main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00xC1A0R/W0x0000008200000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr29716P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr29727NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr29738I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr29750R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SETns_noc_io_pcie_soc_ip.csr29761DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr29773LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr29784BASE_ADDRESS_0_33Base address3960x208000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29791UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr29884main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00xC1A8R/W0x000000fe00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr29809P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr29820NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr29831I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr29842VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SETns_noc_io_pcie_soc_ip.csr29854TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr29865RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr29876MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29883UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30000main0_esr_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00xC1C0R/W0x0000008400000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr29924P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr29935NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr29946I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr29958R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SETns_noc_io_pcie_soc_ip.csr29969DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr29981LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr29992BASE_ADDRESS_0_33Base address3960x210000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr29999UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30092main0_esr_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00xC1C8R/W0x000000fc00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr30017P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr30028NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr30039I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr30050VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SETns_noc_io_pcie_soc_ip.csr30062TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr30073RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr30084MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30091UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30208main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00xC1E0R/W0x0000000002000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr30132P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr30143NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr30154I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr30166R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr30177DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr30189LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr30200BASE_ADDRESS_0_33Base address3960x000080000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30207UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30300main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00xC1E8R/W0x000000ffffff0000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr30225P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr30236NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr30247I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr30258VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr30270TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr30281RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr30292MASK_0_33Mask3960x3fffffc00R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30299UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30416main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00xC200R/W0x0000000020007000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr30340P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr30351NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr30362I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr30374R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr30385DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr30397LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr30408BASE_ADDRESS_0_33Base address3960x0008001c0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30415UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30508main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00xC208R/W0x000000fffffff000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr30433P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr30444NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr30455I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr30466VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr30478TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr30489RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr30500MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30507UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30624main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00xC220R/W0x0000000030001000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr30548P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr30559NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr30570I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr30582R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr30593DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr30605LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr30616BASE_ADDRESS_0_33Base address3960x000c00040R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30623UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30716main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00xC228R/W0x000000fffffff000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr30641P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr30652NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr30663I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr30674VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr30686TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr30697RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr30708MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30715UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30832main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00xC240R/W0x0000000030003000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr30756P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr30767NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr30778I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr30790R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SETns_noc_io_pcie_soc_ip.csr30801DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr30813LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr30824BASE_ADDRESS_0_33Base address3960x000c000c0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30831UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr30924main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00xC248R/W0x000000fffffff000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr30849P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr30860NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr30871I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr30882VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SETns_noc_io_pcie_soc_ip.csr30894TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr30905RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr30916MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr30923UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31040main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00xC260R/W0x0000000030008000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr30964P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr30975NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr30986I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr30998R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SETns_noc_io_pcie_soc_ip.csr31009DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr31021LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr31032BASE_ADDRESS_0_33Base address3960x000c00200R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31039UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31132main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00xC268R/W0x000000ffffffe000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr31057P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr31068NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr31079I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr31090VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SETns_noc_io_pcie_soc_ip.csr31102TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr31113RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr31124MASK_0_33Mask3960x3ffffff80R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31131UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31248main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00xC280R/W0x0000000100000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr31172P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr31183NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr31194I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr31206R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SETns_noc_io_pcie_soc_ip.csr31217DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr31229LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr31240BASE_ADDRESS_0_33Base address3960x004000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31247UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31340main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00xC288R/W0x000000ff00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr31265P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr31276NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr31287I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr31298VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SETns_noc_io_pcie_soc_ip.csr31310TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr31321RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr31332MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31339UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31456main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00xC2A0R/W0x000000c000200010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr31380P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr31391NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr31402I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr31414R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr31425DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr31437LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr31448BASE_ADDRESS_0_33Base address3960x300008000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31455UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31548main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00xC2A8R/W0x000000ffffe00000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr31473P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr31484NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr31495I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr31506VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr31518TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr31529RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr31540MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31547UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31664main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00xC2C0R/W0x000000c000400010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr31588P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr31599NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr31610I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr31622R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr31633DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr31645LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr31656BASE_ADDRESS_0_33Base address3960x300010000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31663UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31756main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00xC2C8R/W0x000000ffffc00000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr31681P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr31692NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr31703I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr31714VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr31726TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr31737RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr31748MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31755UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31872main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00xC2E0R/W0x000000c000800010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr31796P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr31807NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr31818I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr31830R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr31841DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr31853LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr31864BASE_ADDRESS_0_33Base address3960x300020000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31871UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr31964main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00xC2E8R/W0x000000ffff800000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr31889P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr31900NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr31911I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr31922VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr31934TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr31945RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr31956MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr31963UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32080main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00xC300R/W0x000000c001000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr32004P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr32015NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr32026I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr32038R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr32049DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr32061LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr32072BASE_ADDRESS_0_33Base address3960x300040000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32079UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32172main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00xC308R/W0x000000ffff000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr32097P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr32108NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr32119I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr32130VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr32142TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr32153RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr32164MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32171UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32288main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00xC320R/W0x000000c002000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr32212P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr32223NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr32234I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr32246R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SETns_noc_io_pcie_soc_ip.csr32257DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr32269LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr32280BASE_ADDRESS_0_33Base address3960x300080000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32287UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32380main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00xC328R/W0x000000fffe000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr32305P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr32316NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr32327I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr32338VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SETns_noc_io_pcie_soc_ip.csr32350TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr32361RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr32372MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32379UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32496main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00xC340R/W0x000000c004000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr32420P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr32431NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr32442I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr32454R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SETns_noc_io_pcie_soc_ip.csr32465DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr32477LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr32488BASE_ADDRESS_0_33Base address3960x300100000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32495UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32588main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00xC348R/W0x000000fffc000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr32513P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr32524NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr32535I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr32546VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SETns_noc_io_pcie_soc_ip.csr32558TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr32569RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr32580MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32587UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32704main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00xC360R/W0x000000c008000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr32628P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr32639NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr32650I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr32662R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SETns_noc_io_pcie_soc_ip.csr32673DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr32685LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr32696BASE_ADDRESS_0_33Base address3960x300200000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32703UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32796main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00xC368R/W0x000000fff8000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr32721P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr32732NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr32743I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr32754VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SETns_noc_io_pcie_soc_ip.csr32766TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr32777RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr32788MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32795UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr32912main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00xC380R/W0x000000c010000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr32836P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr32847NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr32858I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr32870R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SETns_noc_io_pcie_soc_ip.csr32881DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr32893LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr32904BASE_ADDRESS_0_33Base address3960x300400000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr32911UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33004main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00xC388R/W0x000000fff0000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr32929P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr32940NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr32951I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr32962VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SETns_noc_io_pcie_soc_ip.csr32974TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr32985RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr32996MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33003UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33120main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00xC3A0R/W0x000000c020000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr33044P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr33055NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr33066I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr33078R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SETns_noc_io_pcie_soc_ip.csr33089DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr33101LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr33112BASE_ADDRESS_0_33Base address3960x300800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33119UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33212main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00xC3A8R/W0x000000ffe0000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr33137P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr33148NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr33159I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr33170VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SETns_noc_io_pcie_soc_ip.csr33182TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr33193RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr33204MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33211UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33328main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00xC3C0R/W0x000000c040000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr33252P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr33263NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr33274I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SETns_noc_io_pcie_soc_ip.csr33286R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SETns_noc_io_pcie_soc_ip.csr33297DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SETns_noc_io_pcie_soc_ip.csr33309LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr33320BASE_ADDRESS_0_33Base address3960x301000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33327UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33420main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00xC3C8R/W0x000000ffc0000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr33345P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr33356NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr33367I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SETns_noc_io_pcie_soc_ip.csr33378VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SETns_noc_io_pcie_soc_ip.csr33390TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SETns_noc_io_pcie_soc_ip.csr33401RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr33412MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33419UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33536main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00xC3E0R/W0x000000c080000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr33460P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr33471NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr33482I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SETns_noc_io_pcie_soc_ip.csr33494R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SETns_noc_io_pcie_soc_ip.csr33505DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SETns_noc_io_pcie_soc_ip.csr33517LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr33528BASE_ADDRESS_0_33Base address3960x302000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33535UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33628main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00xC3E8R/W0x000000ff80000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr33553P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr33564NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr33575I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SETns_noc_io_pcie_soc_ip.csr33586VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SETns_noc_io_pcie_soc_ip.csr33598TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SETns_noc_io_pcie_soc_ip.csr33609RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr33620MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33627UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33744main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00xC400R/W0x000000c100000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr33668P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr33679NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr33690I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SETns_noc_io_pcie_soc_ip.csr33702R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SETns_noc_io_pcie_soc_ip.csr33713DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SETns_noc_io_pcie_soc_ip.csr33725LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr33736BASE_ADDRESS_0_33Base address3960x304000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33743UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33836main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00xC408R/W0x000000ff00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr33761P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr33772NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr33783I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SETns_noc_io_pcie_soc_ip.csr33794VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SETns_noc_io_pcie_soc_ip.csr33806TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SETns_noc_io_pcie_soc_ip.csr33817RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr33828MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33835UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr33952main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00xC420R/W0x000000c200000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr33876P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr33887NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr33898I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SETns_noc_io_pcie_soc_ip.csr33910R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SETns_noc_io_pcie_soc_ip.csr33921DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SETns_noc_io_pcie_soc_ip.csr33933LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr33944BASE_ADDRESS_0_33Base address3960x308000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr33951UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34044main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00xC428R/W0x000000fe00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr33969P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr33980NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr33991I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SETns_noc_io_pcie_soc_ip.csr34002VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SETns_noc_io_pcie_soc_ip.csr34014TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SETns_noc_io_pcie_soc_ip.csr34025RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr34036MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34043UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34160main0_esr_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00xC440R/W0x000000c400000010Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr34084P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr34095NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr34106I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SETns_noc_io_pcie_soc_ip.csr34118R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SETns_noc_io_pcie_soc_ip.csr34129DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SETns_noc_io_pcie_soc_ip.csr34141LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr34152BASE_ADDRESS_0_33Base address3960x310000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34159UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34252main0_esr_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00xC448R/W0x000000fc00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr34177P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr34188NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr34199I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SETns_noc_io_pcie_soc_ip.csr34210VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SETns_noc_io_pcie_soc_ip.csr34222TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SETns_noc_io_pcie_soc_ip.csr34233RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr34244MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34251UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34368main0_esr_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00xC460R/W0x0000004000000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr34292P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr34303NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr34314I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr34326R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr34337DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr34349LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr34360BASE_ADDRESS_0_33Base address3960x100000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34367UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34460main0_esr_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00xC468R/W0x000000e000000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr34385P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr34396NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr34407I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr34418VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr34430TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr34441RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr34452MASK_0_33Mask3960x380000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34459UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34576main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00xC480R/W0x0000006000000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr34500P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr34511NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr34522I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr34534R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr34545DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr34557LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr34568BASE_ADDRESS_0_33Base address3960x180000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34575UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34668main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00xC488R/W0x000000f000000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr34593P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr34604NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr34615I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr34626VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr34638TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr34649RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr34660MASK_0_33Mask3960x3c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34667UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34784main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00xC4A0R/W0x0000007000000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr34708P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr34719NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr34730I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr34742R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SETns_noc_io_pcie_soc_ip.csr34753DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr34765LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr34776BASE_ADDRESS_0_33Base address3960x1c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34783UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34876main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00xC4A8R/W0x000000f800000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr34801P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr34812NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr34823I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr34834VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SETns_noc_io_pcie_soc_ip.csr34846TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr34857RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr34868MASK_0_33Mask3960x3e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34875UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr34992main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00xC4C0R/W0x0000007800000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr34916P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr34927NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr34938I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr34950R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SETns_noc_io_pcie_soc_ip.csr34961DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr34973LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr34984BASE_ADDRESS_0_33Base address3960x1e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr34991UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35084main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00xC4C8R/W0x000000fc00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr35009P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr35020NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr35031I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr35042VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SETns_noc_io_pcie_soc_ip.csr35054TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr35065RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr35076MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr35083UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35200main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00xC4E0R/W0x0000007c00000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr35124P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr35135NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr35146I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr35158R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SETns_noc_io_pcie_soc_ip.csr35169DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr35181LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr35192BASE_ADDRESS_0_33Base address3960x1f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr35199UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35292main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00xC4E8R/W0x000000fe00000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr35217P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr35228NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr35239I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr35250VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SETns_noc_io_pcie_soc_ip.csr35262TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr35273RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr35284MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr35291UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35408main0_esr_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00xC500R/W0x0000007e00000000Pcie_noc_bridge_main0_esr_m_1_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr35332P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr35343NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr35354I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr35366R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SETns_noc_io_pcie_soc_ip.csr35377DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr35389LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr35400BASE_ADDRESS_0_33Base address3960x1f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr35407UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35500main0_esr_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00xC508R/W0x000000ff80000000Pcie_noc_bridge_main0_esr_m_1_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr35425P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr35436NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr35447I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr35458VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SETns_noc_io_pcie_soc_ip.csr35470TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr35481RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr35492MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr35499UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_p_0bridge_main0_esr_m_1_5_p_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35565main0_esr_m register p_00xF000R/W0x00000003Pcie_noc_bridge_main0_esr_m_1_5_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr35528WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr35540WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr35552WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr35564WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_p_1bridge_main0_esr_m_1_5_p_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35631main0_esr_m register p_10xF008R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr35594WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr35606WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr35618WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr35630WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_p_2bridge_main0_esr_m_1_5_p_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35697main0_esr_m register p_20xF010R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr35660WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr35672WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr35684WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr35696WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_p_3bridge_main0_esr_m_1_5_p_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35763main0_esr_m register p_30xF018R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr35726WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr35738WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr35750WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr35762WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_txebridge_main0_esr_m_1_5_txePCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35909main0_esr_m register txe0xF040R/W0x00000000Pcie_noc_bridge_main0_esr_m_1_5_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr35790TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr35802SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr35817TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr35830EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr35844FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr35858FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr35872FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr35886FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr35897PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr35908UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_txembridge_main0_esr_m_1_5_txemPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr35988main0_esr_m register txem0xF048R/W0x00000008Pcie_noc_bridge_main0_esr_m_1_5_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr35932UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr35943TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr35954EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr35965UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr35976PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr35987UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_btus_0bridge_main0_esr_m_1_5_btus_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr36356main0_esr_m register btus_00xF058R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr36014L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr36025L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr36036L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr36047L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr36058L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr36069L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr36080L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr36091L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr36102L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr36113L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr36124L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr36135L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr36146L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr36157L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr36168L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr36179L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr36190L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr36201L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr36212L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr36223L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr36234L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr36245L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr36256L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr36267L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr36278L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr36289L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr36300L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr36311L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr36322L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr36333L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr36344L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr36355L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_main0_esr_m_1_5_btus_1bridge_main0_esr_m_1_5_btus_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr36724main0_esr_m register btus_10xF060R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr36382L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr36393L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr36404L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr36415L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr36426L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr36437L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr36448L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr36459L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr36470L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr36481L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr36492L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr36503L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr36514L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr36525L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr36536L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr36547L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr36558L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr36569L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr36580L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr36591L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr36602L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr36613L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr36624L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr36635L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr36646L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr36657L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr36668L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr36679L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr36690L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr36701L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr36712L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr36723L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_main0_esr_m_1_5_btrl_0bridge_main0_esr_m_1_5_btrl_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr36800main0_esr_m register btrl_00xF080R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr36748WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr36759RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr36774CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr36788EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr36799UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_esr_m_1_5_btrl_1bridge_main0_esr_m_1_5_btrl_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr36876main0_esr_m register btrl_10xF088R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr36824WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr36835RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr36850CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr36864EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr36875UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_esr_m_1_5_btrl_2bridge_main0_esr_m_1_5_btrl_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr36952main0_esr_m register btrl_20xF090R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr36900WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr36911RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr36926CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr36940EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr36951UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_esr_m_1_5_btrl_3bridge_main0_esr_m_1_5_btrl_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr37028main0_esr_m register btrl_30xF098R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr36976WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr36987RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr37002CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr37016EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr37027UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_esr_m_1_5_btperrbridge_main0_esr_m_1_5_btperrPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr37230main0_esr_m register btperr0xF0A8R/W0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr37053L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr37064L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr37075L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr37086L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr37097L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr37108L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr37119L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr37130L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr37141L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr37152L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr37163L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr37174L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr37185L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr37196L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr37207L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr37218L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr37229UNSD31160x0000Rregisterpcie_noc.bridge_main0_esr_m_1_5_btperrmbridge_main0_esr_m_1_5_btperrmPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr37430main0_esr_m register btperrm0xF0B0R/W0x00000000Pcie_noc_bridge_main0_esr_m_1_5_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr37253L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr37264L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr37275L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr37286L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr37297L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr37308L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr37319L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr37330L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr37341L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr37352L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr37363L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr37374L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr37385L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr37396L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr37407L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr37418L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr37429UNSD31160x0000Rregisterpcie_noc.bridge_main0_esr_m_1_5_rxebridge_main0_esr_m_1_5_rxePCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr37538main0_esr_m register rxe0xF120R/W0x00000000Pcie_noc_bridge_main0_esr_m_1_5_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr37458CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr37469CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr37480CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr37491CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr37503EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr37514PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr37526EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr37537UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_rxembridge_main0_esr_m_1_5_rxemPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr37610main0_esr_m register rxem0xF128R/W0x00000050Pcie_noc_bridge_main0_esr_m_1_5_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr37559UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr37573EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr37584PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr37598EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr37609UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_brs_0bridge_main0_esr_m_1_5_brs_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr37884main0_esr_m register brs_00xF130R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr37634OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr37645V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr37656S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr37667B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr37678F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr37688UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr37699OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr37710V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr37721S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr37732B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr37743F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr37753UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr37764OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr37775V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr37786S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr37797B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr37808F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr37818UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr37829OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr37840V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr37851S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr37862B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr37873F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr37883UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_esr_m_1_5_brs_1bridge_main0_esr_m_1_5_brs_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38158main0_esr_m register brs_10xF138R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr37908OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr37919V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr37930S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr37941B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr37952F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr37962UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr37973OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr37984V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr37995S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr38006B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr38017F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr38027UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr38038OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr38049V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr38060S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr38071B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr38082F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr38092UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr38103OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr38114V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr38125S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr38136B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr38147F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr38157UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_esr_m_1_5_brusbridge_main0_esr_m_1_5_brusPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38227main0_esr_m register brus0xF1B0R0x00000000Pcie_noc_bridge_main0_esr_m_1_5_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr38183V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr38194V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr38205V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr38216V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr38226UNSD_31_43140x0000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_brperr0bridge_main0_esr_m_1_5_brperr0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38455main0_esr_m register brperr00xF1D0R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr38265D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr38276DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr38287SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr38299SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr38310PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr38321UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr38332D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr38343DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr38354SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr38366SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr38377PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr38388UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr38399UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr38410UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr38421UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr38432UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr38443UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr38454UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_brperr1bridge_main0_esr_m_1_5_brperr1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38571main0_esr_m register brperr10xF1D8R0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr38493UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr38504UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr38515UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr38526UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr38537UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr38548UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr38559UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr38570UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_brperrm0bridge_main0_esr_m_1_5_brperrm0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38792main0_esr_m register brperrm00xF1E0R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr38598D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr38610DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr38621SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr38633SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr38645PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr38656UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr38667D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr38679DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr38690SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr38702SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr38714PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr38725UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr38736UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr38747UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr38758UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr38769UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr38780UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr38791UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_brperrm1bridge_main0_esr_m_1_5_brperrm1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38897main0_esr_m register brperrm10xF1E8R0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr38819UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr38830UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr38841UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr38852UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr38863UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr38874UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr38885UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr38896UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_tocfgbridge_main0_esr_m_1_5_am_tocfgPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr38971main0_esr_m register am_tocfg0xFC00R/W0x000000000000001fPcie_noc_bridge_main0_esr_m_1_5_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr38934TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr38945UNSD_7_6760x0RENPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr38959EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr38970UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_osslvbridge_main0_esr_m_1_5_am_osslvPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39006main0_esr_m register am_osslv0xFC08R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr38994SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr39005UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_cgcbridge_main0_esr_m_1_5_am_cgcPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39043main0_esr_m register am_cgc0xFC10R/W0x0000000000000064Pcie_noc_bridge_main0_esr_m_1_5_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr39031HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr39042UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_cgobridge_main0_esr_m_1_5_am_cgoPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39078main0_esr_m register am_cgo0xFC18R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr39066FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr39077UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_cfgbridge_main0_esr_m_1_5_am_cfgPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39115main0_esr_m register am_cfg0xFC20R/W0x0000000000000001Pcie_noc_bridge_main0_esr_m_1_5_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr39103AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr39114UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_stsbridge_main0_esr_m_1_5_am_stsPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39243main0_esr_m register am_sts0xFD00R0x000000000000000cPcie_noc_bridge_main0_esr_m_1_5_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr39148ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr39162WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr39174ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr39186WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr39197ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr39208AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr39220ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr39232AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr39242UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_bridge_idbridge_main0_esr_m_1_5_am_bridge_idPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39273main0_esr_m register am_bridge_id0xFD08R0x0000000000000001Pcie_noc_bridge_main0_esr_m_1_5_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr39262IDUnique bridge ID1500x0001RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr39272UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_errbridge_main0_esr_m_1_5_am_errPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39769main0_esr_m register am_err0xFE00R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr39295E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr39307E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr39319E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr39331E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr39343E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr39355E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr39368E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr39381E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr39392E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr39403UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr39414E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr39425E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr39436E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr39447E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr39458E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr39469E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr39480E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr39492E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr39503E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr39514UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr39525E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr39536E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr39548E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr39560E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr39571UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr39583E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr39594E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr39605E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr39616E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr39627E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr39638E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr39649E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr39661E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr39673E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr39685E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr39697E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr39709E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr39721E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr39733E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr39745E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr39757E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr39768UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_toslvidbridge_main0_esr_m_1_5_am_toslvidPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39814main0_esr_m register am_toslvid0xFE08R0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr39792AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr39803AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr39813UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_erabridge_main0_esr_m_1_5_am_eraPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39836main0_esr_m register am_era0xFE10R0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr39835READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_ewabridge_main0_esr_m_1_5_am_ewaPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr39858main0_esr_m register am_ewa0xFE18R0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr39857WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_intmbridge_main0_esr_m_1_5_am_intmPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40342main0_esr_m register am_intm0xFE40R/W0x00007e07004f004fPcie_noc_bridge_main0_esr_m_1_5_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr39880M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr39891M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr39902M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr39913M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr39924M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr39935M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr39946M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr39957M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr39968M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr39979UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr39990M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr40001M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr40012M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr40023M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr40034M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr40045M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr40056M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr40067M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr40078M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr40089UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr40100M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr40111M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr40122M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr40133M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr40144UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr40156M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr40167M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr40178M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr40189M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr40200M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr40211M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr40222M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr40234E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr40246E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr40258E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr40270E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr40282E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr40294E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr40306E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr40318E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr40330E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr40341UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_caddrbridge_main0_esr_m_1_5_am_caddrPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40364main0_esr_m register am_caddr0xFF00R/W0xffffffffffffffffPcie_noc_bridge_main0_esr_m_1_5_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr40363CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_main0_esr_m_1_5_am_caddrmskbridge_main0_esr_m_1_5_am_caddrmskPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40387main0_esr_m register am_caddrmsk0xFF08R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr40386CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_main0_esr_m_1_5_am_ccmd0bridge_main0_esr_m_1_5_am_ccmd0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40577main0_esr_m register am_ccmd00xFF10R/W0x0000000003fff33fPcie_noc_bridge_main0_esr_m_1_5_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr40409SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr40420DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr40431UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr40442BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr40453UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr40464CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr40475QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr40486PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr40497LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr40508RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr40519VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr40530UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr40542INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr40553UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr40565TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr40576UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk0bridge_main0_esr_m_1_5_am_ccmdmsk0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40721main0_esr_m register am_ccmdmsk00xFF18R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr40599SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr40610DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr40621UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr40632BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr40643UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr40654CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr40665QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr40676PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr40687LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr40698RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr40709VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr40720UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_cntr0bridge_main0_esr_m_1_5_am_cntr0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40756main0_esr_m register am_cntr00xFF20R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr40744CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr40755UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_latnum0bridge_main0_esr_m_1_5_am_latnum0PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40795main0_esr_m register am_latnum00xFF28R/W0x0000000000000007Pcie_noc_bridge_main0_esr_m_1_5_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr40783CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr40794UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_ccmd1bridge_main0_esr_m_1_5_am_ccmd1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr40985main0_esr_m register am_ccmd10xFF30R/W0x0000000003fff33fPcie_noc_bridge_main0_esr_m_1_5_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr40817SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr40828DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr40839UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr40850BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr40861UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr40872CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr40883QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr40894PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr40905LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr40916RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr40927VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr40938UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr40950INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr40961UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr40973TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr40984UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_ccmdmsk1bridge_main0_esr_m_1_5_am_ccmdmsk1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41129main0_esr_m register am_ccmdmsk10xFF38R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr41007SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr41018DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr41029UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr41040BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr41051UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr41062CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr41073QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr41084PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr41095LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr41106RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr41117VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr41128UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_cntr1bridge_main0_esr_m_1_5_am_cntr1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41164main0_esr_m register am_cntr10xFF40R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr41152CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr41163UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_latnum1bridge_main0_esr_m_1_5_am_latnum1PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41203main0_esr_m register am_latnum10xFF48R/W0x0000000000000007Pcie_noc_bridge_main0_esr_m_1_5_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr41191CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr41202UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_arovrdbridge_main0_esr_m_1_5_am_arovrdPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41316main0_esr_m register am_arovrd0xFF60R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr41221arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr41234arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr41245arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr41256UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr41269arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr41280UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr41291arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr41304arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr41315UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_esr_m_1_5_am_awovrdbridge_main0_esr_m_1_5_am_awovrdPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41429main0_esr_m register am_awovrd0xFF68R/W0x0000000000000000Pcie_noc_bridge_main0_esr_m_1_5_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr41334awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr41347awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr41358awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr41369UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr41382awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr41393UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr41404awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr41417awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_ESR_M_1_5_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr41428UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41545main0_mesh_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x10000R/W0x0000000058200010Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr41469P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr41480NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr41491I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr41503R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr41514DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr41526LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr41537BASE_ADDRESS_0_33Base address3960x001608000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr41544UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41637main0_mesh_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x10008R/W0x000000fffffff000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr41562P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr41573NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr41584I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr41595VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr41607TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr41618RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr41629MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr41636UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41753main0_mesh_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x10020R/W0x0000007f80000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr41677P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr41688NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr41699I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr41711R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr41722DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr41734LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr41745BASE_ADDRESS_0_33Base address3960x1fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr41752UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41845main0_mesh_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x10028R/W0x000000fffffff000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr41770P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr41781NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr41792I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr41803VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr41815TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr41826RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr41837MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr41844UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr41886main0_mesh_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x10030R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr41863UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr41874SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr41885UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42002main0_mesh_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x10040R/W0x0000007f80001000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr41926P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr41937NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr41948I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr41960R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr41971DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr41983LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr41994BASE_ADDRESS_0_33Base address3960x1fe000040R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42001UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42094main0_mesh_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x10048R/W0x000000fffffff000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr42019P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr42030NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr42041I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr42052VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr42064TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr42075RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr42086MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42093UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42135main0_mesh_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x10050R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr42112UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr42123SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SETns_noc_io_pcie_soc_ip.csr42134UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42251main0_mesh_m register am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x10060R/W0x0000007e80000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42175P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42186NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42197I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr42209R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr42220DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr42232LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr42243BASE_ADDRESS_0_33Base address3960x1fa000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42250UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42343main0_mesh_m register am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x10068R/W0x000000ff80000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42268P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42279NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42290I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr42301VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr42313TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr42324RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr42335MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42342UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42384main0_mesh_m register am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x10070R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr42361UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr42372SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr42383UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42500main0_mesh_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00x10080R/W0x0000004000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42424P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42435NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42446I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr42458R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr42469DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr42481LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr42492BASE_ADDRESS_0_33Base address3960x100000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42499UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42592main0_mesh_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00x10088R/W0x000000e000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42517P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42528NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42539I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr42550VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr42562TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr42573RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr42584MASK_0_33Mask3960x380000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42591UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42708main0_mesh_m register am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x100A0R/W0x0000007f00000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42632P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42643NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42654I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr42666R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr42677DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr42689LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr42700BASE_ADDRESS_0_33Base address3960x1fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42707UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42800main0_mesh_m register am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x100A8R/W0x000000ff80000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42725P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42736NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42747I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr42758VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr42770TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr42781RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr42792MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42799UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42841main0_mesh_m register am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x100B0R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr42818UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr42829SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr42840UNSDUnused63400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr42957main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00x100C0R/W0x0000006000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42881P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42892NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42903I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr42915R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr42926DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr42938LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr42949BASE_ADDRESS_0_33Base address3960x180000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr42956UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43049main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00x100C8R/W0x000000f000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr42974P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr42985NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr42996I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr43007VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr43019TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr43030RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr43041MASK_0_33Mask3960x3c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43048UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43165main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00x100E0R/W0x0000007000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr43089P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr43100NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr43111I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr43123R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SETns_noc_io_pcie_soc_ip.csr43134DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr43146LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr43157BASE_ADDRESS_0_33Base address3960x1c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43164UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43257main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00x100E8R/W0x000000f800000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr43182P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr43193NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr43204I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr43215VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SETns_noc_io_pcie_soc_ip.csr43227TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr43238RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr43249MASK_0_33Mask3960x3e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43256UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43373main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00x10100R/W0x0000007800000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr43297P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr43308NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr43319I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr43331R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SETns_noc_io_pcie_soc_ip.csr43342DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr43354LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr43365BASE_ADDRESS_0_33Base address3960x1e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43372UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43465main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00x10108R/W0x000000fc00000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr43390P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr43401NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr43412I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr43423VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SETns_noc_io_pcie_soc_ip.csr43435TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr43446RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr43457MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43464UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43581main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00x10120R/W0x0000007c00000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr43505P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr43516NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr43527I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr43539R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SETns_noc_io_pcie_soc_ip.csr43550DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr43562LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr43573BASE_ADDRESS_0_33Base address3960x1f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43580UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43673main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00x10128R/W0x000000fe00000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr43598P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr43609NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr43620I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr43631VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SETns_noc_io_pcie_soc_ip.csr43643TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr43654RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr43665MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43672UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43789main0_mesh_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00x10140R/W0x0000007e00000000Pcie_noc_bridge_main0_mesh_m_2_5_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr43713P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr43724NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr43735I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr43747R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SETns_noc_io_pcie_soc_ip.csr43758DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr43770LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr43781BASE_ADDRESS_0_33Base address3960x1f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43788UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43881main0_mesh_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00x10148R/W0x000000ff80000000Pcie_noc_bridge_main0_mesh_m_2_5_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr43806P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr43817NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr43828I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr43839VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SETns_noc_io_pcie_soc_ip.csr43851TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr43862RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr43873MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr43880UNSD_34_5763400x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_p_0bridge_main0_mesh_m_2_5_p_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr43946main0_mesh_m register p_00x13000R/W0x00000003Pcie_noc_bridge_main0_mesh_m_2_5_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr43909WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr43921WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr43933WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr43945WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_p_1bridge_main0_mesh_m_2_5_p_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr44012main0_mesh_m register p_10x13008R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr43975WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr43987WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr43999WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr44011WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_p_2bridge_main0_mesh_m_2_5_p_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr44078main0_mesh_m register p_20x13010R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr44041WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr44053WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr44065WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr44077WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_p_3bridge_main0_mesh_m_2_5_p_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr44144main0_mesh_m register p_30x13018R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr44107WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr44119WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr44131WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr44143WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_txebridge_main0_mesh_m_2_5_txePCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr44290main0_mesh_m register txe0x13040R/W0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr44171TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr44183SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr44198TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr44211EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr44225FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr44239FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr44253FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr44267FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr44278PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr44289UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_txembridge_main0_mesh_m_2_5_txemPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr44369main0_mesh_m register txem0x13048R/W0x00000008Pcie_noc_bridge_main0_mesh_m_2_5_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr44313UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr44324TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr44335EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr44346UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr44357PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr44368UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btus_0bridge_main0_mesh_m_2_5_btus_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr44737main0_mesh_m register btus_00x13058R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr44395L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr44406L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr44417L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr44428L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr44439L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr44450L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr44461L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr44472L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr44483L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr44494L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr44505L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr44516L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr44527L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr44538L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr44549L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr44560L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr44571L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr44582L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr44593L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr44604L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr44615L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr44626L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr44637L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr44648L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr44659L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr44670L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr44681L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr44692L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr44703L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr44714L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr44725L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr44736L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btus_1bridge_main0_mesh_m_2_5_btus_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45105main0_mesh_m register btus_10x13060R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr44763L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr44774L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr44785L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr44796L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr44807L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr44818L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr44829L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr44840L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr44851L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr44862L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr44873L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr44884L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr44895L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr44906L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr44917L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr44928L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr44939L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr44950L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr44961L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr44972L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr44983L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr44994L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr45005L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr45016L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr45027L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr45038L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr45049L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr45060L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr45071L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr45082L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr45093L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr45104L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btrl_0bridge_main0_mesh_m_2_5_btrl_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45181main0_mesh_m register btrl_00x13080R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr45129WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr45140RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr45155CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr45169EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr45180UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btrl_1bridge_main0_mesh_m_2_5_btrl_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45257main0_mesh_m register btrl_10x13088R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr45205WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr45216RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr45231CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr45245EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr45256UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btrl_2bridge_main0_mesh_m_2_5_btrl_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45333main0_mesh_m register btrl_20x13090R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr45281WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr45292RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr45307CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr45321EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr45332UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btrl_3bridge_main0_mesh_m_2_5_btrl_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45409main0_mesh_m register btrl_30x13098R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr45357WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr45368RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr45383CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr45397EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr45408UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btperrbridge_main0_mesh_m_2_5_btperrPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45611main0_mesh_m register btperr0x130A8R/W0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr45434L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr45445L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr45456L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr45467L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr45478L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr45489L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr45500L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr45511L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr45522L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr45533L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr45544L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr45555L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr45566L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr45577L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr45588L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr45599L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr45610UNSD31160x0000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_btperrmbridge_main0_mesh_m_2_5_btperrmPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45811main0_mesh_m register btperrm0x130B0R/W0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr45634L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr45645L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr45656L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr45667L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr45678L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr45689L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr45700L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr45711L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr45722L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr45733L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr45744L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr45755L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr45766L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr45777L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr45788L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr45799L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr45810UNSD31160x0000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_rxebridge_main0_mesh_m_2_5_rxePCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45919main0_mesh_m register rxe0x13120R/W0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr45839CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr45850CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr45861CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr45872CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr45884EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr45895PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr45907EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr45918UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_rxembridge_main0_mesh_m_2_5_rxemPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr45991main0_mesh_m register rxem0x13128R/W0x00000050Pcie_noc_bridge_main0_mesh_m_2_5_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr45940UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr45954EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr45965PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr45979EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr45990UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brs_0bridge_main0_mesh_m_2_5_brs_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr46265main0_mesh_m register brs_00x13130R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr46015OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr46026V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr46037S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr46048B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr46059F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr46069UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr46080OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr46091V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr46102S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr46113B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr46124F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr46134UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr46145OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr46156V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr46167S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr46178B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr46189F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr46199UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr46210OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr46221V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr46232S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr46243B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr46254F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr46264UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brs_1bridge_main0_mesh_m_2_5_brs_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr46539main0_mesh_m register brs_10x13138R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr46289OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr46300V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr46311S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr46322B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr46333F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr46343UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr46354OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr46365V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr46376S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr46387B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr46398F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr46408UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr46419OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr46430V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr46441S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr46452B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr46463F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr46473UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr46484OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr46495V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr46506S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr46517B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr46528F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr46538UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brusbridge_main0_mesh_m_2_5_brusPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr46608main0_mesh_m register brus0x131B0R0x00000000Pcie_noc_bridge_main0_mesh_m_2_5_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr46564V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr46575V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr46586V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr46597V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr46607UNSD_31_43140x0000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brperr0bridge_main0_mesh_m_2_5_brperr0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr46836main0_mesh_m register brperr00x131D0R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr46646D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr46657DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr46668SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr46680SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr46691PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr46702UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr46713D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr46724DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr46735SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr46747SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr46758PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr46769UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr46780UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr46791UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr46802UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr46813UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr46824UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr46835UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brperr1bridge_main0_mesh_m_2_5_brperr1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr46952main0_mesh_m register brperr10x131D8R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr46874UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr46885UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr46896UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr46907UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr46918UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr46929UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr46940UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr46951UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brperrm0bridge_main0_mesh_m_2_5_brperrm0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47173main0_mesh_m register brperrm00x131E0R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr46979D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr46991DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr47002SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr47014SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr47026PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr47037UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr47048D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr47060DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr47071SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr47083SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr47095PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr47106UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr47117UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr47128UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr47139UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr47150UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr47161UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr47172UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_brperrm1bridge_main0_mesh_m_2_5_brperrm1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47278main0_mesh_m register brperrm10x131E8R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr47200UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr47211UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr47222UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr47233UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr47244UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr47255UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr47266UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr47277UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_tocfgbridge_main0_mesh_m_2_5_am_tocfgPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47352main0_mesh_m register am_tocfg0x13C00R/W0x000000000000001fPcie_noc_bridge_main0_mesh_m_2_5_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr47315TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr47326UNSD_7_6760x0RENPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr47340EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr47351UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_osslvbridge_main0_mesh_m_2_5_am_osslvPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47387main0_mesh_m register am_osslv0x13C08R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr47375SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr47386UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_cgcbridge_main0_mesh_m_2_5_am_cgcPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47424main0_mesh_m register am_cgc0x13C10R/W0x0000000000000064Pcie_noc_bridge_main0_mesh_m_2_5_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr47412HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr47423UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_cgobridge_main0_mesh_m_2_5_am_cgoPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47459main0_mesh_m register am_cgo0x13C18R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr47447FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr47458UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_cfgbridge_main0_mesh_m_2_5_am_cfgPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47496main0_mesh_m register am_cfg0x13C20R/W0x0000000000000001Pcie_noc_bridge_main0_mesh_m_2_5_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr47484AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr47495UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_stsbridge_main0_mesh_m_2_5_am_stsPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47624main0_mesh_m register am_sts0x13D00R0x000000000000000cPcie_noc_bridge_main0_mesh_m_2_5_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr47529ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr47543WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr47555ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr47567WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr47578ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr47589AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr47601ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr47613AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr47623UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_bridge_idbridge_main0_mesh_m_2_5_am_bridge_idPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr47654main0_mesh_m register am_bridge_id0x13D08R0x0000000000000002Pcie_noc_bridge_main0_mesh_m_2_5_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr47643IDUnique bridge ID1500x0002RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr47653UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_errbridge_main0_mesh_m_2_5_am_errPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48150main0_mesh_m register am_err0x13E00R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr47676E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr47688E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr47700E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr47712E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr47724E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr47736E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr47749E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr47762E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr47773E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr47784UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr47795E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr47806E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr47817E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr47828E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr47839E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr47850E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr47861E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr47873E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr47884E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr47895UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr47906E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr47917E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr47929E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr47941E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr47952UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr47964E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr47975E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr47986E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr47997E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr48008E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr48019E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr48030E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr48042E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr48054E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr48066E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr48078E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr48090E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr48102E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr48114E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr48126E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr48138E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr48149UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_toslvidbridge_main0_mesh_m_2_5_am_toslvidPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48195main0_mesh_m register am_toslvid0x13E08R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr48173AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr48184AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr48194UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_erabridge_main0_mesh_m_2_5_am_eraPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48217main0_mesh_m register am_era0x13E10R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr48216READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_ewabridge_main0_mesh_m_2_5_am_ewaPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48239main0_mesh_m register am_ewa0x13E18R0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr48238WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_intmbridge_main0_mesh_m_2_5_am_intmPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48723main0_mesh_m register am_intm0x13E40R/W0x00007e07004f004fPcie_noc_bridge_main0_mesh_m_2_5_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr48261M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr48272M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr48283M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr48294M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr48305M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr48316M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr48327M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr48338M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr48349M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr48360UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr48371M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr48382M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr48393M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr48404M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr48415M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr48426M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr48437M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr48448M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr48459M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr48470UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr48481M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr48492M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr48503M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr48514M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr48525UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr48537M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr48548M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr48559M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr48570M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr48581M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr48592M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr48603M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr48615E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr48627E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr48639E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr48651E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr48663E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr48675E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr48687E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr48699E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr48711E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr48722UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_caddrbridge_main0_mesh_m_2_5_am_caddrPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48745main0_mesh_m register am_caddr0x13F00R/W0xffffffffffffffffPcie_noc_bridge_main0_mesh_m_2_5_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr48744CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_main0_mesh_m_2_5_am_caddrmskbridge_main0_mesh_m_2_5_am_caddrmskPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48768main0_mesh_m register am_caddrmsk0x13F08R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr48767CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_main0_mesh_m_2_5_am_ccmd0bridge_main0_mesh_m_2_5_am_ccmd0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr48958main0_mesh_m register am_ccmd00x13F10R/W0x0000000003fff33fPcie_noc_bridge_main0_mesh_m_2_5_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr48790SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr48801DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr48812UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr48823BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr48834UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr48845CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr48856QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr48867PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr48878LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr48889RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr48900VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr48911UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr48923INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr48934UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr48946TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr48957UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_ccmdmsk0bridge_main0_mesh_m_2_5_am_ccmdmsk0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49102main0_mesh_m register am_ccmdmsk00x13F18R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr48980SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr48991DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr49002UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr49013BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr49024UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr49035CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr49046QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr49057PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr49068LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr49079RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr49090VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr49101UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_cntr0bridge_main0_mesh_m_2_5_am_cntr0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49137main0_mesh_m register am_cntr00x13F20R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr49125CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr49136UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_latnum0bridge_main0_mesh_m_2_5_am_latnum0PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49176main0_mesh_m register am_latnum00x13F28R/W0x0000000000000007Pcie_noc_bridge_main0_mesh_m_2_5_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr49164CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr49175UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_ccmd1bridge_main0_mesh_m_2_5_am_ccmd1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49366main0_mesh_m register am_ccmd10x13F30R/W0x0000000003fff33fPcie_noc_bridge_main0_mesh_m_2_5_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr49198SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr49209DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr49220UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr49231BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr49242UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr49253CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr49264QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr49275PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr49286LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr49297RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr49308VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr49319UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr49331INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr49342UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr49354TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr49365UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_ccmdmsk1bridge_main0_mesh_m_2_5_am_ccmdmsk1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49510main0_mesh_m register am_ccmdmsk10x13F38R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr49388SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr49399DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr49410UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr49421BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr49432UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr49443CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr49454QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr49465PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr49476LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr49487RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr49498VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr49509UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_cntr1bridge_main0_mesh_m_2_5_am_cntr1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49545main0_mesh_m register am_cntr10x13F40R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr49533CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr49544UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_latnum1bridge_main0_mesh_m_2_5_am_latnum1PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49584main0_mesh_m register am_latnum10x13F48R/W0x0000000000000007Pcie_noc_bridge_main0_mesh_m_2_5_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr49572CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr49583UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_arovrdbridge_main0_mesh_m_2_5_am_arovrdPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49697main0_mesh_m register am_arovrd0x13F60R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr49602arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr49615arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr49626arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr49637UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr49650arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr49661UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr49672arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr49685arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr49696UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_mesh_m_2_5_am_awovrdbridge_main0_mesh_m_2_5_am_awovrdPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49810main0_mesh_m register am_awovrd0x13F68R/W0x0000000000000000Pcie_noc_bridge_main0_mesh_m_2_5_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr49715awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr49728awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr49739awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr49750UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr49763awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr49774UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr49785awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr49798awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_MESH_M_2_5_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr49809UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_cgcbridge_main0_tol3_s_7_5_as_cgcPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49847main0_tol3_s register as_cgc0x15C10R/W0x0000000000000064Pcie_noc_bridge_main0_tol3_s_7_5_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr49835HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr49846UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_cgobridge_main0_tol3_s_7_5_as_cgoPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49882main0_tol3_s register as_cgo0x15C18R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr49870FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr49881UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_stsbridge_main0_tol3_s_7_5_as_stsPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49956main0_tol3_s register as_sts0x15D00R0x000000000000000cPcie_noc_bridge_main0_tol3_s_7_5_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr49905WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr49921ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr49933WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr49945ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr49955UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_bridge_idbridge_main0_tol3_s_7_5_as_bridge_idPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr49986main0_tol3_s register as_bridge_id0x15D08R0x0000000000000007Pcie_noc_bridge_main0_tol3_s_7_5_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr49975IDUnique bridge ID1500x0007RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr49985UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_errbridge_main0_tol3_s_7_5_as_errPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr50339main0_tol3_s register as_err0x15E00R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr50007E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr50019E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr50032E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr50046E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr50058E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr50069UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr50081E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr50093E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr50106E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr50118E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr50129UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr50141E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr50152E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr50163E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr50174E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr50185E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr50196E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr50207E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr50219E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr50231E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr50243E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr50255E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr50267E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr50279E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr50291E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr50303E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr50315E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr50327E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr50338UNSD_63_4963490x0000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_intmbridge_main0_tol3_s_7_5_as_intmPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr50679main0_tol3_s register as_intm0x15E40R/W0x0000007d000b0013Pcie_noc_bridge_main0_tol3_s_7_5_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr50360M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr50371M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr50382M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr50393M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr50404M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr50415UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr50426M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr50437M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr50448M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr50459M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr50470UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr50481M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr50492M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr50503M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr50514M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr50525M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr50536M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr50547M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr50559E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr50571E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr50583E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr50595E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr50607E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr50619E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr50631E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr50643E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr50655E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr50667E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr50678UNSD_63_4963490x0000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_ccmdbridge_main0_tol3_s_7_5_as_ccmdPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr50754main0_tol3_s register as_ccmd0x15F00R/W0x0000000003000000Pcie_noc_bridge_main0_tol3_s_7_5_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr50697UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr50708rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr50719val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr50730UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr50742intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr50753UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_ccmdmskbridge_main0_tol3_s_7_5_as_ccmdmskPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr50806main0_tol3_s register as_ccmdmsk0x15F08R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr50772UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr50783rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr50794val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr50805UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_cntrbridge_main0_tol3_s_7_5_as_cntrPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr50836main0_tol3_s register as_cntr0x15F10R0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr50825CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr50835UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_arovrdbridge_main0_tol3_s_7_5_as_arovrdPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr50949main0_tol3_s register as_arovrd0x15F18R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr50854arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr50867arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr50878arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr50889UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr50902arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr50913UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr50924arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr50937arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr50948UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_as_awovrdbridge_main0_tol3_s_7_5_as_awovrdPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51062main0_tol3_s register as_awovrd0x15F20R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr50967awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr50980awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr50991awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr51002UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr51015awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr51026UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr51037awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr51050awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr51061UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_p_0bridge_main0_tol3_s_7_5_p_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51127main0_tol3_s register p_00x17000R/W0x00000003Pcie_noc_bridge_main0_tol3_s_7_5_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr51090WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr51102WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr51114WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr51126WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_p_1bridge_main0_tol3_s_7_5_p_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51193main0_tol3_s register p_10x17008R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr51156WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr51168WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr51180WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr51192WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_p_2bridge_main0_tol3_s_7_5_p_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51259main0_tol3_s register p_20x17010R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr51222WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr51234WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr51246WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr51258WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_p_3bridge_main0_tol3_s_7_5_p_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51325main0_tol3_s register p_30x17018R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr51288WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr51300WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr51312WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr51324WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_txebridge_main0_tol3_s_7_5_txePCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51471main0_tol3_s register txe0x17040R/W0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr51352TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr51364SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr51379TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr51392EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr51406FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr51420FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr51434FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr51448FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr51459PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr51470UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_txembridge_main0_tol3_s_7_5_txemPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51550main0_tol3_s register txem0x17048R/W0x00000008Pcie_noc_bridge_main0_tol3_s_7_5_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr51494UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr51505TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr51516EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr51527UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr51538PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr51549UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btus_0bridge_main0_tol3_s_7_5_btus_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr51918main0_tol3_s register btus_00x17058R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr51576L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr51587L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr51598L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr51609L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr51620L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr51631L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr51642L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr51653L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr51664L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr51675L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr51686L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr51697L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr51708L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr51719L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr51730L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr51741L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr51752L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr51763L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr51774L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr51785L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr51796L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr51807L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr51818L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr51829L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr51840L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr51851L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr51862L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr51873L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr51884L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr51895L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr51906L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr51917L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btus_1bridge_main0_tol3_s_7_5_btus_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52286main0_tol3_s register btus_10x17060R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr51944L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr51955L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr51966L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr51977L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr51988L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr51999L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr52010L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr52021L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr52032L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr52043L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr52054L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr52065L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr52076L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr52087L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr52098L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr52109L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr52120L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr52131L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr52142L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr52153L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr52164L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr52175L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr52186L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr52197L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr52208L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr52219L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr52230L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr52241L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr52252L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr52263L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr52274L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr52285L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btrl_0bridge_main0_tol3_s_7_5_btrl_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52362main0_tol3_s register btrl_00x17080R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr52310WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr52321RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr52336CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr52350EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr52361UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btrl_1bridge_main0_tol3_s_7_5_btrl_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52438main0_tol3_s register btrl_10x17088R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr52386WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr52397RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr52412CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr52426EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr52437UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btrl_2bridge_main0_tol3_s_7_5_btrl_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52514main0_tol3_s register btrl_20x17090R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr52462WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr52473RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr52488CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr52502EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr52513UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btrl_3bridge_main0_tol3_s_7_5_btrl_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52590main0_tol3_s register btrl_30x17098R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr52538WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr52549RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr52564CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr52578EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr52589UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btperrbridge_main0_tol3_s_7_5_btperrPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52792main0_tol3_s register btperr0x170A8R/W0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr52615L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr52626L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr52637L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr52648L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr52659L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr52670L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr52681L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr52692L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr52703L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr52714L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr52725L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr52736L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr52747L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr52758L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr52769L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr52780L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr52791UNSD31160x0000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_btperrmbridge_main0_tol3_s_7_5_btperrmPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr52992main0_tol3_s register btperrm0x170B0R/W0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr52815L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr52826L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr52837L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr52848L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr52859L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr52870L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr52881L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr52892L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr52903L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr52914L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr52925L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr52936L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr52947L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr52958L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr52969L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr52980L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr52991UNSD31160x0000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_rxebridge_main0_tol3_s_7_5_rxePCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr53100main0_tol3_s register rxe0x17120R/W0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr53020CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr53031CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr53042CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr53053CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr53065EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr53076PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr53088EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr53099UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_rxembridge_main0_tol3_s_7_5_rxemPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr53172main0_tol3_s register rxem0x17128R/W0x00000050Pcie_noc_bridge_main0_tol3_s_7_5_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr53121UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr53135EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr53146PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr53160EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr53171UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brs_0bridge_main0_tol3_s_7_5_brs_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr53446main0_tol3_s register brs_00x17130R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr53196OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr53207V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr53218S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr53229B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr53240F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr53250UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr53261OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr53272V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr53283S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr53294B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr53305F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr53315UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr53326OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr53337V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr53348S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr53359B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr53370F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr53380UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr53391OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr53402V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr53413S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr53424B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr53435F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr53445UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brs_1bridge_main0_tol3_s_7_5_brs_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr53720main0_tol3_s register brs_10x17138R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr53470OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr53481V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr53492S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr53503B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr53514F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr53524UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr53535OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr53546V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr53557S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr53568B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr53579F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr53589UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr53600OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr53611V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr53622S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr53633B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr53644F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr53654UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr53665OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr53676V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr53687S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr53698B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr53709F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr53719UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brusbridge_main0_tol3_s_7_5_brusPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr53789main0_tol3_s register brus0x171B0R0x00000000Pcie_noc_bridge_main0_tol3_s_7_5_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr53745V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr53756V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr53767V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr53778V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr53788UNSD_31_43140x0000000Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brperr0bridge_main0_tol3_s_7_5_brperr0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54017main0_tol3_s register brperr00x171D0R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr53827D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr53838DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr53849SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr53861SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr53872PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr53883UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr53894D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr53905DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr53916SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr53928SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr53939PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr53950UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr53961UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr53972UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr53983UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr53994UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr54005UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr54016UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brperr1bridge_main0_tol3_s_7_5_brperr1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54133main0_tol3_s register brperr10x171D8R0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr54055UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr54066UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr54077UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr54088UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr54099UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr54110UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr54121UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr54132UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brperrm0bridge_main0_tol3_s_7_5_brperrm0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54354main0_tol3_s register brperrm00x171E0R/W0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr54160D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr54172DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr54183SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr54195SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr54207PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr54218UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr54229D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr54241DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr54252SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr54264SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr54276PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr54287UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr54298UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr54309UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr54320UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr54331UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr54342UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr54353UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tol3_s_7_5_brperrm1bridge_main0_tol3_s_7_5_brperrm1PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54459main0_tol3_s register brperrm10x171E8R0x0000000000000000Pcie_noc_bridge_main0_tol3_s_7_5_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr54381UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr54392UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr54403UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr54414UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr54425UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr54436UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr54447UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOL3_S_7_5_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr54458UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_cgcbridge_main0_tosys_s_8_5_as_cgcPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54496main0_tosys_s register as_cgc0x19C10R/W0x0000000000000064Pcie_noc_bridge_main0_tosys_s_8_5_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr54484HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr54495UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_cgobridge_main0_tosys_s_8_5_as_cgoPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54531main0_tosys_s register as_cgo0x19C18R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr54519FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr54530UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_stsbridge_main0_tosys_s_8_5_as_stsPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54605main0_tosys_s register as_sts0x19D00R0x000000000000000cPcie_noc_bridge_main0_tosys_s_8_5_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr54554WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr54570ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr54582WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr54594ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr54604UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_bridge_idbridge_main0_tosys_s_8_5_as_bridge_idPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54635main0_tosys_s register as_bridge_id0x19D08R0x0000000000000008Pcie_noc_bridge_main0_tosys_s_8_5_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr54624IDUnique bridge ID1500x0008RUNSD_63_16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr54634UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_errbridge_main0_tosys_s_8_5_as_errPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr54988main0_tosys_s register as_err0x19E00R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr54656E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr54668E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr54681E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr54695E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr54707E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr54718UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr54730E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr54742E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr54755E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr54767E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr54778UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr54790E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr54801E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr54812E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr54823E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr54834E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr54845E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr54856E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr54868E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr54880E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr54892E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr54904E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr54916E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr54928E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr54940E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr54952E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr54964E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr54976E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr54987UNSD_63_4963490x0000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_intmbridge_main0_tosys_s_8_5_as_intmPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55328main0_tosys_s register as_intm0x19E40R/W0x0000007d000b0013Pcie_noc_bridge_main0_tosys_s_8_5_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr55009M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr55020M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr55031M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr55042M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr55053M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr55064UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr55075M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr55086M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr55097M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr55108M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr55119UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr55130M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr55141M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr55152M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr55163M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr55174M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr55185M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr55196M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr55208E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr55220E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr55232E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr55244E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr55256E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr55268E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr55280E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr55292E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr55304E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr55316E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr55327UNSD_63_4963490x0000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_ccmdbridge_main0_tosys_s_8_5_as_ccmdPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55403main0_tosys_s register as_ccmd0x19F00R/W0x0000000003000000Pcie_noc_bridge_main0_tosys_s_8_5_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr55346UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr55357rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr55368val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr55379UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr55391intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr55402UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_ccmdmskbridge_main0_tosys_s_8_5_as_ccmdmskPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55455main0_tosys_s register as_ccmdmsk0x19F08R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr55421UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr55432rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr55443val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr55454UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_cntrbridge_main0_tosys_s_8_5_as_cntrPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55485main0_tosys_s register as_cntr0x19F10R0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr55474CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr55484UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_arovrdbridge_main0_tosys_s_8_5_as_arovrdPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55598main0_tosys_s register as_arovrd0x19F18R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr55503arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr55516arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr55527arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr55538UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr55551arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr55562UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr55573arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr55586arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr55597UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_as_awovrdbridge_main0_tosys_s_8_5_as_awovrdPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55711main0_tosys_s register as_awovrd0x19F20R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr55616awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr55629awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr55640awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr55651UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr55664awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr55675UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr55686awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr55699awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr55710UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_p_0bridge_main0_tosys_s_8_5_p_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55776main0_tosys_s register p_00x1B000R/W0x00000003Pcie_noc_bridge_main0_tosys_s_8_5_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr55739WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr55751WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr55763WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr55775WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_p_1bridge_main0_tosys_s_8_5_p_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55842main0_tosys_s register p_10x1B008R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr55805WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr55817WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr55829WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr55841WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_p_2bridge_main0_tosys_s_8_5_p_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55908main0_tosys_s register p_20x1B010R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr55871WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr55883WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr55895WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr55907WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_p_3bridge_main0_tosys_s_8_5_p_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr55974main0_tosys_s register p_30x1B018R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr55937WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr55949WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr55961WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr55973WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_txebridge_main0_tosys_s_8_5_txePCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr56120main0_tosys_s register txe0x1B040R/W0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr56001TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr56013SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr56028TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr56041EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr56055FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr56069FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr56083FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr56097FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr56108PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr56119UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_txembridge_main0_tosys_s_8_5_txemPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr56199main0_tosys_s register txem0x1B048R/W0x00000008Pcie_noc_bridge_main0_tosys_s_8_5_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr56143UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr56154TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr56165EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr56176UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr56187PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr56198UNSD_31_93190x000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btus_0bridge_main0_tosys_s_8_5_btus_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr56567main0_tosys_s register btus_00x1B058R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr56225L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr56236L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr56247L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr56258L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr56269L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr56280L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr56291L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr56302L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr56313L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr56324L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr56335L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr56346L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr56357L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr56368L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr56379L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr56390L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr56401L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr56412L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr56423L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr56434L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr56445L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr56456L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr56467L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr56478L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr56489L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr56500L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr56511L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr56522L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr56533L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr56544L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr56555L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr56566L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btus_1bridge_main0_tosys_s_8_5_btus_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr56935main0_tosys_s register btus_10x1B060R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr56593L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr56604L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr56615L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr56626L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr56637L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr56648L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr56659L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr56670L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr56681L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr56692L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr56703L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr56714L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr56725L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr56736L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr56747L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr56758L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr56769L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr56780L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr56791L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr56802L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr56813L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr56824L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr56835L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr56846L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr56857L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr56868L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr56879L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr56890L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr56901L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr56912L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr56923L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr56934L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btrl_0bridge_main0_tosys_s_8_5_btrl_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57011main0_tosys_s register btrl_00x1B080R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr56959WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr56970RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr56985CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr56999EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr57010UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btrl_1bridge_main0_tosys_s_8_5_btrl_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57087main0_tosys_s register btrl_10x1B088R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr57035WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr57046RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr57061CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr57075EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr57086UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btrl_2bridge_main0_tosys_s_8_5_btrl_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57163main0_tosys_s register btrl_20x1B090R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr57111WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr57122RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr57137CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr57151EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr57162UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btrl_3bridge_main0_tosys_s_8_5_btrl_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57239main0_tosys_s register btrl_30x1B098R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr57187WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr57198RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr57213CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr57227EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr57238UNSD_31_2131210x000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btperrbridge_main0_tosys_s_8_5_btperrPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57441main0_tosys_s register btperr0x1B0A8R/W0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr57264L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr57275L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr57286L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr57297L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr57308L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr57319L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr57330L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr57341L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr57352L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr57363L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr57374L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr57385L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr57396L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr57407L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr57418L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr57429L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr57440UNSD31160x0000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_btperrmbridge_main0_tosys_s_8_5_btperrmPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57641main0_tosys_s register btperrm0x1B0B0R/W0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr57464L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr57475L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr57486L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr57497L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr57508L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr57519L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr57530L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr57541L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr57552L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr57563L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr57574L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr57585L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr57596L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr57607L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr57618L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr57629L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr57640UNSD31160x0000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_rxebridge_main0_tosys_s_8_5_rxePCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57749main0_tosys_s register rxe0x1B120R/W0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr57669CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr57680CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr57691CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr57702CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr57714EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr57725PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr57737EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr57748UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_rxembridge_main0_tosys_s_8_5_rxemPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr57821main0_tosys_s register rxem0x1B128R/W0x00000050Pcie_noc_bridge_main0_tosys_s_8_5_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr57770UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr57784EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr57795PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr57809EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr57820UNSD_31_73170x0000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brs_0bridge_main0_tosys_s_8_5_brs_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr58095main0_tosys_s register brs_00x1B130R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr57845OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr57856V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr57867S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr57878B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr57889F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr57899UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr57910OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr57921V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr57932S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr57943B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr57954F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr57964UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr57975OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr57986V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr57997S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr58008B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr58019F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr58029UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr58040OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr58051V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr58062S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr58073B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr58084F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr58094UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brs_1bridge_main0_tosys_s_8_5_brs_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr58369main0_tosys_s register brs_10x1B138R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr58119OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr58130V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr58141S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr58152B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr58163F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr58173UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr58184OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr58195V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr58206S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr58217B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr58228F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr58238UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr58249OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr58260V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr58271S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr58282B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr58293F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr58303UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr58314OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr58325V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr58336S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr58347B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr58358F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr58368UNSD_31_3031300x0Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brusbridge_main0_tosys_s_8_5_brusPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr58438main0_tosys_s register brus0x1B1B0R0x00000000Pcie_noc_bridge_main0_tosys_s_8_5_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr58394V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr58405V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr58416V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr58427V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr58437UNSD_31_43140x0000000Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brperr0bridge_main0_tosys_s_8_5_brperr0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr58666main0_tosys_s register brperr00x1B1D0R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr58476D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr58487DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr58498SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr58510SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr58521PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr58532UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr58543D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr58554DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr58565SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr58577SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr58588PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr58599UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr58610UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr58621UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr58632UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr58643UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr58654UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr58665UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brperr1bridge_main0_tosys_s_8_5_brperr1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr58782main0_tosys_s register brperr10x1B1D8R0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr58704UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr58715UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr58726UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr58737UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr58748UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr58759UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr58770UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr58781UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brperrm0bridge_main0_tosys_s_8_5_brperrm0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59003main0_tosys_s register brperrm00x1B1E0R/W0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr58809D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr58821DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr58832SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr58844SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr58856PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr58867UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr58878D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr58890DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr58901SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr58913SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr58925PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr58936UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr58947UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr58958UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr58969UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr58980UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr58991UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr59002UNSD_63_5663560x00Rregisterpcie_noc.bridge_main0_tosys_s_8_5_brperrm1bridge_main0_tosys_s_8_5_brperrm1PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59108main0_tosys_s register brperrm10x1B1E8R0x0000000000000000Pcie_noc_bridge_main0_tosys_s_8_5_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr59030UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr59041UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr59052UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr59063UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr59074UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr59085UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr59096UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_MAIN0_TOSYS_S_8_5_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr59107UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59224p0_p0_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x1C000R/W0x0000000058200010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr59148P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr59159NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr59170I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr59182R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr59193DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr59205LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr59216BASE_ADDRESS_0_33Base address3960x001608000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59223UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59316p0_p0_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x1C008R/W0x000000fffffff000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr59241P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr59252NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr59263I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr59274VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr59286TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr59297RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr59308MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59315UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59432p0_p0_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x1C020R/W0x0000007f80000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr59356P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr59367NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr59378I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr59390R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr59401DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr59413LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr59424BASE_ADDRESS_0_33Base address3960x1fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59431UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59524p0_p0_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x1C028R/W0x000000fffffff000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr59449P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr59460NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr59471I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr59482VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr59494TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr59505RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr59516MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59523UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59565p0_p0_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x1C030R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr59542UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr59553SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr59564UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59681p0_p0_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x1C040R/W0x0000007f80001010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr59605P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr59616NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr59627I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr59639R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr59650DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr59662LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr59673BASE_ADDRESS_0_33Base address3960x1fe000040R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59680UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59773p0_p0_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x1C048R/W0x000000fffffff000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr59698P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr59709NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr59720I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr59731VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr59743TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr59754RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr59765MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59772UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59814p0_p0_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x1C050R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr59791UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr59802SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SETns_noc_io_pcie_soc_ip.csr59813UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr59930p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00x1C060R/W0x0000000080000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr59854P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr59865NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr59876I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr59888R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr59899DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr59911LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr59922BASE_ADDRESS_0_33Base address3960x002000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr59929UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60022p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00x1C068R/W0x000000ff80000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr59947P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr59958NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr59969I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr59980VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr59992TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr60003RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr60014MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60021UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60138p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00x1C080R/W0x0000008000200010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr60062P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr60073NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr60084I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr60096R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SETns_noc_io_pcie_soc_ip.csr60107DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr60119LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr60130BASE_ADDRESS_0_33Base address3960x200008000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60137UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60230p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00x1C088R/W0x000000ffffe00000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr60155P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr60166NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr60177I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr60188VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SETns_noc_io_pcie_soc_ip.csr60200TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr60211RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr60222MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60229UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60346p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00x1C0A0R/W0x0000008000400010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr60270P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr60281NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr60292I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr60304R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SETns_noc_io_pcie_soc_ip.csr60315DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr60327LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr60338BASE_ADDRESS_0_33Base address3960x200010000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60345UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60438p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00x1C0A8R/W0x000000ffffc00000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr60363P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr60374NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr60385I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr60396VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SETns_noc_io_pcie_soc_ip.csr60408TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr60419RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr60430MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60437UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60554p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00x1C0C0R/W0x0000008000800010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr60478P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr60489NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr60500I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr60512R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SETns_noc_io_pcie_soc_ip.csr60523DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr60535LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr60546BASE_ADDRESS_0_33Base address3960x200020000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60553UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60646p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00x1C0C8R/W0x000000ffff800000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr60571P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr60582NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr60593I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr60604VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SETns_noc_io_pcie_soc_ip.csr60616TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr60627RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr60638MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60645UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60762p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00x1C0E0R/W0x0000008001000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr60686P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr60697NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr60708I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr60720R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SETns_noc_io_pcie_soc_ip.csr60731DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr60743LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr60754BASE_ADDRESS_0_33Base address3960x200040000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60761UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60854p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00x1C0E8R/W0x000000ffff000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr60779P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr60790NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr60801I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr60812VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SETns_noc_io_pcie_soc_ip.csr60824TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr60835RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr60846MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60853UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr60970p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00x1C100R/W0x0000008002000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr60894P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr60905NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr60916I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr60928R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SETns_noc_io_pcie_soc_ip.csr60939DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr60951LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr60962BASE_ADDRESS_0_33Base address3960x200080000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr60969UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61062p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00x1C108R/W0x000000fffe000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr60987P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr60998NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr61009I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr61020VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SETns_noc_io_pcie_soc_ip.csr61032TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr61043RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr61054MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61061UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61178p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00x1C120R/W0x0000008004000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr61102P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr61113NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr61124I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr61136R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr61147DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr61159LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr61170BASE_ADDRESS_0_33Base address3960x200100000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61177UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61270p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00x1C128R/W0x000000fffc000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr61195P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr61206NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr61217I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr61228VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr61240TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr61251RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr61262MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61269UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61386p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00x1C140R/W0x0000008008000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr61310P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr61321NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr61332I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr61344R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr61355DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr61367LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr61378BASE_ADDRESS_0_33Base address3960x200200000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61385UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61478p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00x1C148R/W0x000000fff8000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr61403P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr61414NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr61425I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr61436VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr61448TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr61459RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr61470MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61477UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61594p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00x1C160R/W0x0000008010000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr61518P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr61529NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr61540I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr61552R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr61563DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr61575LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr61586BASE_ADDRESS_0_33Base address3960x200400000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61593UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61686p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00x1C168R/W0x000000fff0000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr61611P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr61622NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr61633I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr61644VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr61656TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr61667RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr61678MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61685UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61802p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00x1C180R/W0x0000008020000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr61726P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr61737NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr61748I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr61760R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr61771DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr61783LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr61794BASE_ADDRESS_0_33Base address3960x200800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61801UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr61894p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00x1C188R/W0x000000ffe0000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr61819P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr61830NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr61841I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr61852VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr61864TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr61875RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr61886MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr61893UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62010p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00x1C1A0R/W0x0000008040000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr61934P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr61945NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr61956I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr61968R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SETns_noc_io_pcie_soc_ip.csr61979DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr61991LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr62002BASE_ADDRESS_0_33Base address3960x201000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62009UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62102p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00x1C1A8R/W0x000000ffc0000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr62027P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr62038NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr62049I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr62060VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SETns_noc_io_pcie_soc_ip.csr62072TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr62083RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr62094MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62101UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62218p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00x1C1C0R/W0x0000008080000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr62142P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr62153NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr62164I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr62176R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SETns_noc_io_pcie_soc_ip.csr62187DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr62199LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr62210BASE_ADDRESS_0_33Base address3960x202000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62217UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62310p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00x1C1C8R/W0x000000ff80000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr62235P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr62246NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr62257I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr62268VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SETns_noc_io_pcie_soc_ip.csr62280TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr62291RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr62302MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62309UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62426p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00x1C1E0R/W0x0000008100000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr62350P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr62361NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr62372I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr62384R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SETns_noc_io_pcie_soc_ip.csr62395DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr62407LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr62418BASE_ADDRESS_0_33Base address3960x204000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62425UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62518p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00x1C1E8R/W0x000000ff00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr62443P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr62454NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr62465I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr62476VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SETns_noc_io_pcie_soc_ip.csr62488TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr62499RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr62510MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62517UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62634p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00x1C200R/W0x0000008200000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr62558P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr62569NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr62580I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr62592R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SETns_noc_io_pcie_soc_ip.csr62603DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr62615LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr62626BASE_ADDRESS_0_33Base address3960x208000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62633UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62726p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00x1C208R/W0x000000fe00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr62651P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr62662NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr62673I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr62684VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SETns_noc_io_pcie_soc_ip.csr62696TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr62707RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr62718MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62725UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62842p0_p0_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00x1C220R/W0x0000008400000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr62766P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr62777NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr62788I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr62800R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SETns_noc_io_pcie_soc_ip.csr62811DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr62823LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr62834BASE_ADDRESS_0_33Base address3960x210000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62841UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr62934p0_p0_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00x1C228R/W0x000000fc00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr62859P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr62870NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr62881I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr62892VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SETns_noc_io_pcie_soc_ip.csr62904TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr62915RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr62926MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr62933UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63050p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00x1C240R/W0x0000000002000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr62974P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr62985NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr62996I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr63008R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr63019DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr63031LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr63042BASE_ADDRESS_0_33Base address3960x000080000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63049UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63142p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00x1C248R/W0x000000ffffff0000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr63067P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr63078NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr63089I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr63100VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr63112TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr63123RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr63134MASK_0_33Mask3960x3fffffc00R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63141UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63258p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00x1C260R/W0x0000000020007000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr63182P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr63193NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr63204I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr63216R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr63227DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr63239LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr63250BASE_ADDRESS_0_33Base address3960x0008001c0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63257UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63350p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00x1C268R/W0x000000fffffff000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr63275P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr63286NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr63297I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr63308VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr63320TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr63331RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr63342MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63349UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63466p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00x1C280R/W0x0000000030001000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr63390P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr63401NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr63412I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr63424R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr63435DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr63447LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr63458BASE_ADDRESS_0_33Base address3960x000c00040R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63465UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63558p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00x1C288R/W0x000000fffffff000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr63483P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr63494NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr63505I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr63516VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr63528TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr63539RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr63550MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63557UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63674p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00x1C2A0R/W0x0000000030003000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr63598P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr63609NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr63620I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr63632R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SETns_noc_io_pcie_soc_ip.csr63643DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr63655LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr63666BASE_ADDRESS_0_33Base address3960x000c000c0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63673UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63766p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00x1C2A8R/W0x000000fffffff000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr63691P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr63702NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr63713I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr63724VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SETns_noc_io_pcie_soc_ip.csr63736TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr63747RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr63758MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63765UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63882p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00x1C2C0R/W0x0000000030008000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr63806P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr63817NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr63828I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr63840R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SETns_noc_io_pcie_soc_ip.csr63851DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr63863LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr63874BASE_ADDRESS_0_33Base address3960x000c00200R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63881UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr63974p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00x1C2C8R/W0x000000ffffffe000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr63899P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr63910NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr63921I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr63932VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SETns_noc_io_pcie_soc_ip.csr63944TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr63955RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr63966MASK_0_33Mask3960x3ffffff80R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr63973UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64090p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00x1C2E0R/W0x0000000100000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr64014P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr64025NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr64036I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr64048R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SETns_noc_io_pcie_soc_ip.csr64059DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr64071LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr64082BASE_ADDRESS_0_33Base address3960x004000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64089UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64182p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00x1C2E8R/W0x000000ff00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr64107P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr64118NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr64129I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr64140VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SETns_noc_io_pcie_soc_ip.csr64152TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr64163RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr64174MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64181UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64298p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00x1C300R/W0x000000c000200010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr64222P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr64233NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr64244I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr64256R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr64267DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr64279LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr64290BASE_ADDRESS_0_33Base address3960x300008000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64297UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64390p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00x1C308R/W0x000000ffffe00000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr64315P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr64326NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr64337I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr64348VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr64360TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr64371RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr64382MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64389UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64506p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00x1C320R/W0x000000c000400010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr64430P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr64441NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr64452I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr64464R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr64475DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr64487LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr64498BASE_ADDRESS_0_33Base address3960x300010000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64505UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64598p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00x1C328R/W0x000000ffffc00000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr64523P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr64534NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr64545I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr64556VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr64568TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr64579RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr64590MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64597UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64714p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00x1C340R/W0x000000c000800010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr64638P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr64649NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr64660I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr64672R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr64683DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr64695LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr64706BASE_ADDRESS_0_33Base address3960x300020000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64713UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64806p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00x1C348R/W0x000000ffff800000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr64731P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr64742NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr64753I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr64764VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr64776TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr64787RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr64798MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64805UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr64922p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00x1C360R/W0x000000c001000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr64846P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr64857NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr64868I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr64880R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr64891DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr64903LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr64914BASE_ADDRESS_0_33Base address3960x300040000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr64921UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65014p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00x1C368R/W0x000000ffff000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr64939P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr64950NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr64961I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr64972VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr64984TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr64995RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr65006MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65013UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65130p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00x1C380R/W0x000000c002000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr65054P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr65065NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr65076I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr65088R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SETns_noc_io_pcie_soc_ip.csr65099DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr65111LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr65122BASE_ADDRESS_0_33Base address3960x300080000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65129UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65222p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00x1C388R/W0x000000fffe000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr65147P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr65158NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr65169I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr65180VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SETns_noc_io_pcie_soc_ip.csr65192TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr65203RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr65214MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65221UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65338p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00x1C3A0R/W0x000000c004000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr65262P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr65273NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr65284I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr65296R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SETns_noc_io_pcie_soc_ip.csr65307DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr65319LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr65330BASE_ADDRESS_0_33Base address3960x300100000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65337UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65430p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00x1C3A8R/W0x000000fffc000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr65355P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr65366NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr65377I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr65388VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SETns_noc_io_pcie_soc_ip.csr65400TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr65411RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr65422MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65429UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65546p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00x1C3C0R/W0x000000c008000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr65470P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr65481NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr65492I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr65504R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SETns_noc_io_pcie_soc_ip.csr65515DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr65527LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr65538BASE_ADDRESS_0_33Base address3960x300200000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65545UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65638p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00x1C3C8R/W0x000000fff8000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr65563P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr65574NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr65585I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr65596VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SETns_noc_io_pcie_soc_ip.csr65608TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr65619RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr65630MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65637UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65754p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00x1C3E0R/W0x000000c010000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr65678P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr65689NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr65700I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr65712R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SETns_noc_io_pcie_soc_ip.csr65723DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr65735LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr65746BASE_ADDRESS_0_33Base address3960x300400000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65753UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65846p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00x1C3E8R/W0x000000fff0000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr65771P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr65782NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr65793I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr65804VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SETns_noc_io_pcie_soc_ip.csr65816TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr65827RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr65838MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65845UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr65962p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00x1C400R/W0x000000c020000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr65886P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr65897NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr65908I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr65920R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SETns_noc_io_pcie_soc_ip.csr65931DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr65943LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr65954BASE_ADDRESS_0_33Base address3960x300800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr65961UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66054p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00x1C408R/W0x000000ffe0000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr65979P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr65990NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr66001I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr66012VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SETns_noc_io_pcie_soc_ip.csr66024TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr66035RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr66046MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66053UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66170p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00x1C420R/W0x000000c040000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr66094P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr66105NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr66116I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SETns_noc_io_pcie_soc_ip.csr66128R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SETns_noc_io_pcie_soc_ip.csr66139DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SETns_noc_io_pcie_soc_ip.csr66151LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr66162BASE_ADDRESS_0_33Base address3960x301000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66169UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66262p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00x1C428R/W0x000000ffc0000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr66187P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr66198NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr66209I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SETns_noc_io_pcie_soc_ip.csr66220VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SETns_noc_io_pcie_soc_ip.csr66232TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SETns_noc_io_pcie_soc_ip.csr66243RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr66254MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66261UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66378p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00x1C440R/W0x000000c080000010Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr66302P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr66313NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr66324I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SETns_noc_io_pcie_soc_ip.csr66336R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SETns_noc_io_pcie_soc_ip.csr66347DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SETns_noc_io_pcie_soc_ip.csr66359LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr66370BASE_ADDRESS_0_33Base address3960x302000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66377UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66470p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00x1C448R/W0x000000ff80000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr66395P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr66406NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr66417I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SETns_noc_io_pcie_soc_ip.csr66428VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SETns_noc_io_pcie_soc_ip.csr66440TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SETns_noc_io_pcie_soc_ip.csr66451RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr66462MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66469UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66586p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00x1C460R/W0x000000c100000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr66510P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr66521NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr66532I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SETns_noc_io_pcie_soc_ip.csr66544R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SETns_noc_io_pcie_soc_ip.csr66555DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SETns_noc_io_pcie_soc_ip.csr66567LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr66578BASE_ADDRESS_0_33Base address3960x304000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66585UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66678p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00x1C468R/W0x000000ff00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr66603P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr66614NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr66625I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SETns_noc_io_pcie_soc_ip.csr66636VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SETns_noc_io_pcie_soc_ip.csr66648TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SETns_noc_io_pcie_soc_ip.csr66659RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr66670MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66677UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66794p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00x1C480R/W0x000000c200000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr66718P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr66729NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr66740I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SETns_noc_io_pcie_soc_ip.csr66752R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SETns_noc_io_pcie_soc_ip.csr66763DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SETns_noc_io_pcie_soc_ip.csr66775LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr66786BASE_ADDRESS_0_33Base address3960x308000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66793UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr66886p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00x1C488R/W0x000000fe00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr66811P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr66822NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr66833I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SETns_noc_io_pcie_soc_ip.csr66844VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SETns_noc_io_pcie_soc_ip.csr66856TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SETns_noc_io_pcie_soc_ip.csr66867RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr66878MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr66885UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67002p0_p0_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00x1C4A0R/W0x000000c400000000Pcie_noc_bridge_p0_p0_m_3_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr66926P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr66937NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr66948I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SETns_noc_io_pcie_soc_ip.csr66960R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SETns_noc_io_pcie_soc_ip.csr66971DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SETns_noc_io_pcie_soc_ip.csr66983LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr66994BASE_ADDRESS_0_33Base address3960x310000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr67001UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67094p0_p0_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00x1C4A8R/W0x000000fc00000000Pcie_noc_bridge_p0_p0_m_3_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr67019P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr67030NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr67041I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SETns_noc_io_pcie_soc_ip.csr67052VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SETns_noc_io_pcie_soc_ip.csr67064TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SETns_noc_io_pcie_soc_ip.csr67075RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr67086MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr67093UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_p_0bridge_p0_p0_m_3_6_p_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67159p0_p0_m register p_00x1F000R/W0x00000003Pcie_noc_bridge_p0_p0_m_3_6_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr67122WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr67134WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr67146WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr67158WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_p_1bridge_p0_p0_m_3_6_p_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67225p0_p0_m register p_10x1F008R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr67188WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr67200WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr67212WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr67224WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_p_2bridge_p0_p0_m_3_6_p_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67291p0_p0_m register p_20x1F010R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr67254WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr67266WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr67278WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr67290WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_p_3bridge_p0_p0_m_3_6_p_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67357p0_p0_m register p_30x1F018R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr67320WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr67332WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr67344WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr67356WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_txebridge_p0_p0_m_3_6_txePCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67503p0_p0_m register txe0x1F040R/W0x00000000Pcie_noc_bridge_p0_p0_m_3_6_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr67384TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr67396SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr67411TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr67424EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr67438FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr67452FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr67466FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr67480FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr67491PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr67502UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_txembridge_p0_p0_m_3_6_txemPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67582p0_p0_m register txem0x1F048R/W0x00000008Pcie_noc_bridge_p0_p0_m_3_6_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr67526UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr67537TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr67548EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr67559UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr67570PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr67581UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_btus_0bridge_p0_p0_m_3_6_btus_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr67950p0_p0_m register btus_00x1F058R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr67608L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr67619L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr67630L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr67641L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr67652L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr67663L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr67674L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr67685L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr67696L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr67707L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr67718L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr67729L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr67740L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr67751L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr67762L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr67773L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr67784L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr67795L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr67806L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr67817L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr67828L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr67839L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr67850L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr67861L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr67872L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr67883L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr67894L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr67905L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr67916L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr67927L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr67938L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr67949L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_p0_m_3_6_btus_1bridge_p0_p0_m_3_6_btus_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr68318p0_p0_m register btus_10x1F060R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr67976L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr67987L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr67998L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr68009L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr68020L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr68031L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr68042L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr68053L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr68064L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr68075L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr68086L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr68097L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr68108L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr68119L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr68130L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr68141L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr68152L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr68163L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr68174L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr68185L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr68196L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr68207L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr68218L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr68229L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr68240L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr68251L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr68262L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr68273L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr68284L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr68295L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr68306L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr68317L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_p0_m_3_6_btrl_0bridge_p0_p0_m_3_6_btrl_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr68394p0_p0_m register btrl_00x1F080R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr68342WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr68353RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr68368CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr68382EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr68393UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_m_3_6_btrl_1bridge_p0_p0_m_3_6_btrl_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr68470p0_p0_m register btrl_10x1F088R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr68418WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr68429RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr68444CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr68458EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr68469UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_m_3_6_btrl_2bridge_p0_p0_m_3_6_btrl_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr68546p0_p0_m register btrl_20x1F090R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr68494WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr68505RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr68520CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr68534EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr68545UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_m_3_6_btrl_3bridge_p0_p0_m_3_6_btrl_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr68622p0_p0_m register btrl_30x1F098R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr68570WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr68581RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr68596CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr68610EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr68621UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_m_3_6_btperrbridge_p0_p0_m_3_6_btperrPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr68824p0_p0_m register btperr0x1F0A8R/W0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr68647L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr68658L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr68669L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr68680L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr68691L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr68702L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr68713L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr68724L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr68735L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr68746L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr68757L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr68768L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr68779L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr68790L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr68801L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr68812L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr68823UNSD31160x0000Rregisterpcie_noc.bridge_p0_p0_m_3_6_btperrmbridge_p0_p0_m_3_6_btperrmPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr69024p0_p0_m register btperrm0x1F0B0R/W0x00000000Pcie_noc_bridge_p0_p0_m_3_6_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr68847L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr68858L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr68869L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr68880L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr68891L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr68902L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr68913L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr68924L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr68935L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr68946L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr68957L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr68968L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr68979L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr68990L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr69001L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr69012L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr69023UNSD31160x0000Rregisterpcie_noc.bridge_p0_p0_m_3_6_rxebridge_p0_p0_m_3_6_rxePCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr69132p0_p0_m register rxe0x1F120R/W0x00000000Pcie_noc_bridge_p0_p0_m_3_6_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr69052CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr69063CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr69074CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr69085CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr69097EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr69108PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr69120EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr69131UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_rxembridge_p0_p0_m_3_6_rxemPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr69204p0_p0_m register rxem0x1F128R/W0x00000050Pcie_noc_bridge_p0_p0_m_3_6_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr69153UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr69167EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr69178PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr69192EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr69203UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_brs_0bridge_p0_p0_m_3_6_brs_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr69478p0_p0_m register brs_00x1F130R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr69228OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr69239V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr69250S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr69261B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr69272F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr69282UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr69293OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr69304V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr69315S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr69326B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr69337F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr69347UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr69358OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr69369V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr69380S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr69391B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr69402F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr69412UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr69423OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr69434V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr69445S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr69456B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr69467F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr69477UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p0_m_3_6_brs_1bridge_p0_p0_m_3_6_brs_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr69752p0_p0_m register brs_10x1F138R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr69502OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr69513V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr69524S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr69535B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr69546F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr69556UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr69567OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr69578V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr69589S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr69600B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr69611F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr69621UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr69632OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr69643V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr69654S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr69665B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr69676F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr69686UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr69697OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr69708V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr69719S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr69730B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr69741F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr69751UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p0_m_3_6_brusbridge_p0_p0_m_3_6_brusPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr69821p0_p0_m register brus0x1F1B0R0x00000000Pcie_noc_bridge_p0_p0_m_3_6_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr69777V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr69788V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr69799V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr69810V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr69820UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_brperr0bridge_p0_p0_m_3_6_brperr0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70049p0_p0_m register brperr00x1F1D0R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr69859D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr69870DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr69881SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr69893SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr69904PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr69915UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr69926D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr69937DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr69948SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr69960SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr69971PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr69982UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr69993UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr70004UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr70015UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr70026UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr70037UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr70048UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_brperr1bridge_p0_p0_m_3_6_brperr1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70165p0_p0_m register brperr10x1F1D8R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr70087UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr70098UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr70109UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr70120UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr70131UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr70142UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr70153UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr70164UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_brperrm0bridge_p0_p0_m_3_6_brperrm0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70386p0_p0_m register brperrm00x1F1E0R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr70192D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr70204DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr70215SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr70227SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr70239PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr70250UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr70261D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr70273DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr70284SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr70296SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr70308PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr70319UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr70330UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr70341UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr70352UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr70363UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr70374UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr70385UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_brperrm1bridge_p0_p0_m_3_6_brperrm1PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70491p0_p0_m register brperrm10x1F1E8R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr70413UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr70424UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr70435UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr70446UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr70457UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr70468UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr70479UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr70490UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_tocfgbridge_p0_p0_m_3_6_am_tocfgPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70565p0_p0_m register am_tocfg0x1FC00R/W0x000000000000001fPcie_noc_bridge_p0_p0_m_3_6_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr70528TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr70539UNSD_7_6760x0RENPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr70553EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr70564UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_osslvbridge_p0_p0_m_3_6_am_osslvPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70600p0_p0_m register am_osslv0x1FC08R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr70588SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr70599UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_cgcbridge_p0_p0_m_3_6_am_cgcPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70637p0_p0_m register am_cgc0x1FC10R/W0x0000000000000064Pcie_noc_bridge_p0_p0_m_3_6_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr70625HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr70636UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_cgobridge_p0_p0_m_3_6_am_cgoPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70672p0_p0_m register am_cgo0x1FC18R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr70660FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr70671UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_cfgbridge_p0_p0_m_3_6_am_cfgPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70709p0_p0_m register am_cfg0x1FC20R/W0x0000000000000001Pcie_noc_bridge_p0_p0_m_3_6_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr70697AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr70708UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_stsbridge_p0_p0_m_3_6_am_stsPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70837p0_p0_m register am_sts0x1FD00R0x000000000000000cPcie_noc_bridge_p0_p0_m_3_6_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr70742ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr70756WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr70768ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr70780WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr70791ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr70802AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr70814ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr70826AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr70836UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_bridge_idbridge_p0_p0_m_3_6_am_bridge_idPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr70867p0_p0_m register am_bridge_id0x1FD08R0x0000000000000003Pcie_noc_bridge_p0_p0_m_3_6_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr70856IDUnique bridge ID1500x0003RUNSD_63_16PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr70866UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_errbridge_p0_p0_m_3_6_am_errPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71363p0_p0_m register am_err0x1FE00R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr70889E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr70901E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr70913E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr70925E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr70937E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr70949E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr70962E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr70975E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr70986E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr70997UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr71008E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr71019E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr71030E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr71041E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr71052E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr71063E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr71074E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr71086E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr71097E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr71108UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr71119E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr71130E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr71142E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr71154E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr71165UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr71177E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr71188E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr71199E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr71210E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr71221E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr71232E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr71243E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr71255E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr71267E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr71279E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr71291E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr71303E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr71315E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr71327E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr71339E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr71351E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr71362UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_toslvidbridge_p0_p0_m_3_6_am_toslvidPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71408p0_p0_m register am_toslvid0x1FE08R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr71386AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr71397AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr71407UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_erabridge_p0_p0_m_3_6_am_eraPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71430p0_p0_m register am_era0x1FE10R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr71429READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_ewabridge_p0_p0_m_3_6_am_ewaPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71452p0_p0_m register am_ewa0x1FE18R0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr71451WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_intmbridge_p0_p0_m_3_6_am_intmPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71936p0_p0_m register am_intm0x1FE40R/W0x00007e07004f004fPcie_noc_bridge_p0_p0_m_3_6_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr71474M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr71485M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr71496M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr71507M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr71518M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr71529M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr71540M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr71551M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr71562M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr71573UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr71584M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr71595M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr71606M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr71617M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr71628M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr71639M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr71650M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr71661M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr71672M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr71683UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr71694M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr71705M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr71716M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr71727M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr71738UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr71750M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr71761M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr71772M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr71783M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr71794M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr71805M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr71816M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr71828E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr71840E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr71852E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr71864E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr71876E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr71888E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr71900E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr71912E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr71924E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr71935UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_caddrbridge_p0_p0_m_3_6_am_caddrPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71958p0_p0_m register am_caddr0x1FF00R/W0xffffffffffffffffPcie_noc_bridge_p0_p0_m_3_6_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr71957CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_p0_p0_m_3_6_am_caddrmskbridge_p0_p0_m_3_6_am_caddrmskPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr71981p0_p0_m register am_caddrmsk0x1FF08R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr71980CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_p0_p0_m_3_6_am_ccmd0bridge_p0_p0_m_3_6_am_ccmd0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72171p0_p0_m register am_ccmd00x1FF10R/W0x0000000003fff33fPcie_noc_bridge_p0_p0_m_3_6_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr72003SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr72014DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr72025UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr72036BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr72047UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr72058CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr72069QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr72080PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr72091LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr72102RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr72113VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr72124UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr72136INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr72147UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr72159TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr72170UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk0bridge_p0_p0_m_3_6_am_ccmdmsk0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72315p0_p0_m register am_ccmdmsk00x1FF18R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr72193SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr72204DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr72215UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr72226BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr72237UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr72248CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr72259QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr72270PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr72281LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr72292RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr72303VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr72314UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_cntr0bridge_p0_p0_m_3_6_am_cntr0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72350p0_p0_m register am_cntr00x1FF20R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr72338CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr72349UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_latnum0bridge_p0_p0_m_3_6_am_latnum0PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72389p0_p0_m register am_latnum00x1FF28R/W0x0000000000000007Pcie_noc_bridge_p0_p0_m_3_6_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr72377CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr72388UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_ccmd1bridge_p0_p0_m_3_6_am_ccmd1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72579p0_p0_m register am_ccmd10x1FF30R/W0x0000000003fff33fPcie_noc_bridge_p0_p0_m_3_6_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr72411SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr72422DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr72433UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr72444BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr72455UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr72466CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr72477QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr72488PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr72499LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr72510RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr72521VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr72532UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr72544INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr72555UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr72567TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr72578UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_ccmdmsk1bridge_p0_p0_m_3_6_am_ccmdmsk1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72723p0_p0_m register am_ccmdmsk10x1FF38R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr72601SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr72612DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr72623UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr72634BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr72645UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr72656CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr72667QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr72678PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr72689LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr72700RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr72711VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr72722UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_cntr1bridge_p0_p0_m_3_6_am_cntr1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72758p0_p0_m register am_cntr10x1FF40R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr72746CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr72757UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_latnum1bridge_p0_p0_m_3_6_am_latnum1PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72797p0_p0_m register am_latnum10x1FF48R/W0x0000000000000007Pcie_noc_bridge_p0_p0_m_3_6_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr72785CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr72796UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_arovrdbridge_p0_p0_m_3_6_am_arovrdPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr72910p0_p0_m register am_arovrd0x1FF60R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr72815arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr72828arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr72839arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr72850UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr72863arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr72874UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr72885arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr72898arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr72909UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p0_m_3_6_am_awovrdbridge_p0_p0_m_3_6_am_awovrdPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73023p0_p0_m register am_awovrd0x1FF68R/W0x0000000000000000Pcie_noc_bridge_p0_p0_m_3_6_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr72928awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr72941awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr72952awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr72963UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr72976awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr72987UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr72998awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr73011awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P0_M_3_6_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr73022UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_cgcbridge_p0_p0_reg_s_9_6_as_cgcPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73060p0_p0_reg_s register as_cgc0x21C10R/W0x0000000000000064Pcie_noc_bridge_p0_p0_reg_s_9_6_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr73048HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr73059UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_cgobridge_p0_p0_reg_s_9_6_as_cgoPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73095p0_p0_reg_s register as_cgo0x21C18R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr73083FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr73094UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_stsbridge_p0_p0_reg_s_9_6_as_stsPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73169p0_p0_reg_s register as_sts0x21D00R0x000000000000000cPcie_noc_bridge_p0_p0_reg_s_9_6_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr73118WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr73134ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr73146WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr73158ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr73168UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_bridge_idbridge_p0_p0_reg_s_9_6_as_bridge_idPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73199p0_p0_reg_s register as_bridge_id0x21D08R0x0000000000000009Pcie_noc_bridge_p0_p0_reg_s_9_6_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr73188IDUnique bridge ID1500x0009RUNSD_63_16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr73198UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_errbridge_p0_p0_reg_s_9_6_as_errPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73552p0_p0_reg_s register as_err0x21E00R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr73220E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr73232E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr73245E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr73259E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr73271E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr73282UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr73294E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr73306E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr73319E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr73331E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr73342UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr73354E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr73365E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr73376E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr73387E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr73398E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr73409E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr73420E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr73432E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr73444E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr73456E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr73468E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr73480E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr73492E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr73504E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr73516E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr73528E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr73540E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr73551UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_intmbridge_p0_p0_reg_s_9_6_as_intmPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73892p0_p0_reg_s register as_intm0x21E40R/W0x0000007d000b0013Pcie_noc_bridge_p0_p0_reg_s_9_6_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr73573M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr73584M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr73595M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr73606M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr73617M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr73628UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr73639M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr73650M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr73661M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr73672M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr73683UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr73694M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr73705M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr73716M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr73727M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr73738M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr73749M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr73760M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr73772E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr73784E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr73796E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr73808E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr73820E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr73832E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr73844E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr73856E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr73868E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr73880E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr73891UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdbridge_p0_p0_reg_s_9_6_as_ccmdPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr73967p0_p0_reg_s register as_ccmd0x21F00R/W0x0000000003000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr73910UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr73921rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr73932val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr73943UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr73955intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr73966UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_ccmdmskbridge_p0_p0_reg_s_9_6_as_ccmdmskPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74019p0_p0_reg_s register as_ccmdmsk0x21F08R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr73985UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr73996rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr74007val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr74018UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_cntrbridge_p0_p0_reg_s_9_6_as_cntrPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74049p0_p0_reg_s register as_cntr0x21F10R0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr74038CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr74048UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_arovrdbridge_p0_p0_reg_s_9_6_as_arovrdPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74162p0_p0_reg_s register as_arovrd0x21F18R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr74067arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr74080arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr74091arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr74102UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr74115arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr74126UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr74137arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr74150arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr74161UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_as_awovrdbridge_p0_p0_reg_s_9_6_as_awovrdPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74275p0_p0_reg_s register as_awovrd0x21F20R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr74180awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr74193awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr74204awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr74215UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr74228awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr74239UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr74250awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr74263awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr74274UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_p_0bridge_p0_p0_reg_s_9_6_p_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74340p0_p0_reg_s register p_00x23000R/W0x00000003Pcie_noc_bridge_p0_p0_reg_s_9_6_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr74303WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr74315WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr74327WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr74339WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_p_1bridge_p0_p0_reg_s_9_6_p_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74406p0_p0_reg_s register p_10x23008R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr74369WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr74381WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr74393WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr74405WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_p_2bridge_p0_p0_reg_s_9_6_p_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74472p0_p0_reg_s register p_20x23010R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr74435WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr74447WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr74459WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr74471WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_p_3bridge_p0_p0_reg_s_9_6_p_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74538p0_p0_reg_s register p_30x23018R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr74501WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr74513WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr74525WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr74537WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_txebridge_p0_p0_reg_s_9_6_txePCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74684p0_p0_reg_s register txe0x23040R/W0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr74565TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr74577SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr74592TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr74605EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr74619FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr74633FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr74647FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr74661FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr74672PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr74683UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_txembridge_p0_p0_reg_s_9_6_txemPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr74763p0_p0_reg_s register txem0x23048R/W0x00000008Pcie_noc_bridge_p0_p0_reg_s_9_6_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr74707UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr74718TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr74729EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr74740UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr74751PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr74762UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btus_0bridge_p0_p0_reg_s_9_6_btus_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr75131p0_p0_reg_s register btus_00x23058R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr74789L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr74800L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr74811L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr74822L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr74833L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr74844L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr74855L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr74866L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr74877L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr74888L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr74899L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr74910L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr74921L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr74932L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr74943L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr74954L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr74965L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr74976L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr74987L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr74998L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr75009L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr75020L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr75031L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr75042L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr75053L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr75064L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr75075L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr75086L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr75097L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr75108L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr75119L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr75130L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btus_1bridge_p0_p0_reg_s_9_6_btus_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr75499p0_p0_reg_s register btus_10x23060R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr75157L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr75168L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr75179L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr75190L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr75201L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr75212L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr75223L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr75234L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr75245L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr75256L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr75267L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr75278L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr75289L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr75300L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr75311L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr75322L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr75333L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr75344L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr75355L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr75366L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr75377L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr75388L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr75399L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr75410L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr75421L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr75432L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr75443L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr75454L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr75465L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr75476L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr75487L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr75498L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btrl_0bridge_p0_p0_reg_s_9_6_btrl_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr75575p0_p0_reg_s register btrl_00x23080R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr75523WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr75534RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr75549CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr75563EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr75574UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btrl_1bridge_p0_p0_reg_s_9_6_btrl_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr75651p0_p0_reg_s register btrl_10x23088R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr75599WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr75610RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr75625CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr75639EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr75650UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btrl_2bridge_p0_p0_reg_s_9_6_btrl_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr75727p0_p0_reg_s register btrl_20x23090R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr75675WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr75686RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr75701CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr75715EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr75726UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btrl_3bridge_p0_p0_reg_s_9_6_btrl_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr75803p0_p0_reg_s register btrl_30x23098R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr75751WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr75762RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr75777CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr75791EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr75802UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btperrbridge_p0_p0_reg_s_9_6_btperrPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr76005p0_p0_reg_s register btperr0x230A8R/W0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr75828L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr75839L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr75850L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr75861L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr75872L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr75883L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr75894L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr75905L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr75916L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr75927L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr75938L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr75949L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr75960L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr75971L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr75982L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr75993L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr76004UNSD31160x0000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_btperrmbridge_p0_p0_reg_s_9_6_btperrmPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr76205p0_p0_reg_s register btperrm0x230B0R/W0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr76028L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr76039L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr76050L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr76061L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr76072L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr76083L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr76094L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr76105L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr76116L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr76127L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr76138L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr76149L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr76160L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr76171L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr76182L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr76193L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr76204UNSD31160x0000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_rxebridge_p0_p0_reg_s_9_6_rxePCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr76313p0_p0_reg_s register rxe0x23120R/W0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr76233CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr76244CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr76255CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr76266CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr76278EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr76289PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr76301EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr76312UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_rxembridge_p0_p0_reg_s_9_6_rxemPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr76385p0_p0_reg_s register rxem0x23128R/W0x00000050Pcie_noc_bridge_p0_p0_reg_s_9_6_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr76334UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr76348EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr76359PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr76373EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr76384UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brs_0bridge_p0_p0_reg_s_9_6_brs_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr76659p0_p0_reg_s register brs_00x23130R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr76409OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr76420V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr76431S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr76442B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr76453F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr76463UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr76474OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr76485V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr76496S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr76507B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr76518F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr76528UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr76539OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr76550V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr76561S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr76572B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr76583F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr76593UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr76604OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr76615V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr76626S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr76637B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr76648F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr76658UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brs_1bridge_p0_p0_reg_s_9_6_brs_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr76933p0_p0_reg_s register brs_10x23138R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr76683OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr76694V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr76705S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr76716B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr76727F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr76737UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr76748OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr76759V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr76770S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr76781B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr76792F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr76802UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr76813OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr76824V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr76835S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr76846B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr76857F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr76867UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr76878OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr76889V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr76900S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr76911B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr76922F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr76932UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brusbridge_p0_p0_reg_s_9_6_brusPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77002p0_p0_reg_s register brus0x231B0R0x00000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr76958V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr76969V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr76980V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr76991V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr77001UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brperr0bridge_p0_p0_reg_s_9_6_brperr0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77230p0_p0_reg_s register brperr00x231D0R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr77040D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr77051DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr77062SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr77074SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr77085PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr77096UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr77107D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr77118DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr77129SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr77141SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr77152PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr77163UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr77174UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr77185UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr77196UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr77207UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr77218UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr77229UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brperr1bridge_p0_p0_reg_s_9_6_brperr1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77346p0_p0_reg_s register brperr10x231D8R0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr77268UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr77279UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr77290UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr77301UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr77312UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr77323UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr77334UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr77345UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brperrm0bridge_p0_p0_reg_s_9_6_brperrm0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77567p0_p0_reg_s register brperrm00x231E0R/W0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr77373D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr77385DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr77396SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr77408SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr77420PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr77431UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr77442D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr77454DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr77465SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr77477SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr77489PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr77500UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr77511UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr77522UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr77533UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr77544UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr77555UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr77566UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_reg_s_9_6_brperrm1bridge_p0_p0_reg_s_9_6_brperrm1PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77672p0_p0_reg_s register brperrm10x231E8R0x0000000000000000Pcie_noc_bridge_p0_p0_reg_s_9_6_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr77594UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr77605UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr77616UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr77627UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr77638UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr77649UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr77660UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_REG_S_9_6_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr77671UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_cgcbridge_p0_p0_s_10_7_as_cgcPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77709p0_p0_s register as_cgc0x25C10R/W0x0000000000000064Pcie_noc_bridge_p0_p0_s_10_7_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr77697HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr77708UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_cgobridge_p0_p0_s_10_7_as_cgoPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77744p0_p0_s register as_cgo0x25C18R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr77732FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr77743UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_stsbridge_p0_p0_s_10_7_as_stsPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77818p0_p0_s register as_sts0x25D00R0x000000000000000cPcie_noc_bridge_p0_p0_s_10_7_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr77767WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr77783ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr77795WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr77807ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr77817UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_bridge_idbridge_p0_p0_s_10_7_as_bridge_idPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr77848p0_p0_s register as_bridge_id0x25D08R0x000000000000000aPcie_noc_bridge_p0_p0_s_10_7_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr77837IDUnique bridge ID1500x000aRUNSD_63_16PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr77847UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_errbridge_p0_p0_s_10_7_as_errPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78201p0_p0_s register as_err0x25E00R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr77869E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr77881E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr77894E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr77908E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr77920E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr77931UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr77943E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr77955E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr77968E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr77980E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr77991UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr78003E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr78014E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr78025E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr78036E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr78047E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr78058E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr78069E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr78081E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr78093E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr78105E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr78117E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr78129E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr78141E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr78153E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr78165E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr78177E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr78189E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr78200UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_intmbridge_p0_p0_s_10_7_as_intmPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78541p0_p0_s register as_intm0x25E40R/W0x0000007d000b0013Pcie_noc_bridge_p0_p0_s_10_7_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr78222M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr78233M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr78244M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr78255M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr78266M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr78277UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr78288M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr78299M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr78310M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr78321M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr78332UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr78343M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr78354M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr78365M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr78376M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr78387M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr78398M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr78409M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr78421E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr78433E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr78445E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr78457E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr78469E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr78481E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr78493E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr78505E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr78517E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr78529E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr78540UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_ccmdbridge_p0_p0_s_10_7_as_ccmdPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78616p0_p0_s register as_ccmd0x25F00R/W0x0000000003000000Pcie_noc_bridge_p0_p0_s_10_7_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr78559UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr78570rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr78581val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr78592UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr78604intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr78615UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_ccmdmskbridge_p0_p0_s_10_7_as_ccmdmskPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78668p0_p0_s register as_ccmdmsk0x25F08R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr78634UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr78645rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr78656val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr78667UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_cntrbridge_p0_p0_s_10_7_as_cntrPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78698p0_p0_s register as_cntr0x25F10R0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr78687CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr78697UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_arovrdbridge_p0_p0_s_10_7_as_arovrdPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78811p0_p0_s register as_arovrd0x25F18R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr78716arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr78729arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr78740arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr78751UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr78764arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr78775UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr78786arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr78799arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr78810UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_as_awovrdbridge_p0_p0_s_10_7_as_awovrdPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78924p0_p0_s register as_awovrd0x25F20R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr78829awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr78842awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr78853awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr78864UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr78877awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr78888UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr78899awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr78912awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr78923UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_p_0bridge_p0_p0_s_10_7_p_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr78989p0_p0_s register p_00x27000R/W0x00000003Pcie_noc_bridge_p0_p0_s_10_7_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr78952WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr78964WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr78976WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr78988WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_p_1bridge_p0_p0_s_10_7_p_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr79055p0_p0_s register p_10x27008R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr79018WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr79030WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr79042WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr79054WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_p_2bridge_p0_p0_s_10_7_p_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr79121p0_p0_s register p_20x27010R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr79084WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr79096WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr79108WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr79120WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_p_3bridge_p0_p0_s_10_7_p_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr79187p0_p0_s register p_30x27018R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr79150WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr79162WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr79174WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr79186WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_txebridge_p0_p0_s_10_7_txePCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr79333p0_p0_s register txe0x27040R/W0x00000000Pcie_noc_bridge_p0_p0_s_10_7_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr79214TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr79226SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr79241TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr79254EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr79268FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr79282FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr79296FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr79310FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr79321PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr79332UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_txembridge_p0_p0_s_10_7_txemPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr79412p0_p0_s register txem0x27048R/W0x00000008Pcie_noc_bridge_p0_p0_s_10_7_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr79356UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr79367TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr79378EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr79389UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr79400PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr79411UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_btus_0bridge_p0_p0_s_10_7_btus_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr79780p0_p0_s register btus_00x27058R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr79438L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr79449L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr79460L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr79471L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr79482L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr79493L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr79504L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr79515L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr79526L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr79537L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr79548L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr79559L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr79570L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr79581L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr79592L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr79603L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr79614L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr79625L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr79636L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr79647L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr79658L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr79669L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr79680L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr79691L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr79702L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr79713L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr79724L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr79735L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr79746L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr79757L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr79768L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr79779L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_p0_s_10_7_btus_1bridge_p0_p0_s_10_7_btus_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80148p0_p0_s register btus_10x27060R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr79806L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr79817L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr79828L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr79839L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr79850L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr79861L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr79872L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr79883L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr79894L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr79905L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr79916L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr79927L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr79938L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr79949L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr79960L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr79971L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr79982L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr79993L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr80004L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr80015L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr80026L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr80037L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr80048L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr80059L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr80070L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr80081L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr80092L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr80103L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr80114L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr80125L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr80136L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr80147L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_p0_s_10_7_btrl_0bridge_p0_p0_s_10_7_btrl_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80224p0_p0_s register btrl_00x27080R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr80172WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr80183RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr80198CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr80212EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr80223UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_s_10_7_btrl_1bridge_p0_p0_s_10_7_btrl_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80300p0_p0_s register btrl_10x27088R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr80248WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr80259RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr80274CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr80288EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr80299UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_s_10_7_btrl_2bridge_p0_p0_s_10_7_btrl_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80376p0_p0_s register btrl_20x27090R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr80324WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr80335RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr80350CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr80364EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr80375UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_s_10_7_btrl_3bridge_p0_p0_s_10_7_btrl_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80452p0_p0_s register btrl_30x27098R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr80400WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr80411RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr80426CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr80440EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr80451UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p0_s_10_7_btperrbridge_p0_p0_s_10_7_btperrPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80654p0_p0_s register btperr0x270A8R/W0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr80477L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr80488L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr80499L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr80510L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr80521L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr80532L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr80543L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr80554L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr80565L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr80576L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr80587L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr80598L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr80609L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr80620L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr80631L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr80642L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr80653UNSD31160x0000Rregisterpcie_noc.bridge_p0_p0_s_10_7_btperrmbridge_p0_p0_s_10_7_btperrmPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80854p0_p0_s register btperrm0x270B0R/W0x00000000Pcie_noc_bridge_p0_p0_s_10_7_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr80677L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr80688L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr80699L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr80710L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr80721L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr80732L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr80743L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr80754L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr80765L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr80776L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr80787L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr80798L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr80809L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr80820L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr80831L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr80842L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr80853UNSD31160x0000Rregisterpcie_noc.bridge_p0_p0_s_10_7_rxebridge_p0_p0_s_10_7_rxePCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr80962p0_p0_s register rxe0x27120R/W0x00000000Pcie_noc_bridge_p0_p0_s_10_7_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr80882CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr80893CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr80904CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr80915CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr80927EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr80938PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr80950EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr80961UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_rxembridge_p0_p0_s_10_7_rxemPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr81034p0_p0_s register rxem0x27128R/W0x00000050Pcie_noc_bridge_p0_p0_s_10_7_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr80983UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr80997EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr81008PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr81022EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr81033UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_brs_0bridge_p0_p0_s_10_7_brs_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr81308p0_p0_s register brs_00x27130R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr81058OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr81069V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr81080S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr81091B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr81102F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr81112UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr81123OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr81134V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr81145S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr81156B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr81167F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr81177UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr81188OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr81199V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr81210S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr81221B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr81232F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr81242UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr81253OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr81264V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr81275S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr81286B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr81297F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr81307UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p0_s_10_7_brs_1bridge_p0_p0_s_10_7_brs_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr81582p0_p0_s register brs_10x27138R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr81332OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr81343V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr81354S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr81365B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr81376F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr81386UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr81397OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr81408V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr81419S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr81430B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr81441F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr81451UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr81462OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr81473V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr81484S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr81495B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr81506F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr81516UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr81527OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr81538V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr81549S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr81560B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr81571F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr81581UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p0_s_10_7_brusbridge_p0_p0_s_10_7_brusPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr81651p0_p0_s register brus0x271B0R0x00000000Pcie_noc_bridge_p0_p0_s_10_7_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr81607V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr81618V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr81629V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr81640V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr81650UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_p0_s_10_7_brperr0bridge_p0_p0_s_10_7_brperr0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr81879p0_p0_s register brperr00x271D0R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr81689D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr81700DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr81711SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr81723SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr81734PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr81745UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr81756D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr81767DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr81778SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr81790SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr81801PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr81812UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr81823UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr81834UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr81845UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr81856UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr81867UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr81878UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_brperr1bridge_p0_p0_s_10_7_brperr1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr81995p0_p0_s register brperr10x271D8R0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr81917UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr81928UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr81939UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr81950UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr81961UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr81972UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr81983UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr81994UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_brperrm0bridge_p0_p0_s_10_7_brperrm0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82216p0_p0_s register brperrm00x271E0R/W0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr82022D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr82034DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr82045SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr82057SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr82069PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr82080UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr82091D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr82103DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr82114SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr82126SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr82138PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr82149UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr82160UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr82171UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr82182UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr82193UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr82204UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr82215UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p0_s_10_7_brperrm1bridge_p0_p0_s_10_7_brperrm1PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82321p0_p0_s register brperrm10x271E8R0x0000000000000000Pcie_noc_bridge_p0_p0_s_10_7_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr82243UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr82254UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr82265UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr82276UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr82287UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr82298UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr82309UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P0_S_10_7_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr82320UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82437p0_p1_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x28000R/W0x0000000058200010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr82361P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr82372NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr82383I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr82395R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr82406DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr82418LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr82429BASE_ADDRESS_0_33Base address3960x001608000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr82436UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82529p0_p1_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x28008R/W0x000000fffffff000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr82454P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr82465NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr82476I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr82487VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr82499TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr82510RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr82521MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr82528UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82645p0_p1_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x28020R/W0x0000007f80000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr82569P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr82580NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr82591I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr82603R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr82614DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr82626LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr82637BASE_ADDRESS_0_33Base address3960x1fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr82644UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82737p0_p1_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x28028R/W0x000000fffffff000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr82662P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr82673NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr82684I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr82695VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr82707TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr82718RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr82729MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr82736UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82778p0_p1_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x28030R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr82755UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr82766SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr82777UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82894p0_p1_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x28040R/W0x0000007f80001010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr82818P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr82829NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr82840I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr82852R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr82863DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr82875LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr82886BASE_ADDRESS_0_33Base address3960x1fe000040R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr82893UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr82986p0_p1_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x28048R/W0x000000fffffff000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr82911P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr82922NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr82933I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr82944VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr82956TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr82967RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr82978MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr82985UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83027p0_p1_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x28050R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr83004UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr83015SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SETns_noc_io_pcie_soc_ip.csr83026UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83143p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00x28060R/W0x0000000080000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr83067P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr83078NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr83089I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr83101R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr83112DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr83124LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr83135BASE_ADDRESS_0_33Base address3960x002000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83142UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83235p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_00x28068R/W0x000000ff80000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_2g__4g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr83160P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr83171NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr83182I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr83193VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr83205TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr83216RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr83227MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_2G__4G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83234UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83351p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00x28080R/W0x0000008000200010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr83275P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr83286NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr83297I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr83309R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_DI_SETns_noc_io_pcie_soc_ip.csr83320DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr83332LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr83343BASE_ADDRESS_0_33Base address3960x200008000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83350UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83443p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_00x28088R/W0x000000ffffe00000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_2m__512g_4m__2m_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_P_SETns_noc_io_pcie_soc_ip.csr83368P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_NS_SETns_noc_io_pcie_soc_ip.csr83379NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_I_SETns_noc_io_pcie_soc_ip.csr83390I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr83401VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_TM_SETns_noc_io_pcie_soc_ip.csr83413TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr83424RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr83435MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_2M__512G_4M__2M_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83442UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83559p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00x280A0R/W0x0000008000400010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr83483P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr83494NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr83505I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr83517R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_DI_SETns_noc_io_pcie_soc_ip.csr83528DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr83540LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr83551BASE_ADDRESS_0_33Base address3960x200010000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83558UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83651p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_00x280A8R/W0x000000ffffc00000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_4m__512g_8m__4m_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_P_SETns_noc_io_pcie_soc_ip.csr83576P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_NS_SETns_noc_io_pcie_soc_ip.csr83587NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_I_SETns_noc_io_pcie_soc_ip.csr83598I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr83609VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_TM_SETns_noc_io_pcie_soc_ip.csr83621TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr83632RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr83643MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_4M__512G_8M__4M_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83650UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83767p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00x280C0R/W0x0000008000800010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr83691P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr83702NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr83713I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr83725R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_DI_SETns_noc_io_pcie_soc_ip.csr83736DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr83748LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr83759BASE_ADDRESS_0_33Base address3960x200020000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83766UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83859p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_00x280C8R/W0x000000ffff800000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_8m__512g_16m__8m_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_P_SETns_noc_io_pcie_soc_ip.csr83784P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_NS_SETns_noc_io_pcie_soc_ip.csr83795NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_I_SETns_noc_io_pcie_soc_ip.csr83806I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr83817VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_TM_SETns_noc_io_pcie_soc_ip.csr83829TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr83840RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr83851MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_8M__512G_16M__8M_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83858UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr83975p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00x280E0R/W0x0000008001000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr83899P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr83910NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr83921I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr83933R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_DI_SETns_noc_io_pcie_soc_ip.csr83944DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr83956LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr83967BASE_ADDRESS_0_33Base address3960x200040000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr83974UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84067p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_00x280E8R/W0x000000ffff000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_16m__512g_32m__16m_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_P_SETns_noc_io_pcie_soc_ip.csr83992P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr84003NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_I_SETns_noc_io_pcie_soc_ip.csr84014I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr84025VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_TM_SETns_noc_io_pcie_soc_ip.csr84037TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr84048RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr84059MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_16M__512G_32M__16M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84066UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84183p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00x28100R/W0x0000008002000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr84107P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr84118NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr84129I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr84141R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_DI_SETns_noc_io_pcie_soc_ip.csr84152DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr84164LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr84175BASE_ADDRESS_0_33Base address3960x200080000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84182UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84275p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_00x28108R/W0x000000fffe000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_32m__512g_64m__32m_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_P_SETns_noc_io_pcie_soc_ip.csr84200P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_NS_SETns_noc_io_pcie_soc_ip.csr84211NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_I_SETns_noc_io_pcie_soc_ip.csr84222I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr84233VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_TM_SETns_noc_io_pcie_soc_ip.csr84245TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr84256RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr84267MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_32M__512G_64M__32M_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84274UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84391p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00x28120R/W0x0000008004000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr84315P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr84326NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr84337I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr84349R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr84360DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr84372LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr84383BASE_ADDRESS_0_33Base address3960x200100000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84390UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84483p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_00x28128R/W0x000000fffc000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_64m__512g_128m__64m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_P_SETns_noc_io_pcie_soc_ip.csr84408P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr84419NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_I_SETns_noc_io_pcie_soc_ip.csr84430I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr84441VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr84453TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr84464RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr84475MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_64M__512G_128M__64M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84482UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84599p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00x28140R/W0x0000008008000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr84523P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr84534NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr84545I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr84557R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr84568DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr84580LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr84591BASE_ADDRESS_0_33Base address3960x200200000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84598UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84691p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_00x28148R/W0x000000fff8000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_128m__512g_256m__128m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_P_SETns_noc_io_pcie_soc_ip.csr84616P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr84627NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_I_SETns_noc_io_pcie_soc_ip.csr84638I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr84649VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr84661TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr84672RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr84683MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_128M__512G_256M__128M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84690UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84807p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00x28160R/W0x0000008010000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr84731P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr84742NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr84753I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr84765R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr84776DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr84788LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr84799BASE_ADDRESS_0_33Base address3960x200400000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84806UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr84899p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_00x28168R/W0x000000fff0000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_256m__512g_512m__256m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_P_SETns_noc_io_pcie_soc_ip.csr84824P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr84835NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_I_SETns_noc_io_pcie_soc_ip.csr84846I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr84857VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr84869TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr84880RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr84891MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_256M__512G_512M__256M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr84898UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85015p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00x28180R/W0x0000008020000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr84939P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr84950NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr84961I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr84973R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr84984DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr84996LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr85007BASE_ADDRESS_0_33Base address3960x200800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85014UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85107p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_00x28188R/W0x000000ffe0000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_512g_512m__513g__512m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_P_SETns_noc_io_pcie_soc_ip.csr85032P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr85043NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_I_SETns_noc_io_pcie_soc_ip.csr85054I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr85065VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr85077TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr85088RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr85099MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_512G_512M__513G__512M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85106UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85223p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00x281A0R/W0x0000008040000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr85147P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr85158NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr85169I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr85181R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_DI_SETns_noc_io_pcie_soc_ip.csr85192DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr85204LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr85215BASE_ADDRESS_0_33Base address3960x201000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85222UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85315p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_00x281A8R/W0x000000ffc0000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_513g__514g__1g_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_P_SETns_noc_io_pcie_soc_ip.csr85240P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_NS_SETns_noc_io_pcie_soc_ip.csr85251NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_I_SETns_noc_io_pcie_soc_ip.csr85262I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr85273VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_TM_SETns_noc_io_pcie_soc_ip.csr85285TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr85296RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr85307MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_513G__514G__1G_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85314UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85431p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00x281C0R/W0x0000008080000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr85355P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr85366NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr85377I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr85389R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_DI_SETns_noc_io_pcie_soc_ip.csr85400DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr85412LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr85423BASE_ADDRESS_0_33Base address3960x202000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85430UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85523p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_00x281C8R/W0x000000ff80000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_514g__516g__2g_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_P_SETns_noc_io_pcie_soc_ip.csr85448P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_NS_SETns_noc_io_pcie_soc_ip.csr85459NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_I_SETns_noc_io_pcie_soc_ip.csr85470I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr85481VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_TM_SETns_noc_io_pcie_soc_ip.csr85493TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr85504RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr85515MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_514G__516G__2G_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85522UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85639p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00x281E0R/W0x0000008100000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr85563P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr85574NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr85585I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr85597R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_DI_SETns_noc_io_pcie_soc_ip.csr85608DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr85620LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr85631BASE_ADDRESS_0_33Base address3960x204000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85638UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85731p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_00x281E8R/W0x000000ff00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_516g__520g__4g_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_P_SETns_noc_io_pcie_soc_ip.csr85656P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_NS_SETns_noc_io_pcie_soc_ip.csr85667NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_I_SETns_noc_io_pcie_soc_ip.csr85678I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr85689VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_TM_SETns_noc_io_pcie_soc_ip.csr85701TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr85712RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr85723MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_516G__520G__4G_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85730UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85847p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00x28200R/W0x0000008200000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr85771P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr85782NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr85793I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr85805R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_DI_SETns_noc_io_pcie_soc_ip.csr85816DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr85828LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr85839BASE_ADDRESS_0_33Base address3960x208000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85846UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr85939p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_00x28208R/W0x000000fe00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_520g__528g__8g_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_P_SETns_noc_io_pcie_soc_ip.csr85864P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_NS_SETns_noc_io_pcie_soc_ip.csr85875NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_I_SETns_noc_io_pcie_soc_ip.csr85886I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr85897VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_TM_SETns_noc_io_pcie_soc_ip.csr85909TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr85920RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr85931MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_520G__528G__8G_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr85938UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86055p0_p1_m register am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00x28220R/W0x0000008400000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr85979P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr85990NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr86001I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr86013R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_DI_SETns_noc_io_pcie_soc_ip.csr86024DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr86036LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr86047BASE_ADDRESS_0_33Base address3960x210000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86054UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86147p0_p1_m register am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_00x28228R/W0x000000fc00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tol3_s_sr_main0_tol3_s_map_r_528g__544g__16g_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_P_SETns_noc_io_pcie_soc_ip.csr86072P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_NS_SETns_noc_io_pcie_soc_ip.csr86083NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_I_SETns_noc_io_pcie_soc_ip.csr86094I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr86105VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_TM_SETns_noc_io_pcie_soc_ip.csr86117TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr86128RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr86139MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOL3_S_SR_MAIN0_TOL3_S_MAP_R_528G__544G__16G_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86146UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86263p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00x28240R/W0x0000000002000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr86187P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr86198NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr86209I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr86221R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr86232DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr86244LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr86255BASE_ADDRESS_0_33Base address3960x000080000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86262UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86355p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_00x28248R/W0x000000ffffff0000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_32m__32m_64k__64k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_P_SETns_noc_io_pcie_soc_ip.csr86280P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr86291NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_I_SETns_noc_io_pcie_soc_ip.csr86302I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr86313VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr86325TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr86336RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr86347MASK_0_33Mask3960x3fffffc00R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_32M__32M_64K__64K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86354UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86471p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00x28260R/W0x0000000020007000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr86395P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr86406NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr86417I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr86429R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr86440DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr86452LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr86463BASE_ADDRESS_0_33Base address3960x0008001c0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86470UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86563p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_00x28268R/W0x000000fffffff000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_512m_28k__512m_32k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr86488P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr86499NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr86510I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr86521VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr86533TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr86544RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr86555MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_512M_28K__512M_32K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86562UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86679p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00x28280R/W0x0000000030001000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr86603P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr86614NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr86625I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr86637R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr86648DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr86660LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr86671BASE_ADDRESS_0_33Base address3960x000c00040R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86678UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86771p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_00x28288R/W0x000000fffffff000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_4k__768m_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr86696P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr86707NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr86718I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr86729VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr86741TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr86752RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr86763MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_4K__768M_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86770UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86887p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00x282A0R/W0x0000000030003000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr86811P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr86822NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr86833I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr86845R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_DI_SETns_noc_io_pcie_soc_ip.csr86856DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr86868LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr86879BASE_ADDRESS_0_33Base address3960x000c000c0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86886UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr86979p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_00x282A8R/W0x000000fffffff000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_12k__768m_16k__4k_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr86904P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr86915NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr86926I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr86937VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_TM_SETns_noc_io_pcie_soc_ip.csr86949TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr86960RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr86971MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_12K__768M_16K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr86978UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87095p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00x282C0R/W0x0000000030008000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr87019P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr87030NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr87041I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr87053R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_DI_SETns_noc_io_pcie_soc_ip.csr87064DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr87076LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr87087BASE_ADDRESS_0_33Base address3960x000c00200R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87094UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87187p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_00x282C8R/W0x000000ffffffe000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768m_32k__768m_40k__8k_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_P_SETns_noc_io_pcie_soc_ip.csr87112P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_NS_SETns_noc_io_pcie_soc_ip.csr87123NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_I_SETns_noc_io_pcie_soc_ip.csr87134I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr87145VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_TM_SETns_noc_io_pcie_soc_ip.csr87157TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr87168RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr87179MASK_0_33Mask3960x3ffffff80R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768M_32K__768M_40K__8K_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87186UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87303p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00x282E0R/W0x0000000100000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr87227P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr87238NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr87249I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_R_WN_SETns_noc_io_pcie_soc_ip.csr87261R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_DI_SETns_noc_io_pcie_soc_ip.csr87272DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_LLC_SETns_noc_io_pcie_soc_ip.csr87284LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr87295BASE_ADDRESS_0_33Base address3960x004000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87302UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87395p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_00x282E8R/W0x000000ff00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_4g__8g__4g_5_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_P_SETns_noc_io_pcie_soc_ip.csr87320P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_NS_SETns_noc_io_pcie_soc_ip.csr87331NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_I_SETns_noc_io_pcie_soc_ip.csr87342I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_VAL_SETns_noc_io_pcie_soc_ip.csr87353VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_TM_SETns_noc_io_pcie_soc_ip.csr87365TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_RSV_SETns_noc_io_pcie_soc_ip.csr87376RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr87387MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_4G__8G__4G_5_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87394UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87511p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00x28300R/W0x000000c000200010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr87435P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr87446NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr87457I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_R_WN_SETns_noc_io_pcie_soc_ip.csr87469R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_DI_SETns_noc_io_pcie_soc_ip.csr87480DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_LLC_SETns_noc_io_pcie_soc_ip.csr87492LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr87503BASE_ADDRESS_0_33Base address3960x300008000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87510UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87603p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_00x28308R/W0x000000ffffe00000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_2m__768g_4m__2m_6_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_P_SETns_noc_io_pcie_soc_ip.csr87528P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_NS_SETns_noc_io_pcie_soc_ip.csr87539NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_I_SETns_noc_io_pcie_soc_ip.csr87550I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_VAL_SETns_noc_io_pcie_soc_ip.csr87561VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_TM_SETns_noc_io_pcie_soc_ip.csr87573TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_RSV_SETns_noc_io_pcie_soc_ip.csr87584RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr87595MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_2M__768G_4M__2M_6_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87602UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87719p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00x28320R/W0x000000c000400010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr87643P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr87654NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr87665I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_R_WN_SETns_noc_io_pcie_soc_ip.csr87677R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_DI_SETns_noc_io_pcie_soc_ip.csr87688DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_LLC_SETns_noc_io_pcie_soc_ip.csr87700LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr87711BASE_ADDRESS_0_33Base address3960x300010000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87718UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87811p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_00x28328R/W0x000000ffffc00000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_4m__768g_8m__4m_7_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_P_SETns_noc_io_pcie_soc_ip.csr87736P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_NS_SETns_noc_io_pcie_soc_ip.csr87747NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_I_SETns_noc_io_pcie_soc_ip.csr87758I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_VAL_SETns_noc_io_pcie_soc_ip.csr87769VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_TM_SETns_noc_io_pcie_soc_ip.csr87781TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_RSV_SETns_noc_io_pcie_soc_ip.csr87792RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr87803MASK_0_33Mask3960x3ffff0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_4M__768G_8M__4M_7_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87810UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr87927p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00x28340R/W0x000000c000800010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr87851P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr87862NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr87873I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_R_WN_SETns_noc_io_pcie_soc_ip.csr87885R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_DI_SETns_noc_io_pcie_soc_ip.csr87896DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_LLC_SETns_noc_io_pcie_soc_ip.csr87908LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr87919BASE_ADDRESS_0_33Base address3960x300020000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr87926UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88019p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_00x28348R/W0x000000ffff800000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_8m__768g_16m__8m_8_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_P_SETns_noc_io_pcie_soc_ip.csr87944P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_NS_SETns_noc_io_pcie_soc_ip.csr87955NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_I_SETns_noc_io_pcie_soc_ip.csr87966I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_VAL_SETns_noc_io_pcie_soc_ip.csr87977VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_TM_SETns_noc_io_pcie_soc_ip.csr87989TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_RSV_SETns_noc_io_pcie_soc_ip.csr88000RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr88011MASK_0_33Mask3960x3fffe0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_8M__768G_16M__8M_8_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88018UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88135p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00x28360R/W0x000000c001000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr88059P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr88070NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr88081I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_R_WN_SETns_noc_io_pcie_soc_ip.csr88093R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_DI_SETns_noc_io_pcie_soc_ip.csr88104DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_LLC_SETns_noc_io_pcie_soc_ip.csr88116LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr88127BASE_ADDRESS_0_33Base address3960x300040000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88134UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88227p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_00x28368R/W0x000000ffff000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_16m__768g_32m__16m_9_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_P_SETns_noc_io_pcie_soc_ip.csr88152P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_NS_SETns_noc_io_pcie_soc_ip.csr88163NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_I_SETns_noc_io_pcie_soc_ip.csr88174I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_VAL_SETns_noc_io_pcie_soc_ip.csr88185VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_TM_SETns_noc_io_pcie_soc_ip.csr88197TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_RSV_SETns_noc_io_pcie_soc_ip.csr88208RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr88219MASK_0_33Mask3960x3fffc0000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_16M__768G_32M__16M_9_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88226UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88343p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00x28380R/W0x000000c002000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr88267P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr88278NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr88289I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_R_WN_SETns_noc_io_pcie_soc_ip.csr88301R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_DI_SETns_noc_io_pcie_soc_ip.csr88312DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_LLC_SETns_noc_io_pcie_soc_ip.csr88324LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr88335BASE_ADDRESS_0_33Base address3960x300080000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88342UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88435p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_00x28388R/W0x000000fffe000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_32m__768g_64m__32m_10_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_P_SETns_noc_io_pcie_soc_ip.csr88360P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_NS_SETns_noc_io_pcie_soc_ip.csr88371NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_I_SETns_noc_io_pcie_soc_ip.csr88382I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_VAL_SETns_noc_io_pcie_soc_ip.csr88393VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_TM_SETns_noc_io_pcie_soc_ip.csr88405TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_RSV_SETns_noc_io_pcie_soc_ip.csr88416RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr88427MASK_0_33Mask3960x3fff80000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_32M__768G_64M__32M_10_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88434UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88551p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00x283A0R/W0x000000c004000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr88475P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr88486NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr88497I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_R_WN_SETns_noc_io_pcie_soc_ip.csr88509R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_DI_SETns_noc_io_pcie_soc_ip.csr88520DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_LLC_SETns_noc_io_pcie_soc_ip.csr88532LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr88543BASE_ADDRESS_0_33Base address3960x300100000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88550UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88643p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_00x283A8R/W0x000000fffc000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_64m__768g_128m__64m_11_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_P_SETns_noc_io_pcie_soc_ip.csr88568P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_NS_SETns_noc_io_pcie_soc_ip.csr88579NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_I_SETns_noc_io_pcie_soc_ip.csr88590I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_VAL_SETns_noc_io_pcie_soc_ip.csr88601VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_TM_SETns_noc_io_pcie_soc_ip.csr88613TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_RSV_SETns_noc_io_pcie_soc_ip.csr88624RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr88635MASK_0_33Mask3960x3fff00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_64M__768G_128M__64M_11_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88642UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88759p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00x283C0R/W0x000000c008000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr88683P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr88694NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr88705I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_R_WN_SETns_noc_io_pcie_soc_ip.csr88717R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_DI_SETns_noc_io_pcie_soc_ip.csr88728DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_LLC_SETns_noc_io_pcie_soc_ip.csr88740LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr88751BASE_ADDRESS_0_33Base address3960x300200000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88758UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88851p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_00x283C8R/W0x000000fff8000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_128m__768g_256m__128m_12_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_P_SETns_noc_io_pcie_soc_ip.csr88776P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_NS_SETns_noc_io_pcie_soc_ip.csr88787NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_I_SETns_noc_io_pcie_soc_ip.csr88798I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_VAL_SETns_noc_io_pcie_soc_ip.csr88809VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_TM_SETns_noc_io_pcie_soc_ip.csr88821TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_RSV_SETns_noc_io_pcie_soc_ip.csr88832RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr88843MASK_0_33Mask3960x3ffe00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_128M__768G_256M__128M_12_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88850UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr88967p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00x283E0R/W0x000000c010000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr88891P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr88902NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr88913I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_R_WN_SETns_noc_io_pcie_soc_ip.csr88925R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_DI_SETns_noc_io_pcie_soc_ip.csr88936DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_LLC_SETns_noc_io_pcie_soc_ip.csr88948LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr88959BASE_ADDRESS_0_33Base address3960x300400000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr88966UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89059p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_00x283E8R/W0x000000fff0000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_256m__768g_512m__256m_13_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_P_SETns_noc_io_pcie_soc_ip.csr88984P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_NS_SETns_noc_io_pcie_soc_ip.csr88995NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_I_SETns_noc_io_pcie_soc_ip.csr89006I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_VAL_SETns_noc_io_pcie_soc_ip.csr89017VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_TM_SETns_noc_io_pcie_soc_ip.csr89029TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_RSV_SETns_noc_io_pcie_soc_ip.csr89040RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr89051MASK_0_33Mask3960x3ffc00000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_256M__768G_512M__256M_13_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89058UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89175p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00x28400R/W0x000000c020000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr89099P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr89110NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr89121I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_R_WN_SETns_noc_io_pcie_soc_ip.csr89133R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_DI_SETns_noc_io_pcie_soc_ip.csr89144DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_LLC_SETns_noc_io_pcie_soc_ip.csr89156LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr89167BASE_ADDRESS_0_33Base address3960x300800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89174UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89267p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_00x28408R/W0x000000ffe0000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_768g_512m__769g__512m_14_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_P_SETns_noc_io_pcie_soc_ip.csr89192P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_NS_SETns_noc_io_pcie_soc_ip.csr89203NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_I_SETns_noc_io_pcie_soc_ip.csr89214I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_VAL_SETns_noc_io_pcie_soc_ip.csr89225VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_TM_SETns_noc_io_pcie_soc_ip.csr89237TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_RSV_SETns_noc_io_pcie_soc_ip.csr89248RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr89259MASK_0_33Mask3960x3ff800000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_768G_512M__769G__512M_14_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89266UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89383p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00x28420R/W0x000000c040000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr89307P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr89318NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr89329I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_R_WN_SETns_noc_io_pcie_soc_ip.csr89341R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_DI_SETns_noc_io_pcie_soc_ip.csr89352DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_LLC_SETns_noc_io_pcie_soc_ip.csr89364LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr89375BASE_ADDRESS_0_33Base address3960x301000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89382UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89475p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_00x28428R/W0x000000ffc0000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_769g__770g__1g_15_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_P_SETns_noc_io_pcie_soc_ip.csr89400P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_NS_SETns_noc_io_pcie_soc_ip.csr89411NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_I_SETns_noc_io_pcie_soc_ip.csr89422I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_VAL_SETns_noc_io_pcie_soc_ip.csr89433VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_TM_SETns_noc_io_pcie_soc_ip.csr89445TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_RSV_SETns_noc_io_pcie_soc_ip.csr89456RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr89467MASK_0_33Mask3960x3ff000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_769G__770G__1G_15_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89474UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89591p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00x28440R/W0x000000c080000010Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr89515P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr89526NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr89537I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_R_WN_SETns_noc_io_pcie_soc_ip.csr89549R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_DI_SETns_noc_io_pcie_soc_ip.csr89560DI1'b1: Address range disabled440x1R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_LLC_SETns_noc_io_pcie_soc_ip.csr89572LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr89583BASE_ADDRESS_0_33Base address3960x302000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89590UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89683p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_00x28448R/W0x000000ff80000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_770g__772g__2g_16_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_P_SETns_noc_io_pcie_soc_ip.csr89608P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_NS_SETns_noc_io_pcie_soc_ip.csr89619NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_I_SETns_noc_io_pcie_soc_ip.csr89630I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_VAL_SETns_noc_io_pcie_soc_ip.csr89641VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_TM_SETns_noc_io_pcie_soc_ip.csr89653TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_RSV_SETns_noc_io_pcie_soc_ip.csr89664RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr89675MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_770G__772G__2G_16_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89682UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89799p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00x28460R/W0x000000c100000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr89723P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr89734NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr89745I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_R_WN_SETns_noc_io_pcie_soc_ip.csr89757R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_DI_SETns_noc_io_pcie_soc_ip.csr89768DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_LLC_SETns_noc_io_pcie_soc_ip.csr89780LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr89791BASE_ADDRESS_0_33Base address3960x304000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89798UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr89891p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_00x28468R/W0x000000ff00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_772g__776g__4g_17_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_P_SETns_noc_io_pcie_soc_ip.csr89816P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_NS_SETns_noc_io_pcie_soc_ip.csr89827NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_I_SETns_noc_io_pcie_soc_ip.csr89838I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_VAL_SETns_noc_io_pcie_soc_ip.csr89849VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_TM_SETns_noc_io_pcie_soc_ip.csr89861TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_RSV_SETns_noc_io_pcie_soc_ip.csr89872RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr89883MASK_0_33Mask3960x3fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_772G__776G__4G_17_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr89890UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90007p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00x28480R/W0x000000c200000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr89931P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr89942NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr89953I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_R_WN_SETns_noc_io_pcie_soc_ip.csr89965R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_DI_SETns_noc_io_pcie_soc_ip.csr89976DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_LLC_SETns_noc_io_pcie_soc_ip.csr89988LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr89999BASE_ADDRESS_0_33Base address3960x308000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr90006UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90099p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_00x28488R/W0x000000fe00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_776g__784g__8g_18_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_P_SETns_noc_io_pcie_soc_ip.csr90024P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_NS_SETns_noc_io_pcie_soc_ip.csr90035NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_I_SETns_noc_io_pcie_soc_ip.csr90046I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_VAL_SETns_noc_io_pcie_soc_ip.csr90057VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_TM_SETns_noc_io_pcie_soc_ip.csr90069TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_RSV_SETns_noc_io_pcie_soc_ip.csr90080RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr90091MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_776G__784G__8G_18_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr90098UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90215p0_p1_m register am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00x284A0R/W0x000000c400000000Pcie_noc_bridge_p0_p1_m_4_6_am_adbase_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr90139P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr90150NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr90161I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_R_WN_SETns_noc_io_pcie_soc_ip.csr90173R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_DI_SETns_noc_io_pcie_soc_ip.csr90184DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_LLC_SETns_noc_io_pcie_soc_ip.csr90196LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr90207BASE_ADDRESS_0_33Base address3960x310000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADBASE_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr90214UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90307p0_p1_m register am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_00x284A8R/W0x000000fc00000000Pcie_noc_bridge_p0_p1_m_4_6_am_admask_mem_main0_tosys_s_sr_main0_tosys_s_map_r_784g__800g__16g_19_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_P_SETns_noc_io_pcie_soc_ip.csr90232P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_NS_SETns_noc_io_pcie_soc_ip.csr90243NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_I_SETns_noc_io_pcie_soc_ip.csr90254I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_VAL_SETns_noc_io_pcie_soc_ip.csr90265VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_TM_SETns_noc_io_pcie_soc_ip.csr90277TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_RSV_SETns_noc_io_pcie_soc_ip.csr90288RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr90299MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ADMASK_MEM_MAIN0_TOSYS_S_SR_MAIN0_TOSYS_S_MAP_R_784G__800G__16G_19_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr90306UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_p_0bridge_p0_p1_m_4_6_p_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90372p0_p1_m register p_00x2B000R/W0x00000003Pcie_noc_bridge_p0_p1_m_4_6_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr90335WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr90347WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr90359WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr90371WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_p_1bridge_p0_p1_m_4_6_p_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90438p0_p1_m register p_10x2B008R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr90401WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr90413WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr90425WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr90437WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_p_2bridge_p0_p1_m_4_6_p_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90504p0_p1_m register p_20x2B010R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr90467WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr90479WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr90491WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr90503WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_p_3bridge_p0_p1_m_4_6_p_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90570p0_p1_m register p_30x2B018R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr90533WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr90545WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr90557WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr90569WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_txebridge_p0_p1_m_4_6_txePCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90716p0_p1_m register txe0x2B040R/W0x00000000Pcie_noc_bridge_p0_p1_m_4_6_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr90597TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr90609SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr90624TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr90637EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr90651FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr90665FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr90679FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr90693FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr90704PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr90715UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_txembridge_p0_p1_m_4_6_txemPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr90795p0_p1_m register txem0x2B048R/W0x00000008Pcie_noc_bridge_p0_p1_m_4_6_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr90739UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr90750TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr90761EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr90772UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr90783PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr90794UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_btus_0bridge_p0_p1_m_4_6_btus_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr91163p0_p1_m register btus_00x2B058R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr90821L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr90832L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr90843L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr90854L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr90865L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr90876L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr90887L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr90898L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr90909L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr90920L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr90931L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr90942L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr90953L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr90964L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr90975L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr90986L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr90997L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr91008L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr91019L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr91030L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr91041L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr91052L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr91063L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr91074L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr91085L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr91096L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr91107L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr91118L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr91129L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr91140L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr91151L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr91162L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_p1_m_4_6_btus_1bridge_p0_p1_m_4_6_btus_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr91531p0_p1_m register btus_10x2B060R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr91189L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr91200L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr91211L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr91222L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr91233L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr91244L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr91255L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr91266L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr91277L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr91288L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr91299L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr91310L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr91321L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr91332L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr91343L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr91354L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr91365L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr91376L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr91387L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr91398L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr91409L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr91420L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr91431L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr91442L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr91453L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr91464L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr91475L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr91486L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr91497L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr91508L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr91519L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr91530L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_p1_m_4_6_btrl_0bridge_p0_p1_m_4_6_btrl_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr91607p0_p1_m register btrl_00x2B080R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr91555WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr91566RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr91581CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr91595EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr91606UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_m_4_6_btrl_1bridge_p0_p1_m_4_6_btrl_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr91683p0_p1_m register btrl_10x2B088R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr91631WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr91642RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr91657CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr91671EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr91682UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_m_4_6_btrl_2bridge_p0_p1_m_4_6_btrl_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr91759p0_p1_m register btrl_20x2B090R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr91707WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr91718RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr91733CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr91747EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr91758UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_m_4_6_btrl_3bridge_p0_p1_m_4_6_btrl_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr91835p0_p1_m register btrl_30x2B098R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr91783WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr91794RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr91809CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr91823EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr91834UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_m_4_6_btperrbridge_p0_p1_m_4_6_btperrPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr92037p0_p1_m register btperr0x2B0A8R/W0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr91860L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr91871L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr91882L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr91893L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr91904L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr91915L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr91926L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr91937L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr91948L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr91959L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr91970L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr91981L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr91992L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr92003L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr92014L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr92025L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr92036UNSD31160x0000Rregisterpcie_noc.bridge_p0_p1_m_4_6_btperrmbridge_p0_p1_m_4_6_btperrmPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr92237p0_p1_m register btperrm0x2B0B0R/W0x00000000Pcie_noc_bridge_p0_p1_m_4_6_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr92060L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr92071L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr92082L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr92093L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr92104L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr92115L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr92126L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr92137L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr92148L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr92159L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr92170L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr92181L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr92192L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr92203L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr92214L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr92225L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr92236UNSD31160x0000Rregisterpcie_noc.bridge_p0_p1_m_4_6_rxebridge_p0_p1_m_4_6_rxePCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr92345p0_p1_m register rxe0x2B120R/W0x00000000Pcie_noc_bridge_p0_p1_m_4_6_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr92265CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr92276CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr92287CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr92298CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr92310EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr92321PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr92333EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr92344UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_rxembridge_p0_p1_m_4_6_rxemPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr92417p0_p1_m register rxem0x2B128R/W0x00000050Pcie_noc_bridge_p0_p1_m_4_6_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr92366UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr92380EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr92391PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr92405EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr92416UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_brs_0bridge_p0_p1_m_4_6_brs_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr92691p0_p1_m register brs_00x2B130R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr92441OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr92452V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr92463S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr92474B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr92485F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr92495UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr92506OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr92517V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr92528S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr92539B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr92550F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr92560UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr92571OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr92582V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr92593S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr92604B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr92615F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr92625UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr92636OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr92647V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr92658S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr92669B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr92680F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr92690UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p1_m_4_6_brs_1bridge_p0_p1_m_4_6_brs_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr92965p0_p1_m register brs_10x2B138R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr92715OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr92726V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr92737S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr92748B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr92759F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr92769UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr92780OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr92791V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr92802S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr92813B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr92824F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr92834UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr92845OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr92856V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr92867S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr92878B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr92889F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr92899UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr92910OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr92921V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr92932S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr92943B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr92954F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr92964UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p1_m_4_6_brusbridge_p0_p1_m_4_6_brusPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93034p0_p1_m register brus0x2B1B0R0x00000000Pcie_noc_bridge_p0_p1_m_4_6_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr92990V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr93001V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr93012V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr93023V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr93033UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_brperr0bridge_p0_p1_m_4_6_brperr0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93262p0_p1_m register brperr00x2B1D0R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr93072D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr93083DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr93094SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr93106SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr93117PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr93128UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr93139D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr93150DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr93161SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr93173SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr93184PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr93195UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr93206UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr93217UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr93228UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr93239UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr93250UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr93261UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_brperr1bridge_p0_p1_m_4_6_brperr1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93378p0_p1_m register brperr10x2B1D8R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr93300UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr93311UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr93322UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr93333UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr93344UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr93355UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr93366UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr93377UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_brperrm0bridge_p0_p1_m_4_6_brperrm0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93599p0_p1_m register brperrm00x2B1E0R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr93405D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr93417DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr93428SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr93440SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr93452PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr93463UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr93474D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr93486DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr93497SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr93509SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr93521PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr93532UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr93543UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr93554UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr93565UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr93576UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr93587UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr93598UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_brperrm1bridge_p0_p1_m_4_6_brperrm1PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93704p0_p1_m register brperrm10x2B1E8R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr93626UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr93637UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr93648UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr93659UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr93670UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr93681UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr93692UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr93703UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_tocfgbridge_p0_p1_m_4_6_am_tocfgPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93778p0_p1_m register am_tocfg0x2BC00R/W0x000000000000001fPcie_noc_bridge_p0_p1_m_4_6_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr93741TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr93752UNSD_7_6760x0RENPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr93766EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr93777UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_osslvbridge_p0_p1_m_4_6_am_osslvPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93813p0_p1_m register am_osslv0x2BC08R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr93801SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr93812UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_cgcbridge_p0_p1_m_4_6_am_cgcPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93850p0_p1_m register am_cgc0x2BC10R/W0x0000000000000064Pcie_noc_bridge_p0_p1_m_4_6_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr93838HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr93849UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_cgobridge_p0_p1_m_4_6_am_cgoPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93885p0_p1_m register am_cgo0x2BC18R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr93873FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr93884UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_cfgbridge_p0_p1_m_4_6_am_cfgPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr93922p0_p1_m register am_cfg0x2BC20R/W0x0000000000000001Pcie_noc_bridge_p0_p1_m_4_6_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr93910AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr93921UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_stsbridge_p0_p1_m_4_6_am_stsPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr94050p0_p1_m register am_sts0x2BD00R0x000000000000000cPcie_noc_bridge_p0_p1_m_4_6_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr93955ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr93969WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr93981ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr93993WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr94004ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr94015AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr94027ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr94039AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr94049UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_bridge_idbridge_p0_p1_m_4_6_am_bridge_idPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr94080p0_p1_m register am_bridge_id0x2BD08R0x0000000000000004Pcie_noc_bridge_p0_p1_m_4_6_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr94069IDUnique bridge ID1500x0004RUNSD_63_16PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr94079UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_errbridge_p0_p1_m_4_6_am_errPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr94576p0_p1_m register am_err0x2BE00R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr94102E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr94114E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr94126E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr94138E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr94150E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr94162E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr94175E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr94188E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr94199E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr94210UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr94221E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr94232E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr94243E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr94254E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr94265E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr94276E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr94287E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr94299E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr94310E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr94321UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr94332E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr94343E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr94355E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr94367E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr94378UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr94390E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr94401E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr94412E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr94423E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr94434E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr94445E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr94456E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr94468E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr94480E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr94492E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr94504E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr94516E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr94528E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr94540E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr94552E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr94564E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr94575UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_toslvidbridge_p0_p1_m_4_6_am_toslvidPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr94621p0_p1_m register am_toslvid0x2BE08R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr94599AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr94610AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr94620UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_erabridge_p0_p1_m_4_6_am_eraPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr94643p0_p1_m register am_era0x2BE10R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr94642READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_ewabridge_p0_p1_m_4_6_am_ewaPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr94665p0_p1_m register am_ewa0x2BE18R0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr94664WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_intmbridge_p0_p1_m_4_6_am_intmPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95149p0_p1_m register am_intm0x2BE40R/W0x00007e07004f004fPcie_noc_bridge_p0_p1_m_4_6_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr94687M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr94698M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr94709M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr94720M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr94731M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr94742M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr94753M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr94764M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr94775M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr94786UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr94797M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr94808M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr94819M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr94830M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr94841M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr94852M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr94863M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr94874M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr94885M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr94896UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr94907M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr94918M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr94929M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr94940M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr94951UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr94963M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr94974M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr94985M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr94996M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr95007M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr95018M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr95029M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr95041E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr95053E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr95065E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr95077E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr95089E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr95101E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr95113E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr95125E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr95137E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr95148UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_caddrbridge_p0_p1_m_4_6_am_caddrPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95171p0_p1_m register am_caddr0x2BF00R/W0xffffffffffffffffPcie_noc_bridge_p0_p1_m_4_6_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr95170CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_p0_p1_m_4_6_am_caddrmskbridge_p0_p1_m_4_6_am_caddrmskPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95194p0_p1_m register am_caddrmsk0x2BF08R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr95193CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_p0_p1_m_4_6_am_ccmd0bridge_p0_p1_m_4_6_am_ccmd0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95384p0_p1_m register am_ccmd00x2BF10R/W0x0000000003fff33fPcie_noc_bridge_p0_p1_m_4_6_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr95216SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr95227DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr95238UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr95249BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr95260UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr95271CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr95282QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr95293PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr95304LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr95315RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr95326VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr95337UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr95349INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr95360UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr95372TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr95383UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk0bridge_p0_p1_m_4_6_am_ccmdmsk0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95528p0_p1_m register am_ccmdmsk00x2BF18R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr95406SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr95417DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr95428UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr95439BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr95450UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr95461CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr95472QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr95483PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr95494LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr95505RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr95516VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr95527UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_cntr0bridge_p0_p1_m_4_6_am_cntr0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95563p0_p1_m register am_cntr00x2BF20R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr95551CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr95562UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_latnum0bridge_p0_p1_m_4_6_am_latnum0PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95602p0_p1_m register am_latnum00x2BF28R/W0x0000000000000007Pcie_noc_bridge_p0_p1_m_4_6_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr95590CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr95601UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_ccmd1bridge_p0_p1_m_4_6_am_ccmd1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95792p0_p1_m register am_ccmd10x2BF30R/W0x0000000003fff33fPcie_noc_bridge_p0_p1_m_4_6_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr95624SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr95635DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr95646UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr95657BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr95668UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr95679CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr95690QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr95701PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr95712LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr95723RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr95734VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr95745UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr95757INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr95768UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr95780TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr95791UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_ccmdmsk1bridge_p0_p1_m_4_6_am_ccmdmsk1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95936p0_p1_m register am_ccmdmsk10x2BF38R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr95814SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr95825DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr95836UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr95847BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr95858UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr95869CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr95880QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr95891PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr95902LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr95913RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr95924VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr95935UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_cntr1bridge_p0_p1_m_4_6_am_cntr1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr95971p0_p1_m register am_cntr10x2BF40R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr95959CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr95970UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_latnum1bridge_p0_p1_m_4_6_am_latnum1PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96010p0_p1_m register am_latnum10x2BF48R/W0x0000000000000007Pcie_noc_bridge_p0_p1_m_4_6_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr95998CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr96009UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_arovrdbridge_p0_p1_m_4_6_am_arovrdPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96123p0_p1_m register am_arovrd0x2BF60R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr96028arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr96041arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr96052arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr96063UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr96076arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr96087UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr96098arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr96111arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr96122UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p1_m_4_6_am_awovrdbridge_p0_p1_m_4_6_am_awovrdPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96236p0_p1_m register am_awovrd0x2BF68R/W0x0000000000000000Pcie_noc_bridge_p0_p1_m_4_6_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr96141awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr96154awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr96165awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr96176UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr96189awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr96200UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr96211awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr96224awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P1_M_4_6_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr96235UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_cgcbridge_p0_p1_reg_s_11_6_as_cgcPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96273p0_p1_reg_s register as_cgc0x2DC10R/W0x0000000000000064Pcie_noc_bridge_p0_p1_reg_s_11_6_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr96261HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr96272UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_cgobridge_p0_p1_reg_s_11_6_as_cgoPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96308p0_p1_reg_s register as_cgo0x2DC18R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr96296FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr96307UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_stsbridge_p0_p1_reg_s_11_6_as_stsPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96382p0_p1_reg_s register as_sts0x2DD00R0x000000000000000cPcie_noc_bridge_p0_p1_reg_s_11_6_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr96331WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr96347ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr96359WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr96371ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr96381UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_bridge_idbridge_p0_p1_reg_s_11_6_as_bridge_idPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96412p0_p1_reg_s register as_bridge_id0x2DD08R0x000000000000000bPcie_noc_bridge_p0_p1_reg_s_11_6_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr96401IDUnique bridge ID1500x000bRUNSD_63_16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr96411UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_errbridge_p0_p1_reg_s_11_6_as_errPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr96765p0_p1_reg_s register as_err0x2DE00R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr96433E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr96445E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr96458E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr96472E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr96484E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr96495UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr96507E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr96519E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr96532E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr96544E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr96555UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr96567E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr96578E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr96589E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr96600E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr96611E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr96622E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr96633E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr96645E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr96657E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr96669E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr96681E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr96693E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr96705E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr96717E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr96729E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr96741E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr96753E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr96764UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_intmbridge_p0_p1_reg_s_11_6_as_intmPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97105p0_p1_reg_s register as_intm0x2DE40R/W0x0000007d000b0013Pcie_noc_bridge_p0_p1_reg_s_11_6_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr96786M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr96797M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr96808M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr96819M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr96830M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr96841UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr96852M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr96863M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr96874M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr96885M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr96896UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr96907M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr96918M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr96929M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr96940M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr96951M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr96962M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr96973M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr96985E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr96997E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr97009E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr97021E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr97033E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr97045E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr97057E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr97069E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr97081E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr97093E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr97104UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdbridge_p0_p1_reg_s_11_6_as_ccmdPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97180p0_p1_reg_s register as_ccmd0x2DF00R/W0x0000000003000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr97123UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr97134rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr97145val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr97156UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr97168intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr97179UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_ccmdmskbridge_p0_p1_reg_s_11_6_as_ccmdmskPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97232p0_p1_reg_s register as_ccmdmsk0x2DF08R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr97198UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr97209rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr97220val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr97231UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_cntrbridge_p0_p1_reg_s_11_6_as_cntrPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97262p0_p1_reg_s register as_cntr0x2DF10R0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr97251CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr97261UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_arovrdbridge_p0_p1_reg_s_11_6_as_arovrdPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97375p0_p1_reg_s register as_arovrd0x2DF18R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr97280arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr97293arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr97304arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr97315UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr97328arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr97339UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr97350arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr97363arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr97374UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_as_awovrdbridge_p0_p1_reg_s_11_6_as_awovrdPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97488p0_p1_reg_s register as_awovrd0x2DF20R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr97393awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr97406awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr97417awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr97428UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr97441awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr97452UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr97463awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr97476awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr97487UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_p_0bridge_p0_p1_reg_s_11_6_p_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97553p0_p1_reg_s register p_00x2F000R/W0x00000003Pcie_noc_bridge_p0_p1_reg_s_11_6_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr97516WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr97528WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr97540WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr97552WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_p_1bridge_p0_p1_reg_s_11_6_p_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97619p0_p1_reg_s register p_10x2F008R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr97582WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr97594WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr97606WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr97618WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_p_2bridge_p0_p1_reg_s_11_6_p_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97685p0_p1_reg_s register p_20x2F010R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr97648WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr97660WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr97672WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr97684WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_p_3bridge_p0_p1_reg_s_11_6_p_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97751p0_p1_reg_s register p_30x2F018R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr97714WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr97726WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr97738WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr97750WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_txebridge_p0_p1_reg_s_11_6_txePCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97897p0_p1_reg_s register txe0x2F040R/W0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr97778TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr97790SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr97805TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr97818EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr97832FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr97846FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr97860FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr97874FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr97885PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr97896UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_txembridge_p0_p1_reg_s_11_6_txemPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr97976p0_p1_reg_s register txem0x2F048R/W0x00000008Pcie_noc_bridge_p0_p1_reg_s_11_6_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr97920UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr97931TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr97942EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr97953UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr97964PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr97975UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btus_0bridge_p0_p1_reg_s_11_6_btus_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr98344p0_p1_reg_s register btus_00x2F058R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr98002L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr98013L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr98024L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr98035L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr98046L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr98057L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr98068L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr98079L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr98090L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr98101L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr98112L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr98123L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr98134L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr98145L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr98156L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr98167L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr98178L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr98189L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr98200L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr98211L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr98222L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr98233L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr98244L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr98255L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr98266L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr98277L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr98288L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr98299L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr98310L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr98321L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr98332L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr98343L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btus_1bridge_p0_p1_reg_s_11_6_btus_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr98712p0_p1_reg_s register btus_10x2F060R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr98370L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr98381L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr98392L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr98403L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr98414L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr98425L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr98436L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr98447L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr98458L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr98469L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr98480L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr98491L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr98502L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr98513L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr98524L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr98535L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr98546L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr98557L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr98568L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr98579L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr98590L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr98601L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr98612L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr98623L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr98634L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr98645L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr98656L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr98667L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr98678L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr98689L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr98700L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr98711L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btrl_0bridge_p0_p1_reg_s_11_6_btrl_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr98788p0_p1_reg_s register btrl_00x2F080R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr98736WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr98747RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr98762CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr98776EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr98787UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btrl_1bridge_p0_p1_reg_s_11_6_btrl_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr98864p0_p1_reg_s register btrl_10x2F088R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr98812WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr98823RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr98838CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr98852EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr98863UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btrl_2bridge_p0_p1_reg_s_11_6_btrl_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr98940p0_p1_reg_s register btrl_20x2F090R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr98888WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr98899RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr98914CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr98928EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr98939UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btrl_3bridge_p0_p1_reg_s_11_6_btrl_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr99016p0_p1_reg_s register btrl_30x2F098R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr98964WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr98975RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr98990CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr99004EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr99015UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btperrbridge_p0_p1_reg_s_11_6_btperrPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr99218p0_p1_reg_s register btperr0x2F0A8R/W0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr99041L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr99052L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr99063L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr99074L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr99085L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr99096L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr99107L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr99118L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr99129L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr99140L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr99151L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr99162L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr99173L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr99184L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr99195L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr99206L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr99217UNSD31160x0000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_btperrmbridge_p0_p1_reg_s_11_6_btperrmPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr99418p0_p1_reg_s register btperrm0x2F0B0R/W0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr99241L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr99252L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr99263L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr99274L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr99285L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr99296L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr99307L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr99318L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr99329L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr99340L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr99351L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr99362L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr99373L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr99384L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr99395L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr99406L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr99417UNSD31160x0000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_rxebridge_p0_p1_reg_s_11_6_rxePCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr99526p0_p1_reg_s register rxe0x2F120R/W0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr99446CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr99457CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr99468CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr99479CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr99491EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr99502PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr99514EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr99525UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_rxembridge_p0_p1_reg_s_11_6_rxemPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr99598p0_p1_reg_s register rxem0x2F128R/W0x00000050Pcie_noc_bridge_p0_p1_reg_s_11_6_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr99547UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr99561EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr99572PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr99586EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr99597UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brs_0bridge_p0_p1_reg_s_11_6_brs_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr99872p0_p1_reg_s register brs_00x2F130R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr99622OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr99633V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr99644S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr99655B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr99666F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr99676UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr99687OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr99698V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr99709S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr99720B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr99731F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr99741UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr99752OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr99763V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr99774S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr99785B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr99796F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr99806UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr99817OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr99828V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr99839S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr99850B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr99861F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr99871UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brs_1bridge_p0_p1_reg_s_11_6_brs_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100146p0_p1_reg_s register brs_10x2F138R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr99896OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr99907V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr99918S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr99929B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr99940F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr99950UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr99961OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr99972V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr99983S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr99994B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr100005F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr100015UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr100026OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr100037V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr100048S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr100059B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr100070F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr100080UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr100091OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr100102V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr100113S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr100124B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr100135F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr100145UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brusbridge_p0_p1_reg_s_11_6_brusPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100215p0_p1_reg_s register brus0x2F1B0R0x00000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr100171V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr100182V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr100193V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr100204V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr100214UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brperr0bridge_p0_p1_reg_s_11_6_brperr0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100443p0_p1_reg_s register brperr00x2F1D0R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr100253D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr100264DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr100275SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr100287SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr100298PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr100309UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr100320D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr100331DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr100342SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr100354SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr100365PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr100376UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr100387UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr100398UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr100409UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr100420UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr100431UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr100442UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brperr1bridge_p0_p1_reg_s_11_6_brperr1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100559p0_p1_reg_s register brperr10x2F1D8R0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr100481UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr100492UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr100503UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr100514UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr100525UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr100536UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr100547UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr100558UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brperrm0bridge_p0_p1_reg_s_11_6_brperrm0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100780p0_p1_reg_s register brperrm00x2F1E0R/W0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr100586D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr100598DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr100609SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr100621SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr100633PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr100644UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr100655D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr100667DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr100678SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr100690SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr100702PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr100713UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr100724UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr100735UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr100746UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr100757UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr100768UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr100779UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_reg_s_11_6_brperrm1bridge_p0_p1_reg_s_11_6_brperrm1PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100885p0_p1_reg_s register brperrm10x2F1E8R0x0000000000000000Pcie_noc_bridge_p0_p1_reg_s_11_6_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr100807UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr100818UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr100829UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr100840UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr100851UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr100862UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr100873UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_REG_S_11_6_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr100884UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_cgcbridge_p0_p1_s_12_10_as_cgcPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100922p0_p1_s register as_cgc0x31C10R/W0x0000000000000064Pcie_noc_bridge_p0_p1_s_12_10_as_cgcProgrammable intervals used by coarse clock gating logic. This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr100910HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr100921UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_cgobridge_p0_p1_s_12_10_as_cgoPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr100957p0_p1_s register as_cgo0x31C18R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_as_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the slave bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr100945FPO1'b1: Clock gating override enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr100956UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_stsbridge_p0_p1_s_12_10_as_stsPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101031p0_p1_s register as_sts0x31D00R0x000000000000000cPcie_noc_bridge_p0_p1_s_12_10_as_stsSlave bridge status bits.falsefalsefalsefalseWOFPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOF_SETns_noc_io_pcie_soc_ip.csr100980WOF1'b1: Maximum number of supported write commands are outstanding to the attached slave device awaiting response, no more write commands will be issued to slave till responses are received.1'b0: Slave device can expect more write commands from NoC000x0RROFPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROF_SETns_noc_io_pcie_soc_ip.csr100996ROF1'b1: Maximum number of supported read commands are outstanding to the attached slave device awaiting response, no more read commands will be issued to slave till responses are received.1'b0: Slave bridge can accept more read commands from the NoC110x0RWOEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_WOE_SETns_noc_io_pcie_soc_ip.csr101008WOE1'b1: There are no write commands outstanding to the attached slave device220x1RROEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_ROE_SETns_noc_io_pcie_soc_ip.csr101020ROE1'b1: There are no read commands outstanding to the attached slave device330x1RUNSD_63_4PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_STS_UNSD_63_4_SETns_noc_io_pcie_soc_ip.csr101030UNSD_63_46340x000000000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_bridge_idbridge_p0_p1_s_12_10_as_bridge_idPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101061p0_p1_s register as_bridge_id0x31D08R0x000000000000000cPcie_noc_bridge_p0_p1_s_12_10_as_bridge_idUnique identifier assigned to the slave bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr101050IDUnique bridge ID1500x000cRUNSD_63_16PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr101060UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_errbridge_p0_p1_s_12_10_as_errPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101414p0_p1_s register as_err0x31E00R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_as_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E0_SETns_noc_io_pcie_soc_ip.csr101082E01'b1: Read decode error response: Decode error response received from slave device for read command000x0R/WE1PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E1_SETns_noc_io_pcie_soc_ip.csr101094E11'b1: Read slave error response: Slave error response received from slave device for read command110x0R/WE2PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E2_SETns_noc_io_pcie_soc_ip.csr101107E21'b1: [FATAL] Unknown read response destination: RID from read response produces a destination which is not present in the routing table220x0R/WE3PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E3_SETns_noc_io_pcie_soc_ip.csr101121E31'b1: [FATAL] Interleaved read response: Interleaved read response. This can occur if interleaved read response is received from a slave device for which a de-interleaver was not specified330x0R/WE4PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E4_SETns_noc_io_pcie_soc_ip.csr101133E41'b1: Read command modified: A read command which was marked as non-modifiable was modified by the slave bridge440x0R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr101144UNSD_15_51550x000RE16PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E16_SETns_noc_io_pcie_soc_ip.csr101156E161'b1: Write decode error response: Decode error response received from slave device for write command16160x0R/WE17PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E17_SETns_noc_io_pcie_soc_ip.csr101168E171'b1: Write slave error response: Slave error response received from slave device for write command17170x0R/WE18PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E18_SETns_noc_io_pcie_soc_ip.csr101181E181'b1: [FATAL] Unknown write response destination: BID from write response produces a destination which is not present in the routing table18180x0R/WE19PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E19_SETns_noc_io_pcie_soc_ip.csr101193E191'b1: Write command modified: A write command which was marked as non-modifiable was modified by the slave bridge19190x0R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr101204UNSD_31_2031200x000RE32PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E32_SETns_noc_io_pcie_soc_ip.csr101216E321'b1: [FATAL] Traffic sent to a noc layer which is power gated32320x0R/WE33PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E33_SETns_noc_io_pcie_soc_ip.csr101227E331'b1: [FATAL] Parity error in config/status registers33330x0R/WE34PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E34_SETns_noc_io_pcie_soc_ip.csr101238E341'b1: [FATAL] RDATA Parity error34340x0R/WE35PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E35_SETns_noc_io_pcie_soc_ip.csr101249E351'b1: [FATAL] RRESP Parity error35350x0R/WE36PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E36_SETns_noc_io_pcie_soc_ip.csr101260E361'b1: [FATAL] BRESP Parity error36360x0R/WE37PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E37_SETns_noc_io_pcie_soc_ip.csr101271E371'b1: [FATAL] AC Parity error37370x0R/WE38PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E38_SETns_noc_io_pcie_soc_ip.csr101282E381'b1: [FATAL] ACADDR Parity error38380x0R/WE39PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E39_SETns_noc_io_pcie_soc_ip.csr101294E391'b1: [FATAL] R Ch Cmdtbl Parity Err39390x0RE40PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E40_SETns_noc_io_pcie_soc_ip.csr101306E401'b1: [FATAL] B Ch Cmdtbl Parity Err40400x0RE41PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E41_SETns_noc_io_pcie_soc_ip.csr101318E411'b1: [FATAL] Rx Fifo Parity Err41410x0RE42PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E42_SETns_noc_io_pcie_soc_ip.csr101330E421'b1: [FATAL] CRCD Ch Reorder Buffer Parity Err42420x0RE43PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E43_SETns_noc_io_pcie_soc_ip.csr101342E431'b1: [FATAL] Ack Ch Wack Reorder Buffer Parity Err43430x0RE44PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E44_SETns_noc_io_pcie_soc_ip.csr101354E441'b1: [FATAL] Ack Ch Rack Reorder Buffer Parity Err44440x0RE45PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E45_SETns_noc_io_pcie_soc_ip.csr101366E451'b1: [FATAL] B Ch Drain Fifo Parity Err45450x0RE46PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E46_SETns_noc_io_pcie_soc_ip.csr101378E461'b1: [FATAL] R Ch Flush Fifo Parity Err46460x0RE47PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E47_SETns_noc_io_pcie_soc_ip.csr101390E471'b1: [FATAL] R Ch Deinterleaver Cmdtbl Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_E48_SETns_noc_io_pcie_soc_ip.csr101402E481'b1: [FATAL] R Ch Deinterleaver Data Buffer Parity Err48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_ERR_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr101413UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_intmbridge_p0_p1_s_12_10_as_intmPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101754p0_p1_s register as_intm0x31E40R/W0x0000007d000b0013Pcie_noc_bridge_p0_p1_s_12_10_as_intmInterrupt mask register.Individual bit positions match the error bit positions in AS_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M0_SETns_noc_io_pcie_soc_ip.csr101435M0 Mask interrupts for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M1_SETns_noc_io_pcie_soc_ip.csr101446M1 Mask interrupts for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M2_SETns_noc_io_pcie_soc_ip.csr101457M2 Mask interrupts for read channel220x0R/WM3PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M3_SETns_noc_io_pcie_soc_ip.csr101468M3 Mask interrupts for read channel330x0R/WM4PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M4_SETns_noc_io_pcie_soc_ip.csr101479M4 Mask interrupts for read channel440x1R/WUNSD_15_5PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr101490UNSD_15_51550x000RM16PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M16_SETns_noc_io_pcie_soc_ip.csr101501M16Mask interrupts for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M17_SETns_noc_io_pcie_soc_ip.csr101512M17Mask interrupts for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M18_SETns_noc_io_pcie_soc_ip.csr101523M18Mask interrupts for write channel18180x0R/WM19PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M19_SETns_noc_io_pcie_soc_ip.csr101534M19Mask interrupts for write channel19190x1R/WUNSD_31_20PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_31_20_SETns_noc_io_pcie_soc_ip.csr101545UNSD_31_2031200x000RM32PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M32_SETns_noc_io_pcie_soc_ip.csr101556M32Mask interrupt on traffic to PG layer32320x1R/WM33PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M33_SETns_noc_io_pcie_soc_ip.csr101567M33Mask interrupt on csr parity errors33330x0R/WM34PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M34_SETns_noc_io_pcie_soc_ip.csr101578M34RDATA parity interrupt Mask34340x1R/WM35PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M35_SETns_noc_io_pcie_soc_ip.csr101589M35RRESP parity interrupt Mask35350x1R/WM36PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M36_SETns_noc_io_pcie_soc_ip.csr101600M36BRESP parity interrupt Mask36360x1R/WM37PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M37_SETns_noc_io_pcie_soc_ip.csr101611M37AC parity interrupt Mask37370x1R/WM38PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_M38_SETns_noc_io_pcie_soc_ip.csr101622M38ACADDR parity interrupt Mask38380x1R/WE39PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E39_SETns_noc_io_pcie_soc_ip.csr101634E391'b1: R Ch Cmdtbl Parity Err Intr Mask39390x0RE40PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E40_SETns_noc_io_pcie_soc_ip.csr101646E401'b1: B Ch Cmdtbl Parity Err Intr Mask40400x0RE41PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E41_SETns_noc_io_pcie_soc_ip.csr101658E411'b1: Rx Fifo Parity Err Intr Mask41410x0RE42PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E42_SETns_noc_io_pcie_soc_ip.csr101670E421'b1: CRCD Ch Reorder Buffer Parity Err Intr Mask42420x0RE43PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E43_SETns_noc_io_pcie_soc_ip.csr101682E431'b1: Ack Ch Wack Reorder Buffer Parity Err IntrMask43430x0RE44PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E44_SETns_noc_io_pcie_soc_ip.csr101694E441'b1: Ack Ch Rack Reorder Buffer Parity Err Intr Mask44440x0RE45PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E45_SETns_noc_io_pcie_soc_ip.csr101706E451'b1: B Ch Drain Fifo Parity Err Intr Mask45450x0RE46PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E46_SETns_noc_io_pcie_soc_ip.csr101718E461'b1: R Ch Flush Fifo Parity Err Intr Mask46460x0RE47PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E47_SETns_noc_io_pcie_soc_ip.csr101730E471'b1: R Ch Deinterleaver Cmdtbl Parity Err Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_E48_SETns_noc_io_pcie_soc_ip.csr101742E481'b1: R Ch Deinterleaver Data Buffer Parity Err Intr Mask48480x0RUNSD_63_49PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_INTM_UNSD_63_49_SETns_noc_io_pcie_soc_ip.csr101753UNSD_63_4963490x0000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_ccmdbridge_p0_p1_s_12_10_as_ccmdPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101829p0_p1_s register as_ccmd0x31F00R/W0x0000000003000000Pcie_noc_bridge_p0_p1_s_12_10_as_ccmdNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr101772UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_RDY_SETns_noc_io_pcie_soc_ip.csr101783rdy1'b1: Ready24240x1R/WvalPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_VAL_SETns_noc_io_pcie_soc_ip.csr101794val1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr101805UNSD_27_2627260x0RintfidPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_INTFID_SETns_noc_io_pcie_soc_ip.csr101817intfid001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_63_31PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMD_UNSD_63_31_SETns_noc_io_pcie_soc_ip.csr101828UNSD_63_3163310x000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_ccmdmskbridge_p0_p1_s_12_10_as_ccmdmskPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101881p0_p1_s register as_ccmdmsk0x31F08R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_as_ccmdmskNot applicable for current release.falsefalsefalsefalseUNSD_23_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_23_0_SETns_noc_io_pcie_soc_ip.csr101847UNSD_23_02300x000000RrdyPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_RDY_SETns_noc_io_pcie_soc_ip.csr101858rdy1'b1: Ready24240x0R/WvalPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_VAL_SETns_noc_io_pcie_soc_ip.csr101869val1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CCMDMSK_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr101880UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_cntrbridge_p0_p1_s_12_10_as_cntrPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr101911p0_p1_s register as_cntr0x31F10R0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_as_cntrNot applicable for current release.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_CNTR_SETns_noc_io_pcie_soc_ip.csr101900CNTRCounter3100x00000000RUNSD_63_32PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_CNTR_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr101910UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_arovrdbridge_p0_p1_s_12_10_as_arovrdPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102024p0_p1_s register as_arovrd0x31F18R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_as_arovrdAR Overrides.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr101929arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr101942arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr101953arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr101964UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr101977arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr101988UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr101999arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr102012arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr102023UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_as_awovrdbridge_p0_p1_s_12_10_as_awovrdPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102137p0_p1_s register as_awovrd0x31F20R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_as_awovrdAW Overrides.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr102042awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr102055awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr102066awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr102077UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr102090awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr102101UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr102112awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr102125awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_AS_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr102136UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_p_0bridge_p0_p1_s_12_10_p_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102202p0_p1_s register p_00x33000R/W0x00000003Pcie_noc_bridge_p0_p1_s_12_10_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr102165WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr102177WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr102189WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr102201WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_p_1bridge_p0_p1_s_12_10_p_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102268p0_p1_s register p_10x33008R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr102231WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr102243WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr102255WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr102267WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_p_2bridge_p0_p1_s_12_10_p_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102334p0_p1_s register p_20x33010R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr102297WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr102309WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr102321WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr102333WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_p_3bridge_p0_p1_s_12_10_p_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102400p0_p1_s register p_30x33018R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr102363WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr102375WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr102387WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr102399WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_txebridge_p0_p1_s_12_10_txePCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102546p0_p1_s register txe0x33040R/W0x00000000Pcie_noc_bridge_p0_p1_s_12_10_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr102427TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr102439SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr102454TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr102467EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr102481FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr102495FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr102509FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr102523FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr102534PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr102545UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_txembridge_p0_p1_s_12_10_txemPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102625p0_p1_s register txem0x33048R/W0x00000008Pcie_noc_bridge_p0_p1_s_12_10_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr102569UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr102580TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr102591EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr102602UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr102613PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr102624UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_btus_0bridge_p0_p1_s_12_10_btus_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr102993p0_p1_s register btus_00x33058R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr102651L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr102662L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr102673L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr102684L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr102695L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr102706L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr102717L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr102728L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr102739L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr102750L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr102761L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr102772L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr102783L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr102794L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr102805L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr102816L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr102827L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr102838L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr102849L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr102860L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr102871L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr102882L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr102893L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr102904L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr102915L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr102926L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr102937L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr102948L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr102959L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr102970L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr102981L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr102992L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_p1_s_12_10_btus_1bridge_p0_p1_s_12_10_btus_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr103361p0_p1_s register btus_10x33060R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr103019L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr103030L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr103041L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr103052L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr103063L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr103074L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr103085L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr103096L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr103107L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr103118L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr103129L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr103140L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr103151L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr103162L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr103173L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr103184L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr103195L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr103206L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr103217L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr103228L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr103239L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr103250L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr103261L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr103272L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr103283L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr103294L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr103305L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr103316L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr103327L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr103338L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr103349L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr103360L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_p1_s_12_10_btrl_0bridge_p0_p1_s_12_10_btrl_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr103437p0_p1_s register btrl_00x33080R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr103385WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr103396RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr103411CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr103425EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr103436UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_s_12_10_btrl_1bridge_p0_p1_s_12_10_btrl_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr103513p0_p1_s register btrl_10x33088R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr103461WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr103472RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr103487CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr103501EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr103512UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_s_12_10_btrl_2bridge_p0_p1_s_12_10_btrl_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr103589p0_p1_s register btrl_20x33090R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr103537WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr103548RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr103563CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr103577EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr103588UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_s_12_10_btrl_3bridge_p0_p1_s_12_10_btrl_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr103665p0_p1_s register btrl_30x33098R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr103613WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr103624RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr103639CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr103653EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr103664UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_p1_s_12_10_btperrbridge_p0_p1_s_12_10_btperrPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr103867p0_p1_s register btperr0x330A8R/W0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr103690L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr103701L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr103712L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr103723L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr103734L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr103745L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr103756L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr103767L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr103778L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr103789L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr103800L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr103811L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr103822L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr103833L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr103844L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr103855L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr103866UNSD31160x0000Rregisterpcie_noc.bridge_p0_p1_s_12_10_btperrmbridge_p0_p1_s_12_10_btperrmPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr104067p0_p1_s register btperrm0x330B0R/W0x00000000Pcie_noc_bridge_p0_p1_s_12_10_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr103890L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr103901L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr103912L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr103923L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr103934L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr103945L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr103956L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr103967L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr103978L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr103989L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr104000L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr104011L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr104022L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr104033L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr104044L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr104055L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr104066UNSD31160x0000Rregisterpcie_noc.bridge_p0_p1_s_12_10_rxebridge_p0_p1_s_12_10_rxePCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr104175p0_p1_s register rxe0x33120R/W0x00000000Pcie_noc_bridge_p0_p1_s_12_10_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr104095CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr104106CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr104117CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr104128CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr104140EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr104151PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr104163EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr104174UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_rxembridge_p0_p1_s_12_10_rxemPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr104247p0_p1_s register rxem0x33128R/W0x00000050Pcie_noc_bridge_p0_p1_s_12_10_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr104196UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr104210EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr104221PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr104235EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr104246UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_brs_0bridge_p0_p1_s_12_10_brs_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr104521p0_p1_s register brs_00x33130R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr104271OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr104282V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr104293S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr104304B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr104315F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr104325UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr104336OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr104347V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr104358S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr104369B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr104380F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr104390UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr104401OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr104412V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr104423S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr104434B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr104445F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr104455UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr104466OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr104477V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr104488S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr104499B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr104510F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr104520UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p1_s_12_10_brs_1bridge_p0_p1_s_12_10_brs_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr104795p0_p1_s register brs_10x33138R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr104545OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr104556V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr104567S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr104578B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr104589F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr104599UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr104610OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr104621V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr104632S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr104643B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr104654F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr104664UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr104675OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr104686V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr104697S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr104708B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr104719F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr104729UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr104740OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr104751V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr104762S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr104773B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr104784F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr104794UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_p1_s_12_10_brusbridge_p0_p1_s_12_10_brusPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr104864p0_p1_s register brus0x331B0R0x00000000Pcie_noc_bridge_p0_p1_s_12_10_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr104820V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr104831V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr104842V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr104853V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr104863UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_p1_s_12_10_brperr0bridge_p0_p1_s_12_10_brperr0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105092p0_p1_s register brperr00x331D0R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr104902D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr104913DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr104924SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr104936SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr104947PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr104958UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr104969D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr104980DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr104991SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr105003SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr105014PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr105025UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr105036UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr105047UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr105058UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr105069UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr105080UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr105091UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_brperr1bridge_p0_p1_s_12_10_brperr1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105208p0_p1_s register brperr10x331D8R0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr105130UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr105141UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr105152UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr105163UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr105174UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr105185UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr105196UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr105207UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_brperrm0bridge_p0_p1_s_12_10_brperrm0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105429p0_p1_s register brperrm00x331E0R/W0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr105235D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr105247DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr105258SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr105270SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr105282PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr105293UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr105304D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr105316DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr105327SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr105339SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr105351PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr105362UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr105373UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr105384UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr105395UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr105406UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr105417UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr105428UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_p1_s_12_10_brperrm1bridge_p0_p1_s_12_10_brperrm1PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105534p0_p1_s register brperrm10x331E8R0x0000000000000000Pcie_noc_bridge_p0_p1_s_12_10_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr105456UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr105467UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr105478UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr105489UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr105500UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr105511UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr105522UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_P1_S_12_10_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr105533UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105650p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x34000R/W0x0000000058200000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr105574P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr105585NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr105596I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr105608R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_DI_SETns_noc_io_pcie_soc_ip.csr105619DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr105631LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr105642BASE_ADDRESS_0_33Base address3960x001608000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr105649UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105742p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_00x34008R/W0x000000fffffff000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m__1g_386m_4k__4k_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_P_SETns_noc_io_pcie_soc_ip.csr105667P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_NS_SETns_noc_io_pcie_soc_ip.csr105678NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_I_SETns_noc_io_pcie_soc_ip.csr105689I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr105700VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_TM_SETns_noc_io_pcie_soc_ip.csr105712TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr105723RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr105734MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M__1G_386M_4K__4K_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr105741UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105858p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_00x34020R/W0x0000000058201000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr105782P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr105793NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr105804I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr105816R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_DI_SETns_noc_io_pcie_soc_ip.csr105827DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr105839LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr105850BASE_ADDRESS_0_33Base address3960x001608040R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr105857UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr105950p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_00x34028R/W0x000000fffffff000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_386m_4k__1g_386m_8k__4k_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_P_SETns_noc_io_pcie_soc_ip.csr105875P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_NS_SETns_noc_io_pcie_soc_ip.csr105886NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_I_SETns_noc_io_pcie_soc_ip.csr105897I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr105908VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_TM_SETns_noc_io_pcie_soc_ip.csr105920TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr105931RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr105942MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_386M_4K__1G_386M_8K__4K_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr105949UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106066p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_00x34040R/W0x0000000058400000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SETns_noc_io_pcie_soc_ip.csr105990P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr106001NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SETns_noc_io_pcie_soc_ip.csr106012I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr106024R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_DI_SETns_noc_io_pcie_soc_ip.csr106035DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr106047LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr106058BASE_ADDRESS_0_33Base address3960x001610000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106065UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106158p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_00x34048R/W0x000000ffffe00000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_1g_388m__1g_390m__2m_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_P_SETns_noc_io_pcie_soc_ip.csr106083P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_NS_SETns_noc_io_pcie_soc_ip.csr106094NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_I_SETns_noc_io_pcie_soc_ip.csr106105I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr106116VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_TM_SETns_noc_io_pcie_soc_ip.csr106128TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr106139RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr106150MASK_0_33Mask3960x3ffff8000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_1G_388M__1G_390M__2M_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106157UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106274p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x34060R/W0x0000007f80000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr106198P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr106209NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr106220I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr106232R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_DI_SETns_noc_io_pcie_soc_ip.csr106243DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr106255LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr106266BASE_ADDRESS_0_33Base address3960x1fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106273UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106366p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x34068R/W0x000000fffffff000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_P_SETns_noc_io_pcie_soc_ip.csr106291P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_NS_SETns_noc_io_pcie_soc_ip.csr106302NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_I_SETns_noc_io_pcie_soc_ip.csr106313I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr106324VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_TM_SETns_noc_io_pcie_soc_ip.csr106336TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr106347RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr106358MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106365UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106407p0_spio_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_00x34070R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g__510g_4k__4k_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr106384UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr106395SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G__510G_4K__4K_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr106406UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106523p0_spio_m register am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x34080R/W0x0000007f80001000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr106447P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr106458NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr106469I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr106481R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_DI_SETns_noc_io_pcie_soc_ip.csr106492DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr106504LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr106515BASE_ADDRESS_0_33Base address3960x1fe000040R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106522UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106615p0_spio_m register am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x34088R/W0x000000fffffff000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_P_SETns_noc_io_pcie_soc_ip.csr106540P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_NS_SETns_noc_io_pcie_soc_ip.csr106551NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_I_SETns_noc_io_pcie_soc_ip.csr106562I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr106573VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_TM_SETns_noc_io_pcie_soc_ip.csr106585TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr106596RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr106607MASK_0_33Mask3960x3ffffffc0R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106614UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106656p0_spio_m register am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_00x34090R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_main0_apb_s_sr_main0_apb_s_map_r_510g_4k__510g_8k__4k_2_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr106633UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr106644SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_MAIN0_APB_S_SR_MAIN0_APB_S_MAP_R_510G_4K__510G_8K__4K_2_0_UNSD_SETns_noc_io_pcie_soc_ip.csr106655UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106772p0_spio_m register am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x340A0R/W0x0000007e80000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr106696P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr106707NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr106718I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr106730R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr106741DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr106753LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr106764BASE_ADDRESS_0_33Base address3960x1fa000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106771UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106864p0_spio_m register am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x340A8R/W0x000000ff80000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr106789P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr106800NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr106811I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr106822VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr106834TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr106845RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr106856MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr106863UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr106905p0_spio_m register am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_00x340B0R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p0_reg_s_sr_p0_p0_reg_s_map_r_506g__508g__2g_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr106882UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr106893SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P0_REG_S_SR_P0_P0_REG_S_MAP_R_506G__508G__2G_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr106904UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107021p0_spio_m register am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00x340C0R/W0x0000004000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr106945P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr106956NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr106967I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr106979R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr106990DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr107002LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr107013BASE_ADDRESS_0_33Base address3960x100000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107020UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107113p0_spio_m register am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_00x340C8R/W0x000000e000000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p0_s_sr_p0_p0_s_map_r_256g__384g__128g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_P_SETns_noc_io_pcie_soc_ip.csr107038P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr107049NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_I_SETns_noc_io_pcie_soc_ip.csr107060I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr107071VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr107083TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr107094RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr107105MASK_0_33Mask3960x380000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P0_S_SR_P0_P0_S_MAP_R_256G__384G__128G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107112UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107229p0_spio_m register am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x340E0R/W0x0000007f00000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr107153P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr107164NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr107175I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr107187R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr107198DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr107210LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr107221BASE_ADDRESS_0_33Base address3960x1fc000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107228UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107321p0_spio_m register am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x340E8R/W0x000000ff80000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_P_SETns_noc_io_pcie_soc_ip.csr107246P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr107257NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_I_SETns_noc_io_pcie_soc_ip.csr107268I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr107279VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr107291TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr107302RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr107313MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107320UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107362p0_spio_m register am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_00x340F0R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adrelocslv_mem_p0_p1_reg_s_sr_p0_p1_reg_s_map_r_508g__510g__2g_0_0See AM_ADBASE.falsefalsefalsefalseUNSD_5_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_5_0_SETns_noc_io_pcie_soc_ip.csr107339UNSD_5_0Unused500x00RSLV_RELOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_SLV_RELOC_SETns_noc_io_pcie_soc_ip.csr107350SLV_RELOCSlave Reloc3960x000000000RUNSDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADRELOCSLV_MEM_P0_P1_REG_S_SR_P0_P1_REG_S_MAP_R_508G__510G__2G_0_0_UNSD_SETns_noc_io_pcie_soc_ip.csr107361UNSDUnused63400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107478p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00x34100R/W0x0000006000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr107402P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr107413NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr107424I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_R_WN_SETns_noc_io_pcie_soc_ip.csr107436R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_DI_SETns_noc_io_pcie_soc_ip.csr107447DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_LLC_SETns_noc_io_pcie_soc_ip.csr107459LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr107470BASE_ADDRESS_0_33Base address3960x180000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107477UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107570p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_00x34108R/W0x000000f000000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_384g__448g__64g_0_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_P_SETns_noc_io_pcie_soc_ip.csr107495P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_NS_SETns_noc_io_pcie_soc_ip.csr107506NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_I_SETns_noc_io_pcie_soc_ip.csr107517I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_VAL_SETns_noc_io_pcie_soc_ip.csr107528VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_TM_SETns_noc_io_pcie_soc_ip.csr107540TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_RSV_SETns_noc_io_pcie_soc_ip.csr107551RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr107562MASK_0_33Mask3960x3c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_384G__448G__64G_0_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107569UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107686p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00x34120R/W0x0000007000000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr107610P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr107621NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr107632I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_R_WN_SETns_noc_io_pcie_soc_ip.csr107644R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_DI_SETns_noc_io_pcie_soc_ip.csr107655DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_LLC_SETns_noc_io_pcie_soc_ip.csr107667LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr107678BASE_ADDRESS_0_33Base address3960x1c0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107685UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107778p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_00x34128R/W0x000000f800000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_448g__480g__32g_1_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_P_SETns_noc_io_pcie_soc_ip.csr107703P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_NS_SETns_noc_io_pcie_soc_ip.csr107714NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_I_SETns_noc_io_pcie_soc_ip.csr107725I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_VAL_SETns_noc_io_pcie_soc_ip.csr107736VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_TM_SETns_noc_io_pcie_soc_ip.csr107748TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_RSV_SETns_noc_io_pcie_soc_ip.csr107759RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr107770MASK_0_33Mask3960x3e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_448G__480G__32G_1_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107777UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107894p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00x34140R/W0x0000007800000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr107818P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr107829NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr107840I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_R_WN_SETns_noc_io_pcie_soc_ip.csr107852R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_DI_SETns_noc_io_pcie_soc_ip.csr107863DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_LLC_SETns_noc_io_pcie_soc_ip.csr107875LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr107886BASE_ADDRESS_0_33Base address3960x1e0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107893UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr107986p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_00x34148R/W0x000000fc00000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_480g__496g__16g_2_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_P_SETns_noc_io_pcie_soc_ip.csr107911P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_NS_SETns_noc_io_pcie_soc_ip.csr107922NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_I_SETns_noc_io_pcie_soc_ip.csr107933I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_VAL_SETns_noc_io_pcie_soc_ip.csr107944VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_TM_SETns_noc_io_pcie_soc_ip.csr107956TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_RSV_SETns_noc_io_pcie_soc_ip.csr107967RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr107978MASK_0_33Mask3960x3f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_480G__496G__16G_2_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr107985UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108102p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00x34160R/W0x0000007c00000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr108026P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr108037NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr108048I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_R_WN_SETns_noc_io_pcie_soc_ip.csr108060R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_DI_SETns_noc_io_pcie_soc_ip.csr108071DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_LLC_SETns_noc_io_pcie_soc_ip.csr108083LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr108094BASE_ADDRESS_0_33Base address3960x1f0000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr108101UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108194p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_00x34168R/W0x000000fe00000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_496g__504g__8g_3_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_P_SETns_noc_io_pcie_soc_ip.csr108119P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_NS_SETns_noc_io_pcie_soc_ip.csr108130NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_I_SETns_noc_io_pcie_soc_ip.csr108141I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_VAL_SETns_noc_io_pcie_soc_ip.csr108152VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_TM_SETns_noc_io_pcie_soc_ip.csr108164TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_RSV_SETns_noc_io_pcie_soc_ip.csr108175RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr108186MASK_0_33Mask3960x3f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_496G__504G__8G_3_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr108193UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108310p0_spio_m register am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00x34180R/W0x0000007e00000000Pcie_noc_bridge_p0_spio_m_5_7_am_adbase_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0These registers specify the base addresses and masks of different slave ranges accessible from this master. One base, mask, and reloc register set per address range assigned to the master. These registers are programmable only if address range programmability is enabled on the master through NocStudio property. When programmability is disabled, these are read-only registers with values specified through NocStudio's add_range properties. A slave address range is specified using the above base address and mask pair. An address on the AR or AW channel has a match against a range if it satisfies the equation AxADDRS & AM_ADMASK[i] == AM_ADBASE[i] Note that programmed 'base' must already factor the 'mask'. The base should not have a 1'b1 bit where the corresponding mask bit is 1'b0. What this means is that the programmed base should already have performed a bit-wise AND operation with the 'mask'. An address which doesn't match any range results in a decode error response. Note that programming of these registers must ensure that an address matches only against one range. Match against multiple ranges is a fatal error and will raise an interrupt. Address ranges are specified at 64B cache line boundary. Lower six bits if AM_ADBASE and AM_ADMASK are used for specifying access permissions on an address range.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr108234P1'b1: Privileged000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr108245NS1'b1: Non-secure110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr108256I1'b1: Instruction220x0R/WR_WnPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_R_WN_SETns_noc_io_pcie_soc_ip.csr108268R_Wn1'b1: Read enabled to range1'b0: Write enabled to range330x0R/WDIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_DI_SETns_noc_io_pcie_soc_ip.csr108279DI1'b1: Address range disabled440x0R/WLLCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_LLC_SETns_noc_io_pcie_soc_ip.csr108291LLCLLC disable550x0RBASE_ADDRESS_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BASE_ADDRESS_0_33_SETns_noc_io_pcie_soc_ip.csr108302BASE_ADDRESS_0_33Base address3960x1f8000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADBASE_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr108309UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108402p0_spio_m register am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_00x34188R/W0x000000ff80000000Pcie_noc_bridge_p0_spio_m_5_7_am_admask_mem_p0_p1_s_sr_p0_p1_s_map_r_504g__506g__2g_4_0See AM_ADBASE.falsefalsefalsefalsePPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_P_SETns_noc_io_pcie_soc_ip.csr108327P1'b1: Privileged field is valid000x0R/WNSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_NS_SETns_noc_io_pcie_soc_ip.csr108338NS1'b1: Non-secure field is valid110x0R/WIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_I_SETns_noc_io_pcie_soc_ip.csr108349I1'b1: Instruction field is valid220x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_VAL_SETns_noc_io_pcie_soc_ip.csr108360VAL1'b1: R_Wn field is valid330x0R/WTMPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_TM_SETns_noc_io_pcie_soc_ip.csr108372TM1'b1: Enable Trusted Master behavior for secure transactions440x0R/WRSVPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_RSV_SETns_noc_io_pcie_soc_ip.csr108383RSVReserved550x0R/WMASK_0_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_MASK_0_33_SETns_noc_io_pcie_soc_ip.csr108394MASK_0_33Mask3960x3fe000000R/WUNSD_34_57PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ADMASK_MEM_P0_P1_S_SR_P0_P1_S_MAP_R_504G__506G__2G_4_0_UNSD_34_57_SETns_noc_io_pcie_soc_ip.csr108401UNSD_34_5763400x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_p_0bridge_p0_spio_m_5_7_p_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108467p0_spio_m register p_00x37000R/W0x00000003Pcie_noc_bridge_p0_spio_m_5_7_p_0This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_0_SETns_noc_io_pcie_soc_ip.csr108430WT_QOS_0Weight of QoS profile 0700x03R/WWT_QOS_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_1_SETns_noc_io_pcie_soc_ip.csr108442WT_QOS_1Weight of QoS profile 11580x00RWT_QOS_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_2_SETns_noc_io_pcie_soc_ip.csr108454WT_QOS_2Weight of QoS profile 223160x00RWT_QOS_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_0_WT_QOS_3_SETns_noc_io_pcie_soc_ip.csr108466WT_QOS_3Weight of QoS profile 331240x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_p_1bridge_p0_spio_m_5_7_p_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108533p0_spio_m register p_10x37008R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_p_1This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_4_SETns_noc_io_pcie_soc_ip.csr108496WT_QOS_4Weight of QoS profile 4700x00RWT_QOS_5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_5_SETns_noc_io_pcie_soc_ip.csr108508WT_QOS_5Weight of QoS profile 51580x00RWT_QOS_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_6_SETns_noc_io_pcie_soc_ip.csr108520WT_QOS_6Weight of QoS profile 623160x00RWT_QOS_7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_1_WT_QOS_7_SETns_noc_io_pcie_soc_ip.csr108532WT_QOS_7Weight of QoS profile 731240x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_p_2bridge_p0_spio_m_5_7_p_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108599p0_spio_m register p_20x37010R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_p_2This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_8_SETns_noc_io_pcie_soc_ip.csr108562WT_QOS_8Weight of QoS profile 8700x00RWT_QOS_9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_9_SETns_noc_io_pcie_soc_ip.csr108574WT_QOS_9Weight of QoS profile 91580x00RWT_QOS_10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_10_SETns_noc_io_pcie_soc_ip.csr108586WT_QOS_10Weight of QoS profile 1023160x00RWT_QOS_11PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_2_WT_QOS_11_SETns_noc_io_pcie_soc_ip.csr108598WT_QOS_11Weight of QoS profile 1131240x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_p_3bridge_p0_spio_m_5_7_p_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108665p0_spio_m register p_30x37018R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_p_3This register describes the weight value of each QoS supported at the bridge. Each byte of this register must be greater than or equal to 3. Each transmitting bridge supports up to 16 QoS profiles. Each QoS is composed of pri and weight, however only the weight is programmable, therefore is part of the registers.QoS data is composed of four registers, P0, P1, P2 and P3, each of which contains the weight of four profiles. Depending upon how many QoS profiles are enabled, the appropriate bits in the following registers are available.falsefalsefalsefalseWT_QOS_12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_12_SETns_noc_io_pcie_soc_ip.csr108628WT_QOS_12Weight of QoS profile 12700x00RWT_QOS_13PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_13_SETns_noc_io_pcie_soc_ip.csr108640WT_QOS_13Weight of QoS profile 131580x00RWT_QOS_14PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_14_SETns_noc_io_pcie_soc_ip.csr108652WT_QOS_14Weight of QoS profile 1423160x00RWT_QOS_15PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_P_3_WT_QOS_15_SETns_noc_io_pcie_soc_ip.csr108664WT_QOS_15Weight of QoS profile 1531240x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_txebridge_p0_spio_m_5_7_txePCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108811p0_spio_m register txe0x37040R/W0x00000000Pcie_noc_bridge_p0_spio_m_5_7_txeThis register tracks error or interrupt conditions. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared. This register works in combination with the Transmit Interrupt Mask register to determine when an interrupt is transmitted.falsefalsefalsefalseTRANS_WITHOUT_SOPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_WITHOUT_SOP_SETns_noc_io_pcie_soc_ip.csr108692TRANS_WITHOUT_SOP1'b1: Sets if a transaction is initiated w/o SOP, this event will always trigger an interrupt and cannot be masked.000x0R/WSOP_AFTER_SOPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_SOP_AFTER_SOP_SETns_noc_io_pcie_soc_ip.csr108704SOP_AFTER_SOP1'b1: Sets if a SOP is received after SOP, this event will always trigger an interrupt and cannot be masked.110x0R/WTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr108719TRANS_ILLEGAL_DEST_QOS1'b1: Sets if a transaction is received from bridge for which there is no entry present in the vcmap, i.e. the destination and/or QoS is not supported, this is a decode error. This event can be masked to not send an interrupt, but the packet will be dropped in the bridge.220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr108732EVENT_CNTR_OVERFLOW1'b1: Sets if the event counter overflows, this event can be masked so that no interrupt is sent on an overflow condition330x0R/WFIFO_OVERFLOW_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_A_SETns_noc_io_pcie_soc_ip.csr108746FIFO_OVERFLOW_AHost interface FIFO A overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked440x0R/WFIFO_OVERFLOW_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_B_SETns_noc_io_pcie_soc_ip.csr108760FIFO_OVERFLOW_BHost interface FIFO B overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked550x0R/WFIFO_OVERFLOW_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_C_SETns_noc_io_pcie_soc_ip.csr108774FIFO_OVERFLOW_CHost interface FIFO C overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked660x0R/WFIFO_OVERFLOW_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_FIFO_OVERFLOW_D_SETns_noc_io_pcie_soc_ip.csr108788FIFO_OVERFLOW_DHost interface FIFO D overflow. Indicates that one of the per-interface FIFOs at the transmitting bridge to NoC has overflowed. This event will always trigger an interrupt and cannot be masked770x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr108799PARITY_ERRRegister parity error interrupt.880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXE_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr108810UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_txembridge_p0_spio_m_5_7_txemPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr108890p0_spio_m register txem0x37048R/W0x00000008Pcie_noc_bridge_p0_spio_m_5_7_txemThis register is used to decide which of the error/interrupt events specified in the Transmit Interrupt Status register should trigger an interrupt. Since only the events in bit 2 and 3 can be masked, only bit 2 and 3 are used in this register. When one of the bits in this register is set to 1, the corresponding interrupt event will not send an interrupt to the system.falsefalsefalsefalseUNSD_1_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_1_0_SETns_noc_io_pcie_soc_ip.csr108834UNSD_1_0100x0RTRANS_ILLEGAL_DEST_QOSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_TRANS_ILLEGAL_DEST_QOS_SETns_noc_io_pcie_soc_ip.csr108845TRANS_ILLEGAL_DEST_QOSInterrupt mask for illegal destination QoS220x0R/WEVENT_CNTR_OVERFLOWPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_EVENT_CNTR_OVERFLOW_SETns_noc_io_pcie_soc_ip.csr108856EVENT_CNTR_OVERFLOWInterrupt mask for event counter overflow330x1R/WUNSD_7_4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_7_4_SETns_noc_io_pcie_soc_ip.csr108867UNSD_7_4740x0RPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr108878PARITY_ERR_MASKInterrupt mask for register parity error880x0R/WUNSD_31_9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_TXEM_UNSD_31_9_SETns_noc_io_pcie_soc_ip.csr108889UNSD_31_93190x000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_btus_0bridge_p0_spio_m_5_7_btus_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr109258p0_spio_m register btus_00x37058R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btus_0These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL0_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_A_SETns_noc_io_pcie_soc_ip.csr108916L0_AInterface upsizer status for interface A, Layer 0000x0RL0_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_B_SETns_noc_io_pcie_soc_ip.csr108927L0_BInterface upsizer status for interface B, Layer 0110x0RL0_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_C_SETns_noc_io_pcie_soc_ip.csr108938L0_CInterface upsizer status for interface C, Layer 0220x0RL0_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L0_D_SETns_noc_io_pcie_soc_ip.csr108949L0_DInterface upsizer status for interface D, Layer 0330x0RL1_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_A_SETns_noc_io_pcie_soc_ip.csr108960L1_AInterface upsizer status for interface A, Layer 1440x0RL1_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_B_SETns_noc_io_pcie_soc_ip.csr108971L1_BInterface upsizer status for interface B, Layer 1550x0RL1_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_C_SETns_noc_io_pcie_soc_ip.csr108982L1_CInterface upsizer status for interface C, Layer 1660x0RL1_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L1_D_SETns_noc_io_pcie_soc_ip.csr108993L1_DInterface upsizer status for interface D, Layer 1770x0RL2_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_A_SETns_noc_io_pcie_soc_ip.csr109004L2_AInterface upsizer status for interface A, Layer 2880x0RL2_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_B_SETns_noc_io_pcie_soc_ip.csr109015L2_BInterface upsizer status for interface B, Layer 2990x0RL2_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_C_SETns_noc_io_pcie_soc_ip.csr109026L2_CInterface upsizer status for interface C, Layer 210100x0RL2_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L2_D_SETns_noc_io_pcie_soc_ip.csr109037L2_DInterface upsizer status for interface D, Layer 211110x0RL3_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_A_SETns_noc_io_pcie_soc_ip.csr109048L3_AInterface upsizer status for interface A, Layer 312120x0RL3_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_B_SETns_noc_io_pcie_soc_ip.csr109059L3_BInterface upsizer status for interface B, Layer 313130x0RL3_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_C_SETns_noc_io_pcie_soc_ip.csr109070L3_CInterface upsizer status for interface C, Layer 314140x0RL3_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L3_D_SETns_noc_io_pcie_soc_ip.csr109081L3_DInterface upsizer status for interface D, Layer 315150x0RL4_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_A_SETns_noc_io_pcie_soc_ip.csr109092L4_AInterface upsizer status for interface A, Layer 416160x0RL4_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_B_SETns_noc_io_pcie_soc_ip.csr109103L4_BInterface upsizer status for interface B, Layer 417170x0RL4_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_C_SETns_noc_io_pcie_soc_ip.csr109114L4_CInterface upsizer status for interface C, Layer 418180x0RL4_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L4_D_SETns_noc_io_pcie_soc_ip.csr109125L4_DInterface upsizer status for interface D, Layer 419190x0RL5_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_A_SETns_noc_io_pcie_soc_ip.csr109136L5_AInterface upsizer status for interface A, Layer 520200x0RL5_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_B_SETns_noc_io_pcie_soc_ip.csr109147L5_BInterface upsizer status for interface B, Layer 521210x0RL5_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_C_SETns_noc_io_pcie_soc_ip.csr109158L5_CInterface upsizer status for interface C, Layer 522220x0RL5_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L5_D_SETns_noc_io_pcie_soc_ip.csr109169L5_DInterface upsizer status for interface D, Layer 523230x0RL6_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_A_SETns_noc_io_pcie_soc_ip.csr109180L6_AInterface upsizer status for interface A, Layer 624240x0RL6_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_B_SETns_noc_io_pcie_soc_ip.csr109191L6_BInterface upsizer status for interface B, Layer 625250x0RL6_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_C_SETns_noc_io_pcie_soc_ip.csr109202L6_CInterface upsizer status for interface C, Layer 626260x0RL6_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L6_D_SETns_noc_io_pcie_soc_ip.csr109213L6_DInterface upsizer status for interface D, Layer 627270x0RL7_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_A_SETns_noc_io_pcie_soc_ip.csr109224L7_AInterface upsizer status for interface A, Layer 728280x0RL7_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_B_SETns_noc_io_pcie_soc_ip.csr109235L7_BInterface upsizer status for interface B, Layer 729290x0RL7_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_C_SETns_noc_io_pcie_soc_ip.csr109246L7_CInterface upsizer status for interface C, Layer 730300x0RL7_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_0_L7_D_SETns_noc_io_pcie_soc_ip.csr109257L7_DInterface upsizer status for interface D, Layer 731310x0Rregisterpcie_noc.bridge_p0_spio_m_5_7_btus_1bridge_p0_spio_m_5_7_btus_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr109626p0_spio_m register btus_10x37060R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btus_1These two registers (BTUS_0 and BTUS_1) track the status of the bridge transmitter upsizer/downsize structure. They can be used with the other status registers to check for packets that are still occupying the bridge. Each NoC layer, up to 16, can have upsizing/downsizing logic, and these 2 registers track the status of all 16 layers (BTUS_0 from 0 to 7 and BTUS_1 from 8 to 15).falsefalsefalsefalseL8_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_A_SETns_noc_io_pcie_soc_ip.csr109284L8_AInterface upsizer status for interface A, Layer 8000x0RL8_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_B_SETns_noc_io_pcie_soc_ip.csr109295L8_BInterface upsizer status for interface B, Layer 8110x0RL8_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_C_SETns_noc_io_pcie_soc_ip.csr109306L8_CInterface upsizer status for interface C, Layer 8220x0RL8_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L8_D_SETns_noc_io_pcie_soc_ip.csr109317L8_DInterface upsizer status for interface D, Layer 8330x0RL9_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_A_SETns_noc_io_pcie_soc_ip.csr109328L9_AInterface upsizer status for interface A, Layer 9440x0RL9_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_B_SETns_noc_io_pcie_soc_ip.csr109339L9_BInterface upsizer status for interface B, Layer 9550x0RL9_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_C_SETns_noc_io_pcie_soc_ip.csr109350L9_CInterface upsizer status for interface C, Layer 9660x0RL9_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L9_D_SETns_noc_io_pcie_soc_ip.csr109361L9_DInterface upsizer status for interface D, Layer 9770x0RL10_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_A_SETns_noc_io_pcie_soc_ip.csr109372L10_AInterface upsizer status for interface A, Layer 10880x0RL10_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_B_SETns_noc_io_pcie_soc_ip.csr109383L10_BInterface upsizer status for interface B, Layer 10990x0RL10_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_C_SETns_noc_io_pcie_soc_ip.csr109394L10_CInterface upsizer status for interface C, Layer 1010100x0RL10_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L10_D_SETns_noc_io_pcie_soc_ip.csr109405L10_DInterface upsizer status for interface D, Layer 1011110x0RL11_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_A_SETns_noc_io_pcie_soc_ip.csr109416L11_AInterface upsizer status for interface A, Layer 1112120x0RL11_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_B_SETns_noc_io_pcie_soc_ip.csr109427L11_BInterface upsizer status for interface B, Layer 1113130x0RL11_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_C_SETns_noc_io_pcie_soc_ip.csr109438L11_CInterface upsizer status for interface C, Layer 1114140x0RL11_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L11_D_SETns_noc_io_pcie_soc_ip.csr109449L11_DInterface upsizer status for interface D, Layer 1115150x0RL12_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_A_SETns_noc_io_pcie_soc_ip.csr109460L12_AInterface upsizer status for interface A, Layer 1216160x0RL12_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_B_SETns_noc_io_pcie_soc_ip.csr109471L12_BInterface upsizer status for interface B, Layer 1217170x0RL12_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_C_SETns_noc_io_pcie_soc_ip.csr109482L12_CInterface upsizer status for interface C, Layer 1218180x0RL12_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L12_D_SETns_noc_io_pcie_soc_ip.csr109493L12_DInterface upsizer status for interface D, Layer 1219190x0RL13_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_A_SETns_noc_io_pcie_soc_ip.csr109504L13_AInterface upsizer status for interface A, Layer 1320200x0RL13_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_B_SETns_noc_io_pcie_soc_ip.csr109515L13_BInterface upsizer status for interface B, Layer 1321210x0RL13_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_C_SETns_noc_io_pcie_soc_ip.csr109526L13_CInterface upsizer status for interface C, Layer 1322220x0RL13_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L13_D_SETns_noc_io_pcie_soc_ip.csr109537L13_DInterface upsizer status for interface D, Layer 1323230x0RL14_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_A_SETns_noc_io_pcie_soc_ip.csr109548L14_AInterface upsizer status for interface A, Layer 1424240x0RL14_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_B_SETns_noc_io_pcie_soc_ip.csr109559L14_BInterface upsizer status for interface B, Layer 1425250x0RL14_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_C_SETns_noc_io_pcie_soc_ip.csr109570L14_CInterface upsizer status for interface C, Layer 1426260x0RL14_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L14_D_SETns_noc_io_pcie_soc_ip.csr109581L14_DInterface upsizer status for interface D, Layer 1427270x0RL15_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_A_SETns_noc_io_pcie_soc_ip.csr109592L15_AInterface upsizer status for interface A, Layer 1528280x0RL15_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_B_SETns_noc_io_pcie_soc_ip.csr109603L15_BInterface upsizer status for interface B, Layer 1529290x0RL15_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_C_SETns_noc_io_pcie_soc_ip.csr109614L15_CInterface upsizer status for interface C, Layer 1530300x0RL15_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTUS_1_L15_D_SETns_noc_io_pcie_soc_ip.csr109625L15_DInterface upsizer status for interface D, Layer 1531310x0Rregisterpcie_noc.bridge_p0_spio_m_5_7_btrl_0bridge_p0_spio_m_5_7_btrl_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr109702p0_spio_m register btrl_00x37080R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btrl_0This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_WT_SETns_noc_io_pcie_soc_ip.csr109650WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr109661RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_CNT_SETns_noc_io_pcie_soc_ip.csr109676CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_EN_SETns_noc_io_pcie_soc_ip.csr109690EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_0_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr109701UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_spio_m_5_7_btrl_1bridge_p0_spio_m_5_7_btrl_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr109778p0_spio_m register btrl_10x37088R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btrl_1This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_WT_SETns_noc_io_pcie_soc_ip.csr109726WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr109737RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_CNT_SETns_noc_io_pcie_soc_ip.csr109752CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_EN_SETns_noc_io_pcie_soc_ip.csr109766EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_1_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr109777UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_spio_m_5_7_btrl_2bridge_p0_spio_m_5_7_btrl_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr109854p0_spio_m register btrl_20x37090R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btrl_2This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_WT_SETns_noc_io_pcie_soc_ip.csr109802WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr109813RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_CNT_SETns_noc_io_pcie_soc_ip.csr109828CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_EN_SETns_noc_io_pcie_soc_ip.csr109842EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_2_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr109853UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_spio_m_5_7_btrl_3bridge_p0_spio_m_5_7_btrl_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr109930p0_spio_m register btrl_30x37098R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btrl_3This is a register per host interface of Tx Bridge for QoS, used to control the rate of Traffic injection from host to the NoC.falsefalsefalsefalseWTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_WT_SETns_noc_io_pcie_soc_ip.csr109878WTStarting Weight, for traffic issue to the NoC from the host interface. When the value is set to 0, it is interpreted as 1.1100x000RRESV_15_12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_RESV_15_12_SETns_noc_io_pcie_soc_ip.csr109889RESV_15_1215120x0RCNTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_CNT_SETns_noc_io_pcie_soc_ip.csr109904CNTMax Count Value for Token. Anytime the token count is greater than zero, the host gets qualified to inject message into NoC. When the value is set to 0, it is interpreted as 1.19160x0RENPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_EN_SETns_noc_io_pcie_soc_ip.csr109918EN1'b1: Rate limit logic enable, rate limiter logic is used for arbitration only.1'b0: Rate limit logic disable20200x0RUNSD_31_21PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTRL_3_UNSD_31_21_SETns_noc_io_pcie_soc_ip.csr109929UNSD_31_2131210x000Rregisterpcie_noc.bridge_p0_spio_m_5_7_btperrbridge_p0_spio_m_5_7_btperrPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr110132p0_spio_m register btperr0x370A8R/W0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btperrTransmit bridge parity error status register. One register bits per layer, to monitor error in credit return signals from the downstream port. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L0_SETns_noc_io_pcie_soc_ip.csr109955L01'b1: Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L1_SETns_noc_io_pcie_soc_ip.csr109966L11'b1: Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L2_SETns_noc_io_pcie_soc_ip.csr109977L21'b1: Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L3_SETns_noc_io_pcie_soc_ip.csr109988L31'b1: Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L4_SETns_noc_io_pcie_soc_ip.csr109999L41'b1: Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L5_SETns_noc_io_pcie_soc_ip.csr110010L51'b1: Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L6_SETns_noc_io_pcie_soc_ip.csr110021L61'b1: Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L7_SETns_noc_io_pcie_soc_ip.csr110032L71'b1: Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L8_SETns_noc_io_pcie_soc_ip.csr110043L81'b1: Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L9_SETns_noc_io_pcie_soc_ip.csr110054L91'b1: Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L10_SETns_noc_io_pcie_soc_ip.csr110065L101'b1: Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L11_SETns_noc_io_pcie_soc_ip.csr110076L111'b1: Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L12_SETns_noc_io_pcie_soc_ip.csr110087L121'b1: Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L13_SETns_noc_io_pcie_soc_ip.csr110098L131'b1: Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L14_SETns_noc_io_pcie_soc_ip.csr110109L141'b1: Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_L15_SETns_noc_io_pcie_soc_ip.csr110120L151'b1: Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERR_UNSD_SETns_noc_io_pcie_soc_ip.csr110131UNSD31160x0000Rregisterpcie_noc.bridge_p0_spio_m_5_7_btperrmbridge_p0_spio_m_5_7_btperrmPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr110332p0_spio_m register btperrm0x370B0R/W0x00000000Pcie_noc_bridge_p0_spio_m_5_7_btperrmMask register for transmit bridge parity error interrupts. One mask register bit for each parity status bit in BTPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.falsefalsefalsefalseL0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L0_SETns_noc_io_pcie_soc_ip.csr110155L01'b1: Interrupt Mask Credit parity error on layer 0000x0R/WL1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L1_SETns_noc_io_pcie_soc_ip.csr110166L11'b1: Interrupt Mask Credit parity error on layer 1110x0R/WL2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L2_SETns_noc_io_pcie_soc_ip.csr110177L21'b1: Interrupt Mask Credit parity error on layer 2220x0R/WL3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L3_SETns_noc_io_pcie_soc_ip.csr110188L31'b1: Interrupt Mask Credit parity error on layer 3330x0R/WL4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L4_SETns_noc_io_pcie_soc_ip.csr110199L41'b1: Interrupt Mask Credit parity error on layer 4440x0R/WL5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L5_SETns_noc_io_pcie_soc_ip.csr110210L51'b1: Interrupt Mask Credit parity error on layer 5550x0R/WL6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L6_SETns_noc_io_pcie_soc_ip.csr110221L61'b1: Interrupt Mask Credit parity error on layer 6660x0R/WL7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L7_SETns_noc_io_pcie_soc_ip.csr110232L71'b1: Interrupt Mask Credit parity error on layer 7770x0R/WL8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L8_SETns_noc_io_pcie_soc_ip.csr110243L81'b1: Interrupt Mask Credit parity error on layer 8880x0R/WL9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L9_SETns_noc_io_pcie_soc_ip.csr110254L91'b1: Interrupt Mask Credit parity error on layer 9990x0R/WL10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L10_SETns_noc_io_pcie_soc_ip.csr110265L101'b1: Interrupt Mask Credit parity error on layer 1010100x0R/WL11PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L11_SETns_noc_io_pcie_soc_ip.csr110276L111'b1: Interrupt Mask Credit parity error on layer 1111110x0R/WL12PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L12_SETns_noc_io_pcie_soc_ip.csr110287L121'b1: Interrupt Mask Credit parity error on layer 1212120x0R/WL13PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L13_SETns_noc_io_pcie_soc_ip.csr110298L131'b1: Interrupt Mask Credit parity error on layer 1313130x0R/WL14PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L14_SETns_noc_io_pcie_soc_ip.csr110309L141'b1: Interrupt Mask Credit parity error on layer 1414140x0R/WL15PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_L15_SETns_noc_io_pcie_soc_ip.csr110320L151'b1: Interrupt Mask Credit parity error on layer 1515150x0R/WUNSDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BTPERRM_UNSD_SETns_noc_io_pcie_soc_ip.csr110331UNSD31160x0000Rregisterpcie_noc.bridge_p0_spio_m_5_7_rxebridge_p0_spio_m_5_7_rxePCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr110440p0_spio_m register rxe0x37120R/W0x00000000Pcie_noc_bridge_p0_spio_m_5_7_rxeThis register tracks the interrupt events in the receive portion of the streaming bridge. It resets to 0, but as these conditions occur, the corresponding bits are set to 1. This register can be read and can also be cleared by sending a write with bits set to 0 for the bits that should be cleared.There are four events that can signal an interrupt. If the host sends more credits than the streaming bridge can take, it will signal an interrupt to indicate a protocol violation has occurred. Each interface has its own status bit. These interrupts cannot be masked.falsefalsefalsefalseCRC_OFLW_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_A_SETns_noc_io_pcie_soc_ip.csr110360CRC_OFLW_ACredit counter overflow for interface A000x0R/WCRC_OFLW_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_B_SETns_noc_io_pcie_soc_ip.csr110371CRC_OFLW_BCredit counter overflow for interface B110x0R/WCRC_OFLW_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_C_SETns_noc_io_pcie_soc_ip.csr110382CRC_OFLW_CCredit counter overflow for interface C220x0R/WCRC_OFLW_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_CRC_OFLW_D_SETns_noc_io_pcie_soc_ip.csr110393CRC_OFLW_DCredit counter overflow for interface D330x0R/WEVC_OFLWPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC_OFLW_SETns_noc_io_pcie_soc_ip.csr110405EVC_OFLWEvent counter overflow. This event can be masked so that no interrupt is sent on an overflow condition.440x0R/WPARITY_ERRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_PARITY_ERR_SETns_noc_io_pcie_soc_ip.csr110416PARITY_ERRRegister parity error interrupt550x0R/WEVC1_OFLWPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_EVC1_OFLW_SETns_noc_io_pcie_soc_ip.csr110428EVC1_OFLWEvent counter1 overflow. This event can be masked so that no interrupt is sent on an overflow condition.660x0R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXE_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr110439UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_rxembridge_p0_spio_m_5_7_rxemPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr110512p0_spio_m register rxem0x37128R/W0x00000050Pcie_noc_bridge_p0_spio_m_5_7_rxemThis register is used to decide which of the error/interrupt events specified in the RXE register should trigger an interrupt.falsefalsefalsefalseUNSD_3_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_3_0_SETns_noc_io_pcie_soc_ip.csr110461UNSD_3_0300x0REVC_OFLW_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr110475EVC_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.440x1R/WPARITY_ERR_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_PARITY_ERR_MASK_SETns_noc_io_pcie_soc_ip.csr110486PARITY_ERR_MASKInterrupt mask for register parity error.550x0R/WEVC1_OFLW_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_EVC1_OFLW_MASK_SETns_noc_io_pcie_soc_ip.csr110500EVC1_OFLW_MASK1'b1: When is set to 1, the corresponding interrupt event will not send an interrupt to the system.1'b0: The corresponding interrupt event will send an interrupt to the system.660x1R/WUNSD_31_7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_RXEM_UNSD_31_7_SETns_noc_io_pcie_soc_ip.csr110511UNSD_31_73170x0000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_brs_0bridge_p0_spio_m_5_7_brs_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr110786p0_spio_m register brs_00x37130R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_brs_0These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_0_SETns_noc_io_pcie_soc_ip.csr110536OUTI_0Head flit output interface for VC 0 Layer 0100x0RV_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_0_SETns_noc_io_pcie_soc_ip.csr110547V_0Head flit (buffer ready) for VC 0 Layer 0220x0RS_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_0_SETns_noc_io_pcie_soc_ip.csr110558S_0Head flit sop for VC 0 Layer 0330x0RB_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_0_SETns_noc_io_pcie_soc_ip.csr110569B_0Head flit barrier state for VC 0 Layer 0440x0RF_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_0_SETns_noc_io_pcie_soc_ip.csr110580F_0Buffer full for VC 0 Layer 0550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr110590UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_1_SETns_noc_io_pcie_soc_ip.csr110601OUTI_1Head flit output interface for VC 1 Layer 0980x0RV_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_1_SETns_noc_io_pcie_soc_ip.csr110612V_1Head flit (buffer ready) for VC 1 Layer 010100x0RS_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_1_SETns_noc_io_pcie_soc_ip.csr110623S_1Head flit sop for VC 1 Layer 011110x0RB_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_1_SETns_noc_io_pcie_soc_ip.csr110634B_1Head flit barrier state for VC 1 Layer 012120x0RF_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_1_SETns_noc_io_pcie_soc_ip.csr110645F_1Buffer full for VC 1 Layer 013130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr110655UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_2_SETns_noc_io_pcie_soc_ip.csr110666OUTI_2Head flit output interface for VC 2 Layer 017160x0RV_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_2_SETns_noc_io_pcie_soc_ip.csr110677V_2Head flit (buffer ready) for VC 2 Layer 018180x0RS_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_2_SETns_noc_io_pcie_soc_ip.csr110688S_2Head flit sop for VC 2 Layer 019190x0RB_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_2_SETns_noc_io_pcie_soc_ip.csr110699B_2Head flit barrier state for VC 2 Layer 020200x0RF_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_2_SETns_noc_io_pcie_soc_ip.csr110710F_2Buffer full for VC 2 Layer 021210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr110720UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_OUTI_3_SETns_noc_io_pcie_soc_ip.csr110731OUTI_3Head flit output interface for VC 3 Layer 025240x0RV_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_V_3_SETns_noc_io_pcie_soc_ip.csr110742V_3Head flit (buffer ready) for VC 3 Layer 026260x0RS_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_S_3_SETns_noc_io_pcie_soc_ip.csr110753S_3Head flit sop for VC 3 Layer 027270x0RB_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_B_3_SETns_noc_io_pcie_soc_ip.csr110764B_3Head flit barrier state for VC 3 Layer 028280x0RF_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_F_3_SETns_noc_io_pcie_soc_ip.csr110775F_3Buffer full for VC 3 Layer 029290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_0_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr110785UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_spio_m_5_7_brs_1bridge_p0_spio_m_5_7_brs_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111060p0_spio_m register brs_10x37138R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_brs_1These registers track the status of the bridge's receive FIFOs from the NoC. Since there are up to 16 layers of the NoC, there are up to 16 registers, one per active layer. Each register tracks the status of the active virtual channels for the layer (up to 4 active VCs within a layer).falsefalsefalsefalseOUTI_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_0_SETns_noc_io_pcie_soc_ip.csr110810OUTI_0Head flit output interface for VC 0 Layer 1100x0RV_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_0_SETns_noc_io_pcie_soc_ip.csr110821V_0Head flit (buffer ready) for VC 0 Layer 1220x0RS_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_0_SETns_noc_io_pcie_soc_ip.csr110832S_0Head flit sop for VC 0 Layer 1330x0RB_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_0_SETns_noc_io_pcie_soc_ip.csr110843B_0Head flit barrier state for VC 0 Layer 1440x0RF_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_0_SETns_noc_io_pcie_soc_ip.csr110854F_0Buffer full for VC 0 Layer 1550x0RUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr110864UNSD_7_6760x0ROUTI_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_1_SETns_noc_io_pcie_soc_ip.csr110875OUTI_1Head flit output interface for VC 1 Layer 1980x0RV_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_1_SETns_noc_io_pcie_soc_ip.csr110886V_1Head flit (buffer ready) for VC 1 Layer 110100x0RS_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_1_SETns_noc_io_pcie_soc_ip.csr110897S_1Head flit sop for VC 1 Layer 111110x0RB_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_1_SETns_noc_io_pcie_soc_ip.csr110908B_1Head flit barrier state for VC 1 Layer 112120x0RF_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_1_SETns_noc_io_pcie_soc_ip.csr110919F_1Buffer full for VC 1 Layer 113130x0RUNSD_15_14PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_15_14_SETns_noc_io_pcie_soc_ip.csr110929UNSD_15_1415140x0ROUTI_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_2_SETns_noc_io_pcie_soc_ip.csr110940OUTI_2Head flit output interface for VC 2 Layer 117160x0RV_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_2_SETns_noc_io_pcie_soc_ip.csr110951V_2Head flit (buffer ready) for VC 2 Layer 118180x0RS_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_2_SETns_noc_io_pcie_soc_ip.csr110962S_2Head flit sop for VC 2 Layer 119190x0RB_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_2_SETns_noc_io_pcie_soc_ip.csr110973B_2Head flit barrier state for VC 2 Layer 120200x0RF_2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_2_SETns_noc_io_pcie_soc_ip.csr110984F_2Buffer full for VC 2 Layer 121210x0RUNSD_23_22PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_23_22_SETns_noc_io_pcie_soc_ip.csr110994UNSD_23_2223220x0ROUTI_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_OUTI_3_SETns_noc_io_pcie_soc_ip.csr111005OUTI_3Head flit output interface for VC 3 Layer 125240x0RV_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_V_3_SETns_noc_io_pcie_soc_ip.csr111016V_3Head flit (buffer ready) for VC 3 Layer 126260x0RS_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_S_3_SETns_noc_io_pcie_soc_ip.csr111027S_3Head flit sop for VC 3 Layer 127270x0RB_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_B_3_SETns_noc_io_pcie_soc_ip.csr111038B_3Head flit barrier state for VC 3 Layer 128280x0RF_3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_F_3_SETns_noc_io_pcie_soc_ip.csr111049F_3Buffer full for VC 3 Layer 129290x0RUNSD_31_30PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRS_1_UNSD_31_30_SETns_noc_io_pcie_soc_ip.csr111059UNSD_31_3031300x0Rregisterpcie_noc.bridge_p0_spio_m_5_7_brusbridge_p0_spio_m_5_7_brusPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111129p0_spio_m register brus0x371B0R0x00000000Pcie_noc_bridge_p0_spio_m_5_7_brusThis register tracks the status of the bridge receiver upsizer/downsize structure. It can be used with the other status registers to check for packets that are still occupying the bridge. Each of the host's receiving interfaces, up to 4, can have upsizing/downsizing logic, and this register tracks the status of all 4 interfaces.falsefalsefalsefalseV_APCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_A_SETns_noc_io_pcie_soc_ip.csr111085V_AInterface A upsizer/downsizer valid000x0RV_BPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_B_SETns_noc_io_pcie_soc_ip.csr111096V_BInterface B upsizer/downsizer valid110x0RV_CPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_C_SETns_noc_io_pcie_soc_ip.csr111107V_CInterface C upsizer/downsizer valid220x0RV_DPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_V_D_SETns_noc_io_pcie_soc_ip.csr111118V_DInterface D upsizer/downsizer valid330x0RUNSD_31_4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRUS_UNSD_31_4_SETns_noc_io_pcie_soc_ip.csr111128UNSD_31_43140x0000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_brperr0bridge_p0_spio_m_5_7_brperr0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111357p0_spio_m register brperr00x371D0R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_brperr0Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D0_SETns_noc_io_pcie_soc_ip.csr111167D0Uncorrectable Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC0_SETns_noc_io_pcie_soc_ip.csr111178DC0Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB0_SETns_noc_io_pcie_soc_ip.csr111189SB0Uncorrectable User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC0_SETns_noc_io_pcie_soc_ip.csr111201SBC0Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK0_SETns_noc_io_pcie_soc_ip.csr111212PK0Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr111223UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_D1_SETns_noc_io_pcie_soc_ip.csr111234D1Uncorrectable Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_DC1_SETns_noc_io_pcie_soc_ip.csr111245DC1Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SB1_SETns_noc_io_pcie_soc_ip.csr111256SB1Uncorrectable User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_SBC1_SETns_noc_io_pcie_soc_ip.csr111268SBC1Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_PK1_SETns_noc_io_pcie_soc_ip.csr111279PK1Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr111290UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr111301UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr111312UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr111323UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr111334UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr111345UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr111356UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_brperr1bridge_p0_spio_m_5_7_brperr1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111473p0_spio_m register brperr10x371D8R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_brperr1Receive bridge parity error status register monitoring parity errors on enabled layers from 0 to 7 (BRPERR0), and from 8 to 15 (BRPERR1). Parity/ECC error are monitored and captured for physical link to the bridge on each NoC layer. Following fields are monitored.- Data ECC/Parity: Parity/ECC is checked over multiple segments of data in each flit. An error in any segment will be recorded in the data ECC/parity error status bit. In ECC mode, single bit errors are corrected and the event is recorded.- User sideband ECC/parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.Correctable errors will raise interrupt_nfatal if fatal/nonfatal interrupt mode is configured. All other error types are considered fatal.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr111395UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr111406UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr111417UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr111428UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr111439UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr111450UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr111461UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERR1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr111472UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_brperrm0bridge_p0_spio_m_5_7_brperrm0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111694p0_spio_m register brperrm00x371E0R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_brperrm0Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseD0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D0_SETns_noc_io_pcie_soc_ip.csr111500D0Mask Data ECC/parity error in layer 0000x0R/WDC0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC0_SETns_noc_io_pcie_soc_ip.csr111512DC0Mask Correctable single bit data error (only ECC) in layer 0110x0R/WSB0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB0_SETns_noc_io_pcie_soc_ip.csr111523SB0Mask User sideband ECC/parity error in layer 0220x0R/WSBC0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC0_SETns_noc_io_pcie_soc_ip.csr111535SBC0Mask Correctable single bit user sideband error (only ECC) in layer 0330x0R/WPK0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK0_SETns_noc_io_pcie_soc_ip.csr111547PK0Mask Parity error in packet delineation controls in layer 0440x0R/WUNSD_7_5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_7_5_SETns_noc_io_pcie_soc_ip.csr111558UNSD_7_5750x0RD1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_D1_SETns_noc_io_pcie_soc_ip.csr111569D1Mask Data ECC/parity error in layer 1880x0R/WDC1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_DC1_SETns_noc_io_pcie_soc_ip.csr111581DC1Mask Correctable single bit data error (only ECC) in layer 1990x0R/WSB1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SB1_SETns_noc_io_pcie_soc_ip.csr111592SB1Mask User sideband ECC/parity error in layer 110100x0R/WSBC1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_SBC1_SETns_noc_io_pcie_soc_ip.csr111604SBC1Mask Correctable single bit user sideband error (only ECC) in layer 111110x0R/WPK1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_PK1_SETns_noc_io_pcie_soc_ip.csr111616PK1Mask Parity error in packet delineation controls in layer 112120x0R/WUNSD_15_13PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_15_13_SETns_noc_io_pcie_soc_ip.csr111627UNSD_15_1315130x0RUNSD_23_16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr111638UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr111649UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr111660UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr111671UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr111682UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM0_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr111693UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_brperrm1bridge_p0_spio_m_5_7_brperrm1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111799p0_spio_m register brperrm10x371E8R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_brperrm1Mask registers for receive bridge parity error interrupts from register BRPERR0 and BRPERR1. One mask register bit for each parity status bit in BRPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error event.This register makes use of the logical layer mapping (and not the physical layer mapping). For the physical to logical table, please refer to the Physical to Logical Layer Mapping section in the help.falsefalsefalsefalseUNSD_7_0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_7_0_SETns_noc_io_pcie_soc_ip.csr111721UNSD_7_0700x00RUNSD_15_8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_15_8_SETns_noc_io_pcie_soc_ip.csr111732UNSD_15_81580x00RUNSD_23_16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_23_16_SETns_noc_io_pcie_soc_ip.csr111743UNSD_23_1623160x00RUNSD_31_24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_31_24_SETns_noc_io_pcie_soc_ip.csr111754UNSD_31_2431240x00RUNSD_39_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_39_32_SETns_noc_io_pcie_soc_ip.csr111765UNSD_39_3239320x00RUNSD_47_40PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_47_40_SETns_noc_io_pcie_soc_ip.csr111776UNSD_47_4047400x00RUNSD_55_48PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_55_48_SETns_noc_io_pcie_soc_ip.csr111787UNSD_55_4855480x00RUNSD_63_56PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_BRPERRM1_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr111798UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_tocfgbridge_p0_spio_m_5_7_am_tocfgPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111873p0_spio_m register am_tocfg0x37C00R/W0x000000000000001fPcie_noc_bridge_p0_spio_m_5_7_am_tocfgThis register is used to configure response timeouts.AM_TOCFG[8] (En) needs to be set for timeout tracking to be enabled. When this bit is 1'b0, no timestamps are recorded to generate timeout interrupts. A 64-bit free running counter is used to time the response interval.AM_TOCFG[5:0] (TI) specifies the lower bit index into this counter, from where 2-bits are picked up and recorded as the arrival time stamp of every incoming AR and AW command. If response for a command does not return before the current time stamp rolls to arrival time stamp minus 1, the response is assumed to have timedout and an interrupt is raised along with the slave ID to which the timed out request was sent.When changing the TI field, first write to the register with the En field cleared, then write a second time with the TI field to its new value, then a 3rd write to restore the En field to Enabled. During this update while the En field is cleared, existing timers will cancelled, and new timer starts will be inhibited.falsefalsefalsefalseTIPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_TI_SETns_noc_io_pcie_soc_ip.csr111836TITimer index, index of a 64-bit counter from where timestamp is picked. The register value has to be 'd62 or smaller.500x1fR/WUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr111847UNSD_7_6760x0RENPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_EN_SETns_noc_io_pcie_soc_ip.csr111861EN1'b1: Enabled timeout tracking, a 64-bit free running counter is used to time the response interval.1'b0: No timestamps are recorded to generate timeout interrupts880x0R/WUNSD_63_9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOCFG_UNSD_63_9_SETns_noc_io_pcie_soc_ip.csr111872UNSD_63_96390x00000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_osslvbridge_p0_spio_m_5_7_am_osslvPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111908p0_spio_m register am_osslv0x37C08R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_osslvThis register is used to check if there are any outstanding read/write commands to a slave specified by field slvid. NocStudio provides a table of slvids corresponding to the slave ports accessible from a master bridge. Outstanding status is reflected in AM_STS.falsefalsefalsefalseSLVIDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_SLVID_SETns_noc_io_pcie_soc_ip.csr111896SLVIDA slave ID associated with the current master for command outstanding status1500x0000R/WUNSD_63_16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_OSSLV_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr111907UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_cgcbridge_p0_spio_m_5_7_am_cgcPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111945p0_spio_m register am_cgc0x37C10R/W0x0000000000000064Pcie_noc_bridge_p0_spio_m_5_7_am_cgcProgrammable interval used by coarse clock gating logic in master bridge.This interval is used to generate heart beat pulses using noc_clk on that bridge. These heart beat pulses are broadcast to each local clock gating domain within the bridge where they are synchronized to the CG domain's clock. Four consecutive heart beat pulses in the CG domain is used as the inactivity/idle interval to initiate coarse clock gating of the CG domain.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr111933HYSTERESIS_COUNTERHysteresis counter3100x00000064R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGC_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr111944UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_cgobridge_p0_spio_m_5_7_am_cgoPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr111980p0_spio_m register am_cgo0x37C18R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_cgoClock gating override, when set to 1'b1 will cause the clock gating logic to be disabled. 1'b1 will allow activity based clock gating to be performed on the master bridge.falsefalsefalsefalseFPOPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_FPO_SETns_noc_io_pcie_soc_ip.csr111968FPO1'b1: Clock gating override is enabled (clock gating logic is disabled).1'b0: Clock gating override is disabled (clock gating logic is enabled).000x0R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CGO_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr111979UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_cfgbridge_p0_spio_m_5_7_am_cfgPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112017p0_spio_m register am_cfg0x37C20R/W0x0000000000000001Pcie_noc_bridge_p0_spio_m_5_7_am_cfgConfigures the master bridge's support for autowake of power domains.When set, master bridge halts a request and issues wakeup requests for power domains that need to powered up to complete the transaction. The power domains should support auto wake. When reset, master bridge issues DECERR for any transaction which has dependent power domains in sleep state.falsefalsefalsefalseAWPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_AW_SETns_noc_io_pcie_soc_ip.csr112005AW1'b1: Autowake enabled1'b0: Autowake disabled000x1R/WUNSD_63_1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CFG_UNSD_63_1_SETns_noc_io_pcie_soc_ip.csr112016UNSD_63_16310x0000000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_stsbridge_p0_spio_m_5_7_am_stsPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112145p0_spio_m register am_sts0x37D00R0x000000000000000cPcie_noc_bridge_p0_spio_m_5_7_am_stsWhen reordering is disabled on the master bridge, hazard stall occurs if the master tries to access a new slave device while response from a different slave is outstanding on the same AID. This is because the responses can arrive out of order and the bridge is not equipped to correct the order. Without re-order buffers, hazard stalls also occur if a new large command needs to be split while there are older commands outstanding, or a large command just finished sending all its split segments but all responses have not returned yet.When reordering is enabled, stall due to hazard occurs if a new command arrives, whose NoC QoS is different from the NoC QoS of commands outstanding on that AID.falsefalsefalsefalseROFPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROF_SETns_noc_io_pcie_soc_ip.csr112050ROF1'b1: Maximum supported number of read commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more read requests000x0RWOFPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOF_SETns_noc_io_pcie_soc_ip.csr112064WOF1'b1: Maximum supported number of write commands are outstanding waiting for response and no more requests can be accepted1'b0: Master bridge can accept more write requests110x0RROEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ROE_SETns_noc_io_pcie_soc_ip.csr112076ROE1'b1: There are no read commands outstanding from the attached master device220x1RWOEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_WOE_SETns_noc_io_pcie_soc_ip.csr112088WOE1'b1: There are no write commands outstanding from the attached master device330x1RARSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARS_SETns_noc_io_pcie_soc_ip.csr112099ARS1'b1: AR channel is stalled on hazard440x0RAWSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWS_SETns_noc_io_pcie_soc_ip.csr112110AWS1'b1: AW channel is stalled on hazard550x0RAROPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_ARO_SETns_noc_io_pcie_soc_ip.csr112122ARO1'b1: Read commands are outstanding to the slave specified in OSSLV register660x0RAWOPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_AWO_SETns_noc_io_pcie_soc_ip.csr112134AWO1'b1: Write commands are outstanding to the slave specified in OSSLV register770x0RUNSD_63_8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_STS_UNSD_63_8_SETns_noc_io_pcie_soc_ip.csr112144UNSD_63_86380x00000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_bridge_idbridge_p0_spio_m_5_7_am_bridge_idPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112175p0_spio_m register am_bridge_id0x37D08R0x0000000000000005Pcie_noc_bridge_p0_spio_m_5_7_am_bridge_idUnique identifier assigned to the master bridge.falsefalsefalsefalseIDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_ID_SETns_noc_io_pcie_soc_ip.csr112164IDUnique bridge ID1500x0005RUNSD_63_16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_BRIDGE_ID_UNSD_63_16_SETns_noc_io_pcie_soc_ip.csr112174UNSD_63_1663160x000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_errbridge_p0_spio_m_5_7_am_errPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112671p0_spio_m register am_err0x37E00R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_errThese error status bits record the first error event and have to be cleared by writing a 1'b0 before new errors are recorded.falsefalsefalsefalseE0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E0_SETns_noc_io_pcie_soc_ip.csr112197E01'b1: Local read address decode error: ARADDR did not find a match in the master bridges address table and a decode error was issued000x0R/WE1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E1_SETns_noc_io_pcie_soc_ip.csr112209E11'b1: Read address decode error from slave: A decode error response was received from a slave device110x0R/WE2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E2_SETns_noc_io_pcie_soc_ip.csr112221E21'b1: Read slave error: A slave error response was received from a slave device220x0R/WE3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E3_SETns_noc_io_pcie_soc_ip.csr112233E31'b1: Non modifiable WRAP: A WRAP command marked as non-modifiable (ARCACHE[0]=0) was detected330x0R/WE4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E4_SETns_noc_io_pcie_soc_ip.csr112245E41'b1: [FATAL] Read exclusive split: An AR command of FIXED burst type was detected440x0R/WE5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E5_SETns_noc_io_pcie_soc_ip.csr112257E51'b1: [FATAL] Read address multi-hit: An AR command matched against multiple entries in the address table550x0R/WE6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E6_SETns_noc_io_pcie_soc_ip.csr112270E61'b1: Read response timeout: Read response timeout occurred. With timeout enabled, a response wasn't received within the expected interval660x0R/WE7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E7_SETns_noc_io_pcie_soc_ip.csr112283E71'b1: [FATAL] Read WRAP not equal to supported cacheline size: A WRAP command of unupported cache line size was detected770x0R/WE8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E8_SETns_noc_io_pcie_soc_ip.csr112294E81'b1: [FATAL] Unexpected narrow read detected880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr112305UNSD_15_91590x00RE16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E16_SETns_noc_io_pcie_soc_ip.csr112316E161'b1: Local write address decode error16160x0R/WE17PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E17_SETns_noc_io_pcie_soc_ip.csr112327E171'b1: Write address decode error from slave17170x0R/WE18PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E18_SETns_noc_io_pcie_soc_ip.csr112338E181'b1: Write slave error18180x0R/WE19PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E19_SETns_noc_io_pcie_soc_ip.csr112349E191'b1: Non modifiable WRAP19190x0R/WE20PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E20_SETns_noc_io_pcie_soc_ip.csr112360E201'b1: [FATAL] Write exclusive split20200x0R/WE21PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E21_SETns_noc_io_pcie_soc_ip.csr112371E211'b1: [FATAL] Write address multi-hit21210x0R/WE22PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E22_SETns_noc_io_pcie_soc_ip.csr112382E221'b1: Write respone timeout22220x0R/WE23PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E23_SETns_noc_io_pcie_soc_ip.csr112394E231'b1: [FATAL] Write WRAP not equal to supported cacheline size23230x0R/WE24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E24_SETns_noc_io_pcie_soc_ip.csr112405E241'b1: [FATAL] Unexpected narrow write detected24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr112416UNSD_31_2531250x00RE32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E32_SETns_noc_io_pcie_soc_ip.csr112427E321'b1: Capture counter0 overflow32320x0R/WE33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E33_SETns_noc_io_pcie_soc_ip.csr112438E331'b1: Capture counter1 overflow33330x0R/WE34PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E34_SETns_noc_io_pcie_soc_ip.csr112450E341'b1: [FATAL] Traffic sent to a noc layer which is power gate34340x0R/WE35PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E35_SETns_noc_io_pcie_soc_ip.csr112462E351'b1: [FATAL] Parity error in configuration/status registers35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr112473UNSD_39_3639360x0RE40PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E40_SETns_noc_io_pcie_soc_ip.csr112485E401'b1: [FATAL] Indicates that portcheck detected error (SIB mode only)40400x0R/WE41PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E41_SETns_noc_io_pcie_soc_ip.csr112496E411'b1: [FATAL] AR Parity Err41410x0R/WE42PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E42_SETns_noc_io_pcie_soc_ip.csr112507E421'b1: [FATAL] ARADDR Parity Err42420x0R/WE43PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E43_SETns_noc_io_pcie_soc_ip.csr112518E431'b1: [FATAL] AW Parity Err43430x0R/WE44PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E44_SETns_noc_io_pcie_soc_ip.csr112529E441'b1: [FATAL] AWADDR Parity Err44440x0R/WE45PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E45_SETns_noc_io_pcie_soc_ip.csr112540E451'b1: [FATAL] WDATA Parity Err45450x0R/WE46PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E46_SETns_noc_io_pcie_soc_ip.csr112551E461'b1: [FATAL] CDDATA Parity Err46460x0R/WE47PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E47_SETns_noc_io_pcie_soc_ip.csr112563E471'b1: [FATAL] Ridtbl Entry Parity Err47470x0RE48PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E48_SETns_noc_io_pcie_soc_ip.csr112575E481'b1: [FATAL] Widtbl Entry Parity Err48480x0RE49PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E49_SETns_noc_io_pcie_soc_ip.csr112587E491'b1: [FATAL] Read Reorder Buffer Parity Err49490x0RE50PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E50_SETns_noc_io_pcie_soc_ip.csr112599E501'b1: [FATAL] Write Reorder Buffer Parity Err50500x0RE51PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E51_SETns_noc_io_pcie_soc_ip.csr112611E511'b1: [FATAL] Rx Fifo Parity Err51510x0RE52PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E52_SETns_noc_io_pcie_soc_ip.csr112623E521'b1: [FATAL] Ack Channel Wack Fifo Parity Error52520x0RE53PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E53_SETns_noc_io_pcie_soc_ip.csr112635E531'b1: [FATAL] Ack Channel Rack Fifo Parity Error53530x0RE54PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E54_SETns_noc_io_pcie_soc_ip.csr112647E541'b1: [FATAL] CRCD Channel Crid Fifo Parity Error54540x0RE55PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_E55_SETns_noc_io_pcie_soc_ip.csr112659E551'b1: [FATAL] R Channel Cpkt Fifo Parity Error55550x0RUNSD_63_56PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERR_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr112670UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_toslvidbridge_p0_spio_m_5_7_am_toslvidPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112716p0_spio_m register am_toslvid0x37E08R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_toslvidAR slvid and AW slvid fields indicate slave IDs to which a read, write response timeout was detected. Note that slvid encoding is not same as the bridge ID of the slave. NocStudio provides a table mapping the slvids to the actual slave ports accessible from the master bridge.falsefalsefalsefalseAR_SLVIDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AR_SLVID_SETns_noc_io_pcie_soc_ip.csr112694AR_SLVIDSlave ID of timed out AR request1500x0000RAW_SLVIDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_AW_SLVID_SETns_noc_io_pcie_soc_ip.csr112705AW_SLVIDSlave ID of timed out AW request31160x0000RUNSD_63_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_TOSLVID_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr112715UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_erabridge_p0_spio_m_5_7_am_eraPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112738p0_spio_m register am_era0x37E10R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_eraThis is the address on AR channel for which a decode error was detected. This corresponds to the status register bit e0 in AM_ERR.falsefalsefalsefalseREAD_DECERR_ADDRSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_ERA_READ_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr112737READ_DECERR_ADDRSRead decerr address6300x0000000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_ewabridge_p0_spio_m_5_7_am_ewaPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr112760p0_spio_m register am_ewa0x37E18R0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_ewaThis is the address on AW channel for which a decode error was detected. This corresponds to the status register bit e16 in AM_ERR.falsefalsefalsefalseWRITE_DECERR_ADDRSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_EWA_WRITE_DECERR_ADDRS_SETns_noc_io_pcie_soc_ip.csr112759WRITE_DECERR_ADDRSWrite decerr address6300x0000000000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_intmbridge_p0_spio_m_5_7_am_intmPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113244p0_spio_m register am_intm0x37E40R/W0x00007e07004f004fPcie_noc_bridge_p0_spio_m_5_7_am_intmInterrupt mask register. Individual bit position matches the error bit positions in AM_ERR. When an INTM bit is set, occurrence of the corresponding error event will not cause an interrupt to be raised. When 1'b0, error event will cause interrupt to be raised.falsefalsefalsefalseM0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M0_SETns_noc_io_pcie_soc_ip.csr112782M01'b1: Mask interrupt for read channel000x1R/WM1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M1_SETns_noc_io_pcie_soc_ip.csr112793M11'b1: Mask interrupt for read channel110x1R/WM2PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M2_SETns_noc_io_pcie_soc_ip.csr112804M21'b1: Mask interrupt for read channel220x1R/WM3PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M3_SETns_noc_io_pcie_soc_ip.csr112815M31'b1: Mask interrupt for read channel330x1R/WM4PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M4_SETns_noc_io_pcie_soc_ip.csr112826M41'b1: Mask interrupt for read channel440x0R/WM5PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M5_SETns_noc_io_pcie_soc_ip.csr112837M51'b1: Mask interrupt for read channel550x0R/WM6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M6_SETns_noc_io_pcie_soc_ip.csr112848M61'b1: Mask interrupt for read channel660x1R/WM7PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M7_SETns_noc_io_pcie_soc_ip.csr112859M71'b1: Mask interrupt for read channel770x0R/WM8PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M8_SETns_noc_io_pcie_soc_ip.csr112870M81'b1: Mask interrupt for read channel880x0R/WUNSD_15_9PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_15_9_SETns_noc_io_pcie_soc_ip.csr112881UNSD_15_91590x00RM16PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M16_SETns_noc_io_pcie_soc_ip.csr112892M161'b1: Mask interrupt for write channel16160x1R/WM17PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M17_SETns_noc_io_pcie_soc_ip.csr112903M171'b1: Mask interrupt for write channel17170x1R/WM18PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M18_SETns_noc_io_pcie_soc_ip.csr112914M181'b1: Mask interrupt for write channel18180x1R/WM19PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M19_SETns_noc_io_pcie_soc_ip.csr112925M191'b1: Mask interrupt for write channel19190x1R/WM20PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M20_SETns_noc_io_pcie_soc_ip.csr112936M201'b1: Mask interrupt for write channel20200x0R/WM21PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M21_SETns_noc_io_pcie_soc_ip.csr112947M211'b1: Mask interrupt for write channel21210x0R/WM22PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M22_SETns_noc_io_pcie_soc_ip.csr112958M221'b1: Mask interrupt for write channel22220x1R/WM23PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M23_SETns_noc_io_pcie_soc_ip.csr112969M231'b1: Mask interrupt for write channel23230x0R/WM24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M24_SETns_noc_io_pcie_soc_ip.csr112980M241'b1: Mask interrupt for write channel24240x0R/WUNSD_31_25PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr112991UNSD_31_2531250x00RM32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M32_SETns_noc_io_pcie_soc_ip.csr113002M321'b1: Counter 0 overflow interrupt mask32320x1R/WM33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M33_SETns_noc_io_pcie_soc_ip.csr113013M331'b1: Counter 1 overflow interrupt mask33330x1R/WM34PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M34_SETns_noc_io_pcie_soc_ip.csr113024M341'b1: Mask interrupt on traffic to PG layer34340x1R/WM35PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M35_SETns_noc_io_pcie_soc_ip.csr113035M351'b1: Mask interrupt on csr parity errors35350x0R/WUNSD_39_36PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_39_36_SETns_noc_io_pcie_soc_ip.csr113046UNSD_39_3639360x0RM40PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M40_SETns_noc_io_pcie_soc_ip.csr113058M401'b1: Mask interrupt for SIB portcheck error (SIB mode only)40400x0R/WM41PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M41_SETns_noc_io_pcie_soc_ip.csr113069M411'b1: AR Parity Intr Mask41410x1R/WM42PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M42_SETns_noc_io_pcie_soc_ip.csr113080M421'b1: ARADDR Parity Intr Mask42420x1R/WM43PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M43_SETns_noc_io_pcie_soc_ip.csr113091M431'b1: AW Parity Intr Mask43430x1R/WM44PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M44_SETns_noc_io_pcie_soc_ip.csr113102M441'b1: AWADDR Parity Intr Mask44440x1R/WM45PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M45_SETns_noc_io_pcie_soc_ip.csr113113M451'b1: WDATA Parity Intr Mask45450x1R/WM46PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_M46_SETns_noc_io_pcie_soc_ip.csr113124M461'b1: CDDATA Parity Intr Mask46460x1R/WE47PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E47_SETns_noc_io_pcie_soc_ip.csr113136E471'b1: Ridtbl Parity Intr Mask47470x0RE48PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E48_SETns_noc_io_pcie_soc_ip.csr113148E481'b1: Widtbl Parity Intr Mask48480x0RE49PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E49_SETns_noc_io_pcie_soc_ip.csr113160E491'b1: Read Reorder Buffer Parity Intr Mask49490x0RE50PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E50_SETns_noc_io_pcie_soc_ip.csr113172E501'b1: Write Reorder Buffer Parity Intr Mask50500x0RE51PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E51_SETns_noc_io_pcie_soc_ip.csr113184E511'b1: Rx Fifo Parity Intr Mask51510x0RE52PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E52_SETns_noc_io_pcie_soc_ip.csr113196E521'b1: Ack Channel Wack Fifo Parity Intr Mask52520x0RE53PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E53_SETns_noc_io_pcie_soc_ip.csr113208E531'b1: Ack Channel Rack Fifo Parity Intr Mask53530x0RE54PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E54_SETns_noc_io_pcie_soc_ip.csr113220E541'b1: CRCD Channel Crid Fifo Parity Intr Mask54540x0RE55PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_E55_SETns_noc_io_pcie_soc_ip.csr113232E551'b1: R Channel Cpkt Fifo Parity Intr Mask55550x0RUNSD_63_56PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_INTM_UNSD_63_56_SETns_noc_io_pcie_soc_ip.csr113243UNSD_63_5663560x00Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_caddrbridge_p0_spio_m_5_7_am_caddrPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113266p0_spio_m register am_caddr0x37F00R/W0xffffffffffffffffPcie_noc_bridge_p0_spio_m_5_7_am_caddrThis register is part of statistics gathering on the AR and AW command channels. This is the address value which is checked against AR, AW command channels in conjunction with the mask below to filter commands for statistics gathering.falsefalsefalsefalseCAPTURE_ADDRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDR_CAPTURE_ADDR_SETns_noc_io_pcie_soc_ip.csr113265CAPTURE_ADDRCapture address6300xffffffffffffffffR/Wregisterpcie_noc.bridge_p0_spio_m_5_7_am_caddrmskbridge_p0_spio_m_5_7_am_caddrmskPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113289p0_spio_m register am_caddrmsk0x37F08R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_caddrmskIf command address on the AR, AW channel logically ANDed with this mask is equal to the value specified in AM_CADDR, then an address match has occurred. Note that only lowest significant bits equal to the master's address width are used in the comparison.falsefalsefalsefalseCAPTURE_ADDR_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CADDRMSK_CAPTURE_ADDR_MASK_SETns_noc_io_pcie_soc_ip.csr113288CAPTURE_ADDR_MASKCapture address mask6300x0000000000000000R/Wregisterpcie_noc.bridge_p0_spio_m_5_7_am_ccmd0bridge_p0_spio_m_5_7_am_ccmd0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113479p0_spio_m register am_ccmd00x37F10R/W0x0000000003fff33fPcie_noc_bridge_p0_spio_m_5_7_am_ccmd0Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_SNOOP_SETns_noc_io_pcie_soc_ip.csr113311SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr113322DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr113333UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_BAR_SETns_noc_io_pcie_soc_ip.csr113344BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr113355UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_CACHE_SETns_noc_io_pcie_soc_ip.csr113366CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_QOS_SETns_noc_io_pcie_soc_ip.csr113377QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_PROT_SETns_noc_io_pcie_soc_ip.csr113388PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_LOC_SETns_noc_io_pcie_soc_ip.csr113399LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_RDY_SETns_noc_io_pcie_soc_ip.csr113410RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_VAL_SETns_noc_io_pcie_soc_ip.csr113421VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr113432UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_INTFID_SETns_noc_io_pcie_soc_ip.csr113444INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr113455UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_TYP_SETns_noc_io_pcie_soc_ip.csr113467TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD0_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr113478UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk0bridge_p0_spio_m_5_7_am_ccmdmsk0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113623p0_spio_m register am_ccmdmsk00x37F18R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_ccmdmsk0If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_SNOOP_SETns_noc_io_pcie_soc_ip.csr113501SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_DOMAIN_SETns_noc_io_pcie_soc_ip.csr113512DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr113523UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_BAR_SETns_noc_io_pcie_soc_ip.csr113534BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr113545UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_CACHE_SETns_noc_io_pcie_soc_ip.csr113556CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_QOS_SETns_noc_io_pcie_soc_ip.csr113567QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_PROT_SETns_noc_io_pcie_soc_ip.csr113578PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_LOC_SETns_noc_io_pcie_soc_ip.csr113589LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_RDY_SETns_noc_io_pcie_soc_ip.csr113600RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_VAL_SETns_noc_io_pcie_soc_ip.csr113611VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK0_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr113622UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_cntr0bridge_p0_spio_m_5_7_am_cntr0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113658p0_spio_m register am_cntr00x37F20R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_cntr032-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_CNTR_SETns_noc_io_pcie_soc_ip.csr113646CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr113657UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_latnum0bridge_p0_spio_m_5_7_am_latnum0PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113697p0_spio_m register am_latnum00x37F28R/W0x0000000000000007Pcie_noc_bridge_p0_spio_m_5_7_am_latnum0This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_CNTR_SETns_noc_io_pcie_soc_ip.csr113685CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM0_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr113696UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_ccmd1bridge_p0_spio_m_5_7_am_ccmd1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr113887p0_spio_m register am_ccmd10x37F30R/W0x0000000003fff33fPcie_noc_bridge_p0_spio_m_5_7_am_ccmd1Values of command fields/pins that are compared against AR, AW, R, W channel interface signals to filter commands/events for statistics gathering. Two selections can be made for statistics gathering, counting filtered commands or measuring latency of filtered commands.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_SNOOP_SETns_noc_io_pcie_soc_ip.csr113719SNOOPSnoop300xfR/WDOMAINPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr113730DOMAINDomain540x3R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr113741UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_BAR_SETns_noc_io_pcie_soc_ip.csr113752BARBar980x3R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr113763UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_CACHE_SETns_noc_io_pcie_soc_ip.csr113774CACHECache15120xfR/WQOSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_QOS_SETns_noc_io_pcie_soc_ip.csr113785QOSQoS19160xfR/WPROTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_PROT_SETns_noc_io_pcie_soc_ip.csr113796PROTProt22200x7R/WLOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_LOC_SETns_noc_io_pcie_soc_ip.csr113807LOC1'b1: Lock23230x1R/WRDYPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_RDY_SETns_noc_io_pcie_soc_ip.csr113818RDY1'b1: Ready24240x1R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_VAL_SETns_noc_io_pcie_soc_ip.csr113829VAL1'b1: Valid25250x1R/WUNSD_27_26PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_27_26_SETns_noc_io_pcie_soc_ip.csr113840UNSD_27_2627260x0RINTFIDPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_INTFID_SETns_noc_io_pcie_soc_ip.csr113852INTFID001: AW (can count captured event or response latency)000: AR (can count captured event or response latency)30280x0R/WUNSD_31_31PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_31_31_SETns_noc_io_pcie_soc_ip.csr113863UNSD_31_3131310x0RTYPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_TYP_SETns_noc_io_pcie_soc_ip.csr113875TYP1'b1: Count response latency of captured command1'b0: Count captured command32320x0R/WUNSD_63_33PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMD1_UNSD_63_33_SETns_noc_io_pcie_soc_ip.csr113886UNSD_63_3363330x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_ccmdmsk1bridge_p0_spio_m_5_7_am_ccmdmsk1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114031p0_spio_m register am_ccmdmsk10x37F38R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_ccmdmsk1If Command fields on AR, AW channel logically ANDed with this mask are equal to the corresponding command field values in AM_CCMD0 then a command match has occurred. Address and command value match occurring together constitute events for the statistics counters.falsefalsefalsefalseSNOOPPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_SNOOP_SETns_noc_io_pcie_soc_ip.csr113909SNOOPSnoop300x0R/WDOMAINPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_DOMAIN_SETns_noc_io_pcie_soc_ip.csr113920DOMAINDomain540x0R/WUNSD_7_6PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_7_6_SETns_noc_io_pcie_soc_ip.csr113931UNSD_7_6760x0RBARPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_BAR_SETns_noc_io_pcie_soc_ip.csr113942BARBar980x0R/WUNSD_11_10PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_11_10_SETns_noc_io_pcie_soc_ip.csr113953UNSD_11_1011100x0RCACHEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_CACHE_SETns_noc_io_pcie_soc_ip.csr113964CACHECache15120x0R/WQOSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_QOS_SETns_noc_io_pcie_soc_ip.csr113975QOSQoS19160x0R/WPROTPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_PROT_SETns_noc_io_pcie_soc_ip.csr113986PROTProt22200x0R/WLOCPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_LOC_SETns_noc_io_pcie_soc_ip.csr113997LOC1'b1: Lock23230x0R/WRDYPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_RDY_SETns_noc_io_pcie_soc_ip.csr114008RDY1'b1: Ready24240x0R/WVALPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_VAL_SETns_noc_io_pcie_soc_ip.csr114019VAL1'b1: Valid25250x0R/WUNSD_63_26PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CCMDMSK1_UNSD_63_26_SETns_noc_io_pcie_soc_ip.csr114030UNSD_63_2663260x0000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_cntr1bridge_p0_spio_m_5_7_am_cntr1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114066p0_spio_m register am_cntr10x37F40R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_cntr132-bit counter which is used to count the captured statistics events. This counter can hold the count of commands filtered on the AR, AW channels. When measuring command latency, this counter holds the denominator or sum of number of cycles between command and response for multiple commands over which latency is measured.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_CNTR_SETns_noc_io_pcie_soc_ip.csr114054CNTRCounter3100x00000000R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_CNTR1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr114065UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_latnum1bridge_p0_spio_m_5_7_am_latnum1PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114105p0_spio_m register am_latnum10x37F48R/W0x0000000000000007Pcie_noc_bridge_p0_spio_m_5_7_am_latnum1This register is programmed with the number of commands over which latency is to be measured. When this register counts down to 0, latency measurement is complete and average latency can be computed using:Average command latency = Value in AM_CNTR0/Value which was programmed in AM_LATNUM0There are two sets of counters available for gathering statistics. AM_CCMD1, AM_CCMDMSK1, AM_CNTR1, AM_LATNUM1 constitute the second bank of counters and are similar to the above set.falsefalsefalsefalseCNTRPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_CNTR_SETns_noc_io_pcie_soc_ip.csr114093CNTRCounter3100x00000007R/WUNSD_63_32PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_LATNUM1_UNSD_63_32_SETns_noc_io_pcie_soc_ip.csr114104UNSD_63_3263320x00000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_arovrdbridge_p0_spio_m_5_7_am_arovrdPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114218p0_spio_m register am_arovrd0x37F60R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_arovrdAR override.falsefalsefalsefalsearcache_valPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr114123arcache_valValue to override incoming ARCACHE300x0R/Warcache_enbPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr114136arcache_enb1'b1 indicates bit positions where ARCACHE value is overridden. 1'b0 indicates bit positions where ARCACHE is unchanged.740x0R/Warprot_valPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_VAL_SETns_noc_io_pcie_soc_ip.csr114147arprot_valValue to override incoming ARPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr114158UNSD_11_1111110x0Rarprot_enbPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARPROT_ENB_SETns_noc_io_pcie_soc_ip.csr114171arprot_enb1'b1 indicates bit positions where ARPROT value is overridden. 1'b0 indicates bit positions where ARPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr114182UNSD_15_1515150x0Rarqos_valPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_VAL_SETns_noc_io_pcie_soc_ip.csr114193arqos_valValue to override incoming ARQOS19160x0R/Warqos_enbPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_ARQOS_ENB_SETns_noc_io_pcie_soc_ip.csr114206arqos_enb1'b1 indicates bit positions where ARQOS value is overridden. 1'b0 indicates bit positions where ARQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AROVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr114217UNSD_63_2463240x0000000000Rregisterpcie_noc.bridge_p0_spio_m_5_7_am_awovrdbridge_p0_spio_m_5_7_am_awovrdPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_BYTE_ADDRESSPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_OFFSETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114331p0_spio_m register am_awovrd0x37F68R/W0x0000000000000000Pcie_noc_bridge_p0_spio_m_5_7_am_awovrdAW override.falsefalsefalsefalseawcache_valPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_VAL_SETns_noc_io_pcie_soc_ip.csr114236awcache_valValue to override incoming AWCACHE300x0R/Wawcache_enbPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWCACHE_ENB_SETns_noc_io_pcie_soc_ip.csr114249awcache_enb1'b1 indicates bit positions where AWCACHE value is overridden. 1'b0 indicates bit positions where AWCACHE is unchanged.740x0R/Wawprot_valPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_VAL_SETns_noc_io_pcie_soc_ip.csr114260awprot_valValue to override incoming AWPROT1080x0R/WUNSD_11_11PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_11_11_SETns_noc_io_pcie_soc_ip.csr114271UNSD_11_1111110x0Rawprot_enbPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWPROT_ENB_SETns_noc_io_pcie_soc_ip.csr114284awprot_enb1'b1 indicates bit positions where AWPROT value is overridden. 1'b0 indicates bit positions where AWPROT is unchanged.14120x0R/WUNSD_15_15PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_15_15_SETns_noc_io_pcie_soc_ip.csr114295UNSD_15_1515150x0Rawqos_valPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_VAL_SETns_noc_io_pcie_soc_ip.csr114306awqos_valValue to override incoming AWQOS19160x0R/Wawqos_enbPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_AWQOS_ENB_SETns_noc_io_pcie_soc_ip.csr114319awqos_enb1'b1 indicates bit positions where AWQOS value is overridden. 1'b0 indicates bit positions where AWQOS is unchanged.23200x0R/WUNSD_63_24PCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_WIDTHPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_MSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_LSBPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_RANGEPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_RESETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_FIELD_MASKPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_GETPCIE_NOC_BRIDGE_P0_SPIO_M_5_7_AM_AWOVRD_UNSD_63_24_SETns_noc_io_pcie_soc_ip.csr114330UNSD_63_2463240x0000000000Rregisterpcie_noc.router_0_5_5_rivcs_hrouter_0_5_5_rivcs_hPCIE_NOC_ROUTER_0_5_5_RIVCS_H_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114660R0_5 register rivcs_h0x38000R0x00000000Pcie_noc_router_0_5_5_rivcs_hThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_0_SETns_noc_io_pcie_soc_ip.csr114356OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_0_SETns_noc_io_pcie_soc_ip.csr114370UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_0_SETns_noc_io_pcie_soc_ip.csr114386S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_0_SETns_noc_io_pcie_soc_ip.csr114400B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_0_SETns_noc_io_pcie_soc_ip.csr114411F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_0_SETns_noc_io_pcie_soc_ip.csr114422V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_1_SETns_noc_io_pcie_soc_ip.csr114435OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_1_SETns_noc_io_pcie_soc_ip.csr114449UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_1_SETns_noc_io_pcie_soc_ip.csr114465S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_1_SETns_noc_io_pcie_soc_ip.csr114479B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_1_SETns_noc_io_pcie_soc_ip.csr114490F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_1_SETns_noc_io_pcie_soc_ip.csr114501V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_2_SETns_noc_io_pcie_soc_ip.csr114514OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_2_SETns_noc_io_pcie_soc_ip.csr114528UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_2_SETns_noc_io_pcie_soc_ip.csr114544S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_2_SETns_noc_io_pcie_soc_ip.csr114558B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_2_SETns_noc_io_pcie_soc_ip.csr114569F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_2_SETns_noc_io_pcie_soc_ip.csr114580V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_OUTP_3_SETns_noc_io_pcie_soc_ip.csr114593OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_UP_3_SETns_noc_io_pcie_soc_ip.csr114607UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_S_3_SETns_noc_io_pcie_soc_ip.csr114623S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_B_3_SETns_noc_io_pcie_soc_ip.csr114637B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_F_3_SETns_noc_io_pcie_soc_ip.csr114648F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_H_V_3_SETns_noc_io_pcie_soc_ip.csr114659V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rivcs_erouter_0_5_5_rivcs_ePCIE_NOC_ROUTER_0_5_5_RIVCS_E_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr114989R0_5 register rivcs_e0x38008R0x00000000Pcie_noc_router_0_5_5_rivcs_eThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_0_SETns_noc_io_pcie_soc_ip.csr114685OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_0_SETns_noc_io_pcie_soc_ip.csr114699UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_0_SETns_noc_io_pcie_soc_ip.csr114715S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_0_SETns_noc_io_pcie_soc_ip.csr114729B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_0_SETns_noc_io_pcie_soc_ip.csr114740F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_0_SETns_noc_io_pcie_soc_ip.csr114751V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_1_SETns_noc_io_pcie_soc_ip.csr114764OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_1_SETns_noc_io_pcie_soc_ip.csr114778UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_1_SETns_noc_io_pcie_soc_ip.csr114794S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_1_SETns_noc_io_pcie_soc_ip.csr114808B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_1_SETns_noc_io_pcie_soc_ip.csr114819F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_1_SETns_noc_io_pcie_soc_ip.csr114830V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_2_SETns_noc_io_pcie_soc_ip.csr114843OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_2_SETns_noc_io_pcie_soc_ip.csr114857UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_2_SETns_noc_io_pcie_soc_ip.csr114873S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_2_SETns_noc_io_pcie_soc_ip.csr114887B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_2_SETns_noc_io_pcie_soc_ip.csr114898F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_2_SETns_noc_io_pcie_soc_ip.csr114909V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_OUTP_3_SETns_noc_io_pcie_soc_ip.csr114922OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_UP_3_SETns_noc_io_pcie_soc_ip.csr114936UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_S_3_SETns_noc_io_pcie_soc_ip.csr114952S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_B_3_SETns_noc_io_pcie_soc_ip.csr114966B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_F_3_SETns_noc_io_pcie_soc_ip.csr114977F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_E_V_3_SETns_noc_io_pcie_soc_ip.csr114988V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rivcs_srouter_0_5_5_rivcs_sPCIE_NOC_ROUTER_0_5_5_RIVCS_S_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr115318R0_5 register rivcs_s0x38010R0x00000000Pcie_noc_router_0_5_5_rivcs_sThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_0_SETns_noc_io_pcie_soc_ip.csr115014OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_0_SETns_noc_io_pcie_soc_ip.csr115028UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_0_SETns_noc_io_pcie_soc_ip.csr115044S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_0_SETns_noc_io_pcie_soc_ip.csr115058B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_0_SETns_noc_io_pcie_soc_ip.csr115069F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_0_SETns_noc_io_pcie_soc_ip.csr115080V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_1_SETns_noc_io_pcie_soc_ip.csr115093OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_1_SETns_noc_io_pcie_soc_ip.csr115107UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_1_SETns_noc_io_pcie_soc_ip.csr115123S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_1_SETns_noc_io_pcie_soc_ip.csr115137B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_1_SETns_noc_io_pcie_soc_ip.csr115148F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_1_SETns_noc_io_pcie_soc_ip.csr115159V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_2_SETns_noc_io_pcie_soc_ip.csr115172OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_2_SETns_noc_io_pcie_soc_ip.csr115186UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_2_SETns_noc_io_pcie_soc_ip.csr115202S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_2_SETns_noc_io_pcie_soc_ip.csr115216B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_2_SETns_noc_io_pcie_soc_ip.csr115227F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_2_SETns_noc_io_pcie_soc_ip.csr115238V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_OUTP_3_SETns_noc_io_pcie_soc_ip.csr115251OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_UP_3_SETns_noc_io_pcie_soc_ip.csr115265UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_S_3_SETns_noc_io_pcie_soc_ip.csr115281S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_B_3_SETns_noc_io_pcie_soc_ip.csr115295B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_F_3_SETns_noc_io_pcie_soc_ip.csr115306F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_S_V_3_SETns_noc_io_pcie_soc_ip.csr115317V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rivcs_wrouter_0_5_5_rivcs_wPCIE_NOC_ROUTER_0_5_5_RIVCS_W_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr115647R0_5 register rivcs_w0x38018R0x00000000Pcie_noc_router_0_5_5_rivcs_wThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_0_SETns_noc_io_pcie_soc_ip.csr115343OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_0_SETns_noc_io_pcie_soc_ip.csr115357UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_0_SETns_noc_io_pcie_soc_ip.csr115373S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_0_SETns_noc_io_pcie_soc_ip.csr115387B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_0_SETns_noc_io_pcie_soc_ip.csr115398F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_0_SETns_noc_io_pcie_soc_ip.csr115409V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_1_SETns_noc_io_pcie_soc_ip.csr115422OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_1_SETns_noc_io_pcie_soc_ip.csr115436UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_1_SETns_noc_io_pcie_soc_ip.csr115452S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_1_SETns_noc_io_pcie_soc_ip.csr115466B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_1_SETns_noc_io_pcie_soc_ip.csr115477F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_1_SETns_noc_io_pcie_soc_ip.csr115488V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_2_SETns_noc_io_pcie_soc_ip.csr115501OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_2_SETns_noc_io_pcie_soc_ip.csr115515UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_2_SETns_noc_io_pcie_soc_ip.csr115531S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_2_SETns_noc_io_pcie_soc_ip.csr115545B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_2_SETns_noc_io_pcie_soc_ip.csr115556F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_2_SETns_noc_io_pcie_soc_ip.csr115567V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_OUTP_3_SETns_noc_io_pcie_soc_ip.csr115580OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_UP_3_SETns_noc_io_pcie_soc_ip.csr115594UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_S_3_SETns_noc_io_pcie_soc_ip.csr115610S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_B_3_SETns_noc_io_pcie_soc_ip.csr115624B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_F_3_SETns_noc_io_pcie_soc_ip.csr115635F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_W_V_3_SETns_noc_io_pcie_soc_ip.csr115646V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rivcs_irouter_0_5_5_rivcs_iPCIE_NOC_ROUTER_0_5_5_RIVCS_I_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr115976R0_5 register rivcs_i0x38028R0x00000000Pcie_noc_router_0_5_5_rivcs_iThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_0_SETns_noc_io_pcie_soc_ip.csr115672OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_0_SETns_noc_io_pcie_soc_ip.csr115686UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_0_SETns_noc_io_pcie_soc_ip.csr115702S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_0_SETns_noc_io_pcie_soc_ip.csr115716B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_0_SETns_noc_io_pcie_soc_ip.csr115727F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_0_SETns_noc_io_pcie_soc_ip.csr115738V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_1_SETns_noc_io_pcie_soc_ip.csr115751OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_1_SETns_noc_io_pcie_soc_ip.csr115765UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_1_SETns_noc_io_pcie_soc_ip.csr115781S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_1_SETns_noc_io_pcie_soc_ip.csr115795B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_1_SETns_noc_io_pcie_soc_ip.csr115806F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_1_SETns_noc_io_pcie_soc_ip.csr115817V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_2_SETns_noc_io_pcie_soc_ip.csr115830OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_2_SETns_noc_io_pcie_soc_ip.csr115844UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_2_SETns_noc_io_pcie_soc_ip.csr115860S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_2_SETns_noc_io_pcie_soc_ip.csr115874B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_2_SETns_noc_io_pcie_soc_ip.csr115885F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_2_SETns_noc_io_pcie_soc_ip.csr115896V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_OUTP_3_SETns_noc_io_pcie_soc_ip.csr115909OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_UP_3_SETns_noc_io_pcie_soc_ip.csr115923UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_S_3_SETns_noc_io_pcie_soc_ip.csr115939S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_B_3_SETns_noc_io_pcie_soc_ip.csr115953B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_F_3_SETns_noc_io_pcie_soc_ip.csr115964F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_I_V_3_SETns_noc_io_pcie_soc_ip.csr115975V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rivcs_jrouter_0_5_5_rivcs_jPCIE_NOC_ROUTER_0_5_5_RIVCS_J_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr116305R0_5 register rivcs_j0x38030R0x00000000Pcie_noc_router_0_5_5_rivcs_jThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_0_SETns_noc_io_pcie_soc_ip.csr116001OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_0_SETns_noc_io_pcie_soc_ip.csr116015UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_0_SETns_noc_io_pcie_soc_ip.csr116031S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_0_SETns_noc_io_pcie_soc_ip.csr116045B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_0_SETns_noc_io_pcie_soc_ip.csr116056F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_0_SETns_noc_io_pcie_soc_ip.csr116067V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_1_SETns_noc_io_pcie_soc_ip.csr116080OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_1_SETns_noc_io_pcie_soc_ip.csr116094UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_1_SETns_noc_io_pcie_soc_ip.csr116110S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_1_SETns_noc_io_pcie_soc_ip.csr116124B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_1_SETns_noc_io_pcie_soc_ip.csr116135F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_1_SETns_noc_io_pcie_soc_ip.csr116146V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_2_SETns_noc_io_pcie_soc_ip.csr116159OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_2_SETns_noc_io_pcie_soc_ip.csr116173UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_2_SETns_noc_io_pcie_soc_ip.csr116189S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_2_SETns_noc_io_pcie_soc_ip.csr116203B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_2_SETns_noc_io_pcie_soc_ip.csr116214F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_2_SETns_noc_io_pcie_soc_ip.csr116225V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_OUTP_3_SETns_noc_io_pcie_soc_ip.csr116238OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_UP_3_SETns_noc_io_pcie_soc_ip.csr116252UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_S_3_SETns_noc_io_pcie_soc_ip.csr116268S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_B_3_SETns_noc_io_pcie_soc_ip.csr116282B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_F_3_SETns_noc_io_pcie_soc_ip.csr116293F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_J_V_3_SETns_noc_io_pcie_soc_ip.csr116304V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rivcs_krouter_0_5_5_rivcs_kPCIE_NOC_ROUTER_0_5_5_RIVCS_K_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OFFSETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr116634R0_5 register rivcs_k0x38038R0x00000000Pcie_noc_router_0_5_5_rivcs_kThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_0_SETns_noc_io_pcie_soc_ip.csr116330OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_0_SETns_noc_io_pcie_soc_ip.csr116344UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_0_SETns_noc_io_pcie_soc_ip.csr116360S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_0_SETns_noc_io_pcie_soc_ip.csr116374B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_0_SETns_noc_io_pcie_soc_ip.csr116385F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_0_SETns_noc_io_pcie_soc_ip.csr116396V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_1_SETns_noc_io_pcie_soc_ip.csr116409OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_1_SETns_noc_io_pcie_soc_ip.csr116423UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_1_SETns_noc_io_pcie_soc_ip.csr116439S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_1_SETns_noc_io_pcie_soc_ip.csr116453B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_1_SETns_noc_io_pcie_soc_ip.csr116464F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_1_SETns_noc_io_pcie_soc_ip.csr116475V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_2_SETns_noc_io_pcie_soc_ip.csr116488OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_2_SETns_noc_io_pcie_soc_ip.csr116502UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_2_SETns_noc_io_pcie_soc_ip.csr116518S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_2_SETns_noc_io_pcie_soc_ip.csr116532B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_2_SETns_noc_io_pcie_soc_ip.csr116543F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_2_SETns_noc_io_pcie_soc_ip.csr116554V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_OUTP_3_SETns_noc_io_pcie_soc_ip.csr116567OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_UP_3_SETns_noc_io_pcie_soc_ip.csr116581UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_S_3_SETns_noc_io_pcie_soc_ip.csr116597S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_B_3_SETns_noc_io_pcie_soc_ip.csr116611B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_F_3_SETns_noc_io_pcie_soc_ip.csr116622F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_MSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_LSBPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_RANGEPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_RESETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_GETPCIE_NOC_ROUTER_0_5_5_RIVCS_K_V_3_SETns_noc_io_pcie_soc_ip.csr116633V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_5_5_rovcs_hrouter_0_5_5_rovcs_hPCIE_NOC_ROUTER_0_5_5_ROVCS_H_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_H_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr116895R0_5 register rovcs_h0x38040R0x00000101Pcie_noc_router_0_5_5_rovcs_hThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_0_SETns_noc_io_pcie_soc_ip.csr116658CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_0_SETns_noc_io_pcie_soc_ip.csr116672CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_0_SETns_noc_io_pcie_soc_ip.csr116687VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_0_SETns_noc_io_pcie_soc_ip.csr116698RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_0_SETns_noc_io_pcie_soc_ip.csr116708UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_1_SETns_noc_io_pcie_soc_ip.csr116720CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_1_SETns_noc_io_pcie_soc_ip.csr116734CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_1_SETns_noc_io_pcie_soc_ip.csr116749VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_1_SETns_noc_io_pcie_soc_ip.csr116760RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_1_SETns_noc_io_pcie_soc_ip.csr116770UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_2_SETns_noc_io_pcie_soc_ip.csr116782CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_2_SETns_noc_io_pcie_soc_ip.csr116796CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_2_SETns_noc_io_pcie_soc_ip.csr116811VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_2_SETns_noc_io_pcie_soc_ip.csr116822RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_2_SETns_noc_io_pcie_soc_ip.csr116832UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CF_3_SETns_noc_io_pcie_soc_ip.csr116844CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_CE_3_SETns_noc_io_pcie_soc_ip.csr116858CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_VB_3_SETns_noc_io_pcie_soc_ip.csr116873VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_RSV_3_SETns_noc_io_pcie_soc_ip.csr116884RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_H_UNSD_3_SETns_noc_io_pcie_soc_ip.csr116894UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rovcs_erouter_0_5_5_rovcs_ePCIE_NOC_ROUTER_0_5_5_ROVCS_E_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_E_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr117156R0_5 register rovcs_e0x38048R0x00000001Pcie_noc_router_0_5_5_rovcs_eThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_0_SETns_noc_io_pcie_soc_ip.csr116919CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_0_SETns_noc_io_pcie_soc_ip.csr116933CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_0_SETns_noc_io_pcie_soc_ip.csr116948VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_0_SETns_noc_io_pcie_soc_ip.csr116959RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_0_SETns_noc_io_pcie_soc_ip.csr116969UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_1_SETns_noc_io_pcie_soc_ip.csr116981CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_1_SETns_noc_io_pcie_soc_ip.csr116995CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_1_SETns_noc_io_pcie_soc_ip.csr117010VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_1_SETns_noc_io_pcie_soc_ip.csr117021RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_1_SETns_noc_io_pcie_soc_ip.csr117031UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_2_SETns_noc_io_pcie_soc_ip.csr117043CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_2_SETns_noc_io_pcie_soc_ip.csr117057CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_2_SETns_noc_io_pcie_soc_ip.csr117072VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_2_SETns_noc_io_pcie_soc_ip.csr117083RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_2_SETns_noc_io_pcie_soc_ip.csr117093UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CF_3_SETns_noc_io_pcie_soc_ip.csr117105CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_CE_3_SETns_noc_io_pcie_soc_ip.csr117119CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_VB_3_SETns_noc_io_pcie_soc_ip.csr117134VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_RSV_3_SETns_noc_io_pcie_soc_ip.csr117145RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_E_UNSD_3_SETns_noc_io_pcie_soc_ip.csr117155UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rovcs_srouter_0_5_5_rovcs_sPCIE_NOC_ROUTER_0_5_5_ROVCS_S_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_S_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr117417R0_5 register rovcs_s0x38050R0x00000001Pcie_noc_router_0_5_5_rovcs_sThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_0_SETns_noc_io_pcie_soc_ip.csr117180CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_0_SETns_noc_io_pcie_soc_ip.csr117194CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_0_SETns_noc_io_pcie_soc_ip.csr117209VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_0_SETns_noc_io_pcie_soc_ip.csr117220RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_0_SETns_noc_io_pcie_soc_ip.csr117230UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_1_SETns_noc_io_pcie_soc_ip.csr117242CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_1_SETns_noc_io_pcie_soc_ip.csr117256CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_1_SETns_noc_io_pcie_soc_ip.csr117271VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_1_SETns_noc_io_pcie_soc_ip.csr117282RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_1_SETns_noc_io_pcie_soc_ip.csr117292UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_2_SETns_noc_io_pcie_soc_ip.csr117304CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_2_SETns_noc_io_pcie_soc_ip.csr117318CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_2_SETns_noc_io_pcie_soc_ip.csr117333VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_2_SETns_noc_io_pcie_soc_ip.csr117344RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_2_SETns_noc_io_pcie_soc_ip.csr117354UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CF_3_SETns_noc_io_pcie_soc_ip.csr117366CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_CE_3_SETns_noc_io_pcie_soc_ip.csr117380CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_VB_3_SETns_noc_io_pcie_soc_ip.csr117395VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_RSV_3_SETns_noc_io_pcie_soc_ip.csr117406RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_S_UNSD_3_SETns_noc_io_pcie_soc_ip.csr117416UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rovcs_wrouter_0_5_5_rovcs_wPCIE_NOC_ROUTER_0_5_5_ROVCS_W_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_W_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr117678R0_5 register rovcs_w0x38058R0x00000101Pcie_noc_router_0_5_5_rovcs_wThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_0_SETns_noc_io_pcie_soc_ip.csr117441CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_0_SETns_noc_io_pcie_soc_ip.csr117455CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_0_SETns_noc_io_pcie_soc_ip.csr117470VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_0_SETns_noc_io_pcie_soc_ip.csr117481RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_0_SETns_noc_io_pcie_soc_ip.csr117491UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_1_SETns_noc_io_pcie_soc_ip.csr117503CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_1_SETns_noc_io_pcie_soc_ip.csr117517CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_1_SETns_noc_io_pcie_soc_ip.csr117532VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_1_SETns_noc_io_pcie_soc_ip.csr117543RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_1_SETns_noc_io_pcie_soc_ip.csr117553UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_2_SETns_noc_io_pcie_soc_ip.csr117565CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_2_SETns_noc_io_pcie_soc_ip.csr117579CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_2_SETns_noc_io_pcie_soc_ip.csr117594VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_2_SETns_noc_io_pcie_soc_ip.csr117605RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_2_SETns_noc_io_pcie_soc_ip.csr117615UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CF_3_SETns_noc_io_pcie_soc_ip.csr117627CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_CE_3_SETns_noc_io_pcie_soc_ip.csr117641CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_VB_3_SETns_noc_io_pcie_soc_ip.csr117656VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_RSV_3_SETns_noc_io_pcie_soc_ip.csr117667RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_W_UNSD_3_SETns_noc_io_pcie_soc_ip.csr117677UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rovcs_irouter_0_5_5_rovcs_iPCIE_NOC_ROUTER_0_5_5_ROVCS_I_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_I_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr117939R0_5 register rovcs_i0x38068R0x00000001Pcie_noc_router_0_5_5_rovcs_iThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_0_SETns_noc_io_pcie_soc_ip.csr117702CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_0_SETns_noc_io_pcie_soc_ip.csr117716CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_0_SETns_noc_io_pcie_soc_ip.csr117731VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_0_SETns_noc_io_pcie_soc_ip.csr117742RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_0_SETns_noc_io_pcie_soc_ip.csr117752UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_1_SETns_noc_io_pcie_soc_ip.csr117764CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_1_SETns_noc_io_pcie_soc_ip.csr117778CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_1_SETns_noc_io_pcie_soc_ip.csr117793VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_1_SETns_noc_io_pcie_soc_ip.csr117804RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_1_SETns_noc_io_pcie_soc_ip.csr117814UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_2_SETns_noc_io_pcie_soc_ip.csr117826CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_2_SETns_noc_io_pcie_soc_ip.csr117840CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_2_SETns_noc_io_pcie_soc_ip.csr117855VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_2_SETns_noc_io_pcie_soc_ip.csr117866RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_2_SETns_noc_io_pcie_soc_ip.csr117876UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CF_3_SETns_noc_io_pcie_soc_ip.csr117888CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_CE_3_SETns_noc_io_pcie_soc_ip.csr117902CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_VB_3_SETns_noc_io_pcie_soc_ip.csr117917VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_RSV_3_SETns_noc_io_pcie_soc_ip.csr117928RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_I_UNSD_3_SETns_noc_io_pcie_soc_ip.csr117938UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rovcs_jrouter_0_5_5_rovcs_jPCIE_NOC_ROUTER_0_5_5_ROVCS_J_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_J_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118200R0_5 register rovcs_j0x38070R0x00000001Pcie_noc_router_0_5_5_rovcs_jThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_0_SETns_noc_io_pcie_soc_ip.csr117963CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_0_SETns_noc_io_pcie_soc_ip.csr117977CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_0_SETns_noc_io_pcie_soc_ip.csr117992VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_0_SETns_noc_io_pcie_soc_ip.csr118003RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_0_SETns_noc_io_pcie_soc_ip.csr118013UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_1_SETns_noc_io_pcie_soc_ip.csr118025CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_1_SETns_noc_io_pcie_soc_ip.csr118039CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_1_SETns_noc_io_pcie_soc_ip.csr118054VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_1_SETns_noc_io_pcie_soc_ip.csr118065RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_1_SETns_noc_io_pcie_soc_ip.csr118075UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_2_SETns_noc_io_pcie_soc_ip.csr118087CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_2_SETns_noc_io_pcie_soc_ip.csr118101CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_2_SETns_noc_io_pcie_soc_ip.csr118116VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_2_SETns_noc_io_pcie_soc_ip.csr118127RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_2_SETns_noc_io_pcie_soc_ip.csr118137UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CF_3_SETns_noc_io_pcie_soc_ip.csr118149CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_CE_3_SETns_noc_io_pcie_soc_ip.csr118163CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_VB_3_SETns_noc_io_pcie_soc_ip.csr118178VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_RSV_3_SETns_noc_io_pcie_soc_ip.csr118189RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_J_UNSD_3_SETns_noc_io_pcie_soc_ip.csr118199UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rovcs_krouter_0_5_5_rovcs_kPCIE_NOC_ROUTER_0_5_5_ROVCS_K_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROVCS_K_OFFSETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118461R0_5 register rovcs_k0x38078R0x00000101Pcie_noc_router_0_5_5_rovcs_kThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_0_SETns_noc_io_pcie_soc_ip.csr118224CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_0_SETns_noc_io_pcie_soc_ip.csr118238CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_0_SETns_noc_io_pcie_soc_ip.csr118253VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_0_SETns_noc_io_pcie_soc_ip.csr118264RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_0_SETns_noc_io_pcie_soc_ip.csr118274UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_1_SETns_noc_io_pcie_soc_ip.csr118286CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_1_SETns_noc_io_pcie_soc_ip.csr118300CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_1_SETns_noc_io_pcie_soc_ip.csr118315VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_1_SETns_noc_io_pcie_soc_ip.csr118326RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_1_SETns_noc_io_pcie_soc_ip.csr118336UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_2_SETns_noc_io_pcie_soc_ip.csr118348CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_2_SETns_noc_io_pcie_soc_ip.csr118362CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_2_SETns_noc_io_pcie_soc_ip.csr118377VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_2_SETns_noc_io_pcie_soc_ip.csr118388RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_2_SETns_noc_io_pcie_soc_ip.csr118398UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CF_3_SETns_noc_io_pcie_soc_ip.csr118410CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_CE_3_SETns_noc_io_pcie_soc_ip.csr118424CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_VB_3_SETns_noc_io_pcie_soc_ip.csr118439VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_RSV_3_SETns_noc_io_pcie_soc_ip.csr118450RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_MSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_LSBPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_RANGEPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_RESETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_GETPCIE_NOC_ROUTER_0_5_5_ROVCS_K_UNSD_3_SETns_noc_io_pcie_soc_ip.csr118460UNSD_331280x0Rregisterpcie_noc.router_0_5_5_rerouter_0_5_5_rePCIE_NOC_ROUTER_0_5_5_RE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RE_OFFSETPCIE_NOC_ROUTER_0_5_5_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118635R0_5 register re0x38080R/W0x00000000Pcie_noc_router_0_5_5_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_0_5_5_RE_OVFI_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_OVFI_MSBPCIE_NOC_ROUTER_0_5_5_RE_OVFI_LSBPCIE_NOC_ROUTER_0_5_5_RE_OVFI_RANGEPCIE_NOC_ROUTER_0_5_5_RE_OVFI_RESETPCIE_NOC_ROUTER_0_5_5_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_OVFI_GETPCIE_NOC_ROUTER_0_5_5_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr118487OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_0_5_5_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr118498CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_0_5_5_RE_OVFO_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_OVFO_MSBPCIE_NOC_ROUTER_0_5_5_RE_OVFO_LSBPCIE_NOC_ROUTER_0_5_5_RE_OVFO_RANGEPCIE_NOC_ROUTER_0_5_5_RE_OVFO_RESETPCIE_NOC_ROUTER_0_5_5_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_OVFO_GETPCIE_NOC_ROUTER_0_5_5_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr118512OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_0_5_5_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr118523UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_0_5_5_RE_PGE_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_PGE_MSBPCIE_NOC_ROUTER_0_5_5_RE_PGE_LSBPCIE_NOC_ROUTER_0_5_5_RE_PGE_RANGEPCIE_NOC_ROUTER_0_5_5_RE_PGE_RESETPCIE_NOC_ROUTER_0_5_5_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_PGE_GETPCIE_NOC_ROUTER_0_5_5_RE_PGE_SETns_noc_io_pcie_soc_ip.csr118535PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_0_5_5_RE_NLU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_NLU_MSBPCIE_NOC_ROUTER_0_5_5_RE_NLU_LSBPCIE_NOC_ROUTER_0_5_5_RE_NLU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_NLU_RESETPCIE_NOC_ROUTER_0_5_5_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_NLU_GETPCIE_NOC_ROUTER_0_5_5_RE_NLU_SETns_noc_io_pcie_soc_ip.csr118546NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_0_5_5_RE_ELU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_ELU_MSBPCIE_NOC_ROUTER_0_5_5_RE_ELU_LSBPCIE_NOC_ROUTER_0_5_5_RE_ELU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_ELU_RESETPCIE_NOC_ROUTER_0_5_5_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_ELU_GETPCIE_NOC_ROUTER_0_5_5_RE_ELU_SETns_noc_io_pcie_soc_ip.csr118557ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_0_5_5_RE_WLU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_WLU_MSBPCIE_NOC_ROUTER_0_5_5_RE_WLU_LSBPCIE_NOC_ROUTER_0_5_5_RE_WLU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_WLU_RESETPCIE_NOC_ROUTER_0_5_5_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_WLU_GETPCIE_NOC_ROUTER_0_5_5_RE_WLU_SETns_noc_io_pcie_soc_ip.csr118568WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_0_5_5_RE_SLU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_SLU_MSBPCIE_NOC_ROUTER_0_5_5_RE_SLU_LSBPCIE_NOC_ROUTER_0_5_5_RE_SLU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_SLU_RESETPCIE_NOC_ROUTER_0_5_5_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_SLU_GETPCIE_NOC_ROUTER_0_5_5_RE_SLU_SETns_noc_io_pcie_soc_ip.csr118579SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_0_5_5_RE_HLU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_HLU_MSBPCIE_NOC_ROUTER_0_5_5_RE_HLU_LSBPCIE_NOC_ROUTER_0_5_5_RE_HLU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_HLU_RESETPCIE_NOC_ROUTER_0_5_5_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_HLU_GETPCIE_NOC_ROUTER_0_5_5_RE_HLU_SETns_noc_io_pcie_soc_ip.csr118590HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_0_5_5_RE_ILU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_ILU_MSBPCIE_NOC_ROUTER_0_5_5_RE_ILU_LSBPCIE_NOC_ROUTER_0_5_5_RE_ILU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_ILU_RESETPCIE_NOC_ROUTER_0_5_5_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_ILU_GETPCIE_NOC_ROUTER_0_5_5_RE_ILU_SETns_noc_io_pcie_soc_ip.csr118601ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_0_5_5_RE_JLU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_JLU_MSBPCIE_NOC_ROUTER_0_5_5_RE_JLU_LSBPCIE_NOC_ROUTER_0_5_5_RE_JLU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_JLU_RESETPCIE_NOC_ROUTER_0_5_5_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_JLU_GETPCIE_NOC_ROUTER_0_5_5_RE_JLU_SETns_noc_io_pcie_soc_ip.csr118612JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_0_5_5_RE_KLU_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_KLU_MSBPCIE_NOC_ROUTER_0_5_5_RE_KLU_LSBPCIE_NOC_ROUTER_0_5_5_RE_KLU_RANGEPCIE_NOC_ROUTER_0_5_5_RE_KLU_RESETPCIE_NOC_ROUTER_0_5_5_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_KLU_GETPCIE_NOC_ROUTER_0_5_5_RE_KLU_SETns_noc_io_pcie_soc_ip.csr118623KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_0_5_5_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr118634UNSD_31_1431170x0000Rregisterpcie_noc.router_0_5_5_remrouter_0_5_5_remPCIE_NOC_ROUTER_0_5_5_REM_ADDRESSPCIE_NOC_ROUTER_0_5_5_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_REM_OFFSETPCIE_NOC_ROUTER_0_5_5_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118808R0_5 register rem0x38088R/W0x0001fe00Pcie_noc_router_0_5_5_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_MSBPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_LSBPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_RANGEPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_RESETPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_GETPCIE_NOC_ROUTER_0_5_5_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr118661OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_0_5_5_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr118672CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_MSBPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_LSBPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_RANGEPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_RESETPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_GETPCIE_NOC_ROUTER_0_5_5_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr118686OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_0_5_5_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr118697UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_0_5_5_REM_PGM_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_PGM_MSBPCIE_NOC_ROUTER_0_5_5_REM_PGM_LSBPCIE_NOC_ROUTER_0_5_5_REM_PGM_RANGEPCIE_NOC_ROUTER_0_5_5_REM_PGM_RESETPCIE_NOC_ROUTER_0_5_5_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_PGM_GETPCIE_NOC_ROUTER_0_5_5_REM_PGM_SETns_noc_io_pcie_soc_ip.csr118708PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_0_5_5_REM_MN_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MN_MSBPCIE_NOC_ROUTER_0_5_5_REM_MN_LSBPCIE_NOC_ROUTER_0_5_5_REM_MN_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MN_RESETPCIE_NOC_ROUTER_0_5_5_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MN_GETPCIE_NOC_ROUTER_0_5_5_REM_MN_SETns_noc_io_pcie_soc_ip.csr118719MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_0_5_5_REM_ME_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_ME_MSBPCIE_NOC_ROUTER_0_5_5_REM_ME_LSBPCIE_NOC_ROUTER_0_5_5_REM_ME_RANGEPCIE_NOC_ROUTER_0_5_5_REM_ME_RESETPCIE_NOC_ROUTER_0_5_5_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_ME_GETPCIE_NOC_ROUTER_0_5_5_REM_ME_SETns_noc_io_pcie_soc_ip.csr118730ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_0_5_5_REM_MW_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MW_MSBPCIE_NOC_ROUTER_0_5_5_REM_MW_LSBPCIE_NOC_ROUTER_0_5_5_REM_MW_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MW_RESETPCIE_NOC_ROUTER_0_5_5_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MW_GETPCIE_NOC_ROUTER_0_5_5_REM_MW_SETns_noc_io_pcie_soc_ip.csr118741MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_0_5_5_REM_MS_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MS_MSBPCIE_NOC_ROUTER_0_5_5_REM_MS_LSBPCIE_NOC_ROUTER_0_5_5_REM_MS_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MS_RESETPCIE_NOC_ROUTER_0_5_5_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MS_GETPCIE_NOC_ROUTER_0_5_5_REM_MS_SETns_noc_io_pcie_soc_ip.csr118752MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_0_5_5_REM_MH_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MH_MSBPCIE_NOC_ROUTER_0_5_5_REM_MH_LSBPCIE_NOC_ROUTER_0_5_5_REM_MH_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MH_RESETPCIE_NOC_ROUTER_0_5_5_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MH_GETPCIE_NOC_ROUTER_0_5_5_REM_MH_SETns_noc_io_pcie_soc_ip.csr118763MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_0_5_5_REM_MI_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MI_MSBPCIE_NOC_ROUTER_0_5_5_REM_MI_LSBPCIE_NOC_ROUTER_0_5_5_REM_MI_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MI_RESETPCIE_NOC_ROUTER_0_5_5_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MI_GETPCIE_NOC_ROUTER_0_5_5_REM_MI_SETns_noc_io_pcie_soc_ip.csr118774MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_0_5_5_REM_MJ_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MJ_MSBPCIE_NOC_ROUTER_0_5_5_REM_MJ_LSBPCIE_NOC_ROUTER_0_5_5_REM_MJ_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MJ_RESETPCIE_NOC_ROUTER_0_5_5_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MJ_GETPCIE_NOC_ROUTER_0_5_5_REM_MJ_SETns_noc_io_pcie_soc_ip.csr118785MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_0_5_5_REM_MK_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_MK_MSBPCIE_NOC_ROUTER_0_5_5_REM_MK_LSBPCIE_NOC_ROUTER_0_5_5_REM_MK_RANGEPCIE_NOC_ROUTER_0_5_5_REM_MK_RESETPCIE_NOC_ROUTER_0_5_5_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_MK_GETPCIE_NOC_ROUTER_0_5_5_REM_MK_SETns_noc_io_pcie_soc_ip.csr118796MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_0_5_5_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr118807UNSD_31_1431170x0000Rregisterpcie_noc.router_0_5_5_reccrouter_0_5_5_reccPCIE_NOC_ROUTER_0_5_5_RECC_ADDRESSPCIE_NOC_ROUTER_0_5_5_RECC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RECC_OFFSETPCIE_NOC_ROUTER_0_5_5_RECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118893R0_5 register recc0x38090R/W0x00000000Pcie_noc_router_0_5_5_reccThis register is used to select which hardware events will increment the event counter.falsefalsefalsefalseIVCPCIE_NOC_ROUTER_0_5_5_RECC_IVC_WIDTHPCIE_NOC_ROUTER_0_5_5_RECC_IVC_MSBPCIE_NOC_ROUTER_0_5_5_RECC_IVC_LSBPCIE_NOC_ROUTER_0_5_5_RECC_IVC_RANGEPCIE_NOC_ROUTER_0_5_5_RECC_IVC_RESETPCIE_NOC_ROUTER_0_5_5_RECC_IVC_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RECC_IVC_GETPCIE_NOC_ROUTER_0_5_5_RECC_IVC_SETns_noc_io_pcie_soc_ip.csr118829IVC11: Input VC 310: Input VC 201: Input VC 100: Input VC 0100x0R/WUNSD_3_2PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_WIDTHPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_MSBPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_LSBPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_RANGEPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_RESETPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_GETPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_3_2_SETns_noc_io_pcie_soc_ip.csr118840UNSD_3_2320x0RINPPCIE_NOC_ROUTER_0_5_5_RECC_INP_WIDTHPCIE_NOC_ROUTER_0_5_5_RECC_INP_MSBPCIE_NOC_ROUTER_0_5_5_RECC_INP_LSBPCIE_NOC_ROUTER_0_5_5_RECC_INP_RANGEPCIE_NOC_ROUTER_0_5_5_RECC_INP_RESETPCIE_NOC_ROUTER_0_5_5_RECC_INP_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RECC_INP_GETPCIE_NOC_ROUTER_0_5_5_RECC_INP_SETns_noc_io_pcie_soc_ip.csr118851INPInput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_GETPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr118862UNSD_7_7770x0REVTPCIE_NOC_ROUTER_0_5_5_RECC_EVT_WIDTHPCIE_NOC_ROUTER_0_5_5_RECC_EVT_MSBPCIE_NOC_ROUTER_0_5_5_RECC_EVT_LSBPCIE_NOC_ROUTER_0_5_5_RECC_EVT_RANGEPCIE_NOC_ROUTER_0_5_5_RECC_EVT_RESETPCIE_NOC_ROUTER_0_5_5_RECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RECC_EVT_GETPCIE_NOC_ROUTER_0_5_5_RECC_EVT_SETns_noc_io_pcie_soc_ip.csr118881EVT11: Generates count event when VC has valid data, but is stalled10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port00: Disable980x0R/WUNSD_31_10PCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_WIDTHPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_MSBPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_LSBPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_RANGEPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_RESETPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_GETPCIE_NOC_ROUTER_0_5_5_RECC_UNSD_31_10_SETns_noc_io_pcie_soc_ip.csr118892UNSD_31_1031100x000000Rregisterpcie_noc.router_0_5_5_recrouter_0_5_5_recPCIE_NOC_ROUTER_0_5_5_REC_ADDRESSPCIE_NOC_ROUTER_0_5_5_REC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_REC_OFFSETPCIE_NOC_ROUTER_0_5_5_REC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118918R0_5 register rec0x38098R/W0x00000000Pcie_noc_router_0_5_5_recThis register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_GETPCIE_NOC_ROUTER_0_5_5_REC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr118917EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_0_5_5_idrouter_0_5_5_idPCIE_NOC_ROUTER_0_5_5_ID_ADDRESSPCIE_NOC_ROUTER_0_5_5_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ID_OFFSETPCIE_NOC_ROUTER_0_5_5_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr118987R0_5 register id0x380A0R0x010000a0Pcie_noc_router_0_5_5_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_0_5_5_ID_LAYER_WIDTHPCIE_NOC_ROUTER_0_5_5_ID_LAYER_MSBPCIE_NOC_ROUTER_0_5_5_ID_LAYER_LSBPCIE_NOC_ROUTER_0_5_5_ID_LAYER_RANGEPCIE_NOC_ROUTER_0_5_5_ID_LAYER_RESETPCIE_NOC_ROUTER_0_5_5_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ID_LAYER_GETPCIE_NOC_ROUTER_0_5_5_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr118943LAYER5-bit identifier of the NoC layer on which this router is located400x00RPOSPCIE_NOC_ROUTER_0_5_5_ID_POS_WIDTHPCIE_NOC_ROUTER_0_5_5_ID_POS_MSBPCIE_NOC_ROUTER_0_5_5_ID_POS_LSBPCIE_NOC_ROUTER_0_5_5_ID_POS_RANGEPCIE_NOC_ROUTER_0_5_5_ID_POS_RESETPCIE_NOC_ROUTER_0_5_5_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ID_POS_GETPCIE_NOC_ROUTER_0_5_5_ID_POS_SETns_noc_io_pcie_soc_ip.csr118954POS16-bit position ID of this router in the NoC2050x0005RZEROPCIE_NOC_ROUTER_0_5_5_ID_ZERO_WIDTHPCIE_NOC_ROUTER_0_5_5_ID_ZERO_MSBPCIE_NOC_ROUTER_0_5_5_ID_ZERO_LSBPCIE_NOC_ROUTER_0_5_5_ID_ZERO_RANGEPCIE_NOC_ROUTER_0_5_5_ID_ZERO_RESETPCIE_NOC_ROUTER_0_5_5_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ID_ZERO_GETPCIE_NOC_ROUTER_0_5_5_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr118965ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_0_5_5_ID_ONE_WIDTHPCIE_NOC_ROUTER_0_5_5_ID_ONE_MSBPCIE_NOC_ROUTER_0_5_5_ID_ONE_LSBPCIE_NOC_ROUTER_0_5_5_ID_ONE_RANGEPCIE_NOC_ROUTER_0_5_5_ID_ONE_RESETPCIE_NOC_ROUTER_0_5_5_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ID_ONE_GETPCIE_NOC_ROUTER_0_5_5_ID_ONE_SETns_noc_io_pcie_soc_ip.csr118976ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_0_5_5_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr118986UNSD_31_2531250x00Rregisterpcie_noc.router_0_5_5_rcgcrouter_0_5_5_rcgcPCIE_NOC_ROUTER_0_5_5_RCGC_ADDRESSPCIE_NOC_ROUTER_0_5_5_RCGC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RCGC_OFFSETPCIE_NOC_ROUTER_0_5_5_RCGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr119013R0_5 register rcgc0x380A8R/W0x00000064Pcie_noc_router_0_5_5_rcgcProgrammable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_GETPCIE_NOC_ROUTER_0_5_5_RCGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr119012HYSTERESIS_COUNTERHysteresis counter3100x00000064R/Wregisterpcie_noc.router_0_5_5_rcgorouter_0_5_5_rcgoPCIE_NOC_ROUTER_0_5_5_RCGO_ADDRESSPCIE_NOC_ROUTER_0_5_5_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_RCGO_OFFSETPCIE_NOC_ROUTER_0_5_5_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr119052R0_5 register rcgo0x380B0R/W0x00000000Pcie_noc_router_0_5_5_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_MSBPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_LSBPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_RANGEPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_RESETPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_GETPCIE_NOC_ROUTER_0_5_5_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr119040FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_0_5_5_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr119051UNSD_31_13110x00000000Rregisterpcie_noc.router_0_5_5_p1_rperrrouter_0_5_5_p1_rperrPCIE_NOC_ROUTER_0_5_5_P1_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P1_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P1_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr119339R0_5 register p1_rperr0x380C0R/W0x00000000Pcie_noc_router_0_5_5_p1_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_SETns_noc_io_pcie_soc_ip.csr119095D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr119106SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr119117PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr119128RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr119139CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr119150UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr119161D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr119172SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr119184PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr119195RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr119206D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr119217SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr119229PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr119240RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr119252D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr119264SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr119277PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr119289RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr119301D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr119313SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr119326PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr119338RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p2_rperrrouter_0_5_5_p2_rperrPCIE_NOC_ROUTER_0_5_5_P2_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P2_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P2_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr119630R0_5 register p2_rperr0x380C8R/W0x00000000Pcie_noc_router_0_5_5_p2_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_SETns_noc_io_pcie_soc_ip.csr119382D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr119393SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr119404PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr119415RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr119426CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr119437UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr119448D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr119459SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr119471PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr119482RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr119494D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr119506SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr119519PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr119531RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr119543D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr119555SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr119568PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr119580RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr119592D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr119604SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr119617PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr119629RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p3_rperrrouter_0_5_5_p3_rperrPCIE_NOC_ROUTER_0_5_5_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P3_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr119921R0_5 register p3_rperr0x380D0R/W0x00000000Pcie_noc_router_0_5_5_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr119673D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr119684SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr119695PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr119706RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr119717CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr119728UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr119739D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr119750SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr119762PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr119773RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr119785D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr119797SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr119810PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr119822RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr119834D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr119846SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr119859PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr119871RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr119883D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr119895SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr119908PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr119920RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p4_rperrrouter_0_5_5_p4_rperrPCIE_NOC_ROUTER_0_5_5_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P4_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr120212R0_5 register p4_rperr0x380D8R/W0x00000000Pcie_noc_router_0_5_5_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr119964D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr119975SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr119986PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr119997RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr120008CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr120019UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr120030D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr120041SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr120053PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr120064RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr120076D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr120088SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr120101PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr120113RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr120125D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr120137SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr120150PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr120162RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr120174D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr120186SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr120199PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr120211RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p5_rperrrouter_0_5_5_p5_rperrPCIE_NOC_ROUTER_0_5_5_P5_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P5_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P5_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr120503R0_5 register p5_rperr0x380E0R/W0x00000000Pcie_noc_router_0_5_5_p5_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_SETns_noc_io_pcie_soc_ip.csr120255D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr120266SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr120277PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr120288RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr120299CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr120310UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr120321D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr120332SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr120344PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr120355RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr120367D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr120379SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr120392PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr120404RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr120416D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr120428SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr120441PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr120453RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr120465D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr120477SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr120490PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr120502RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p6_rperrrouter_0_5_5_p6_rperrPCIE_NOC_ROUTER_0_5_5_P6_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P6_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P6_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr120794R0_5 register p6_rperr0x380E8R/W0x00000000Pcie_noc_router_0_5_5_p6_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_SETns_noc_io_pcie_soc_ip.csr120546D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr120557SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr120568PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr120579RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr120590CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr120601UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr120612D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr120623SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr120635PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr120646RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr120658D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr120670SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr120683PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr120695RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr120707D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr120719SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr120732PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr120744RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr120756D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr120768SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr120781PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr120793RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p7_rperrrouter_0_5_5_p7_rperrPCIE_NOC_ROUTER_0_5_5_P7_RPERR_ADDRESSPCIE_NOC_ROUTER_0_5_5_P7_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P7_RPERR_OFFSETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr121085R0_5 register p7_rperr0x380F0R/W0x00000000Pcie_noc_router_0_5_5_p7_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_SETns_noc_io_pcie_soc_ip.csr120837D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr120848SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr120859PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr120870RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr120881CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr120892UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr120903D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr120914SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr120926PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr120937RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr120949D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr120961SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr120974PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr120986RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr120998D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr121010SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr121023PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr121035RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr121047D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr121059SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr121072PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr121084RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_5_5_p1_rperrmrouter_0_5_5_p1_rperrmPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr121343R0_5 register p1_rperrm0x38100R/W0x00000000Pcie_noc_router_0_5_5_p1_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr121107DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr121118SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr121129PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr121140RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr121151CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr121162UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr121173D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr121184SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr121196PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr121207RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr121218D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr121229SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr121241PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr121252RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr121263D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr121274SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr121286PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr121297RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr121308D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr121319SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr121331PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P1_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr121342RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_p2_rperrmrouter_0_5_5_p2_rperrmPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr121601R0_5 register p2_rperrm0x38108R/W0x00000000Pcie_noc_router_0_5_5_p2_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr121365DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr121376SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr121387PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr121398RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr121409CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr121420UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr121431D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr121442SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr121454PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr121465RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr121476D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr121487SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr121499PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr121510RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr121521D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr121532SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr121544PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr121555RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr121566D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr121577SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr121589PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P2_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr121600RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_p3_rperrmrouter_0_5_5_p3_rperrmPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr121859R0_5 register p3_rperrm0x38110R/W0x00000000Pcie_noc_router_0_5_5_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr121623DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr121634SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr121645PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr121656RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr121667CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr121678UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr121689D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr121700SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr121712PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr121723RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr121734D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr121745SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr121757PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr121768RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr121779D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr121790SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr121802PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr121813RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr121824D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr121835SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr121847PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr121858RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_p4_rperrmrouter_0_5_5_p4_rperrmPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr122117R0_5 register p4_rperrm0x38118R/W0x00000000Pcie_noc_router_0_5_5_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr121881DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr121892SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr121903PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr121914RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr121925CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr121936UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr121947D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr121958SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr121970PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr121981RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr121992D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr122003SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr122015PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr122026RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr122037D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr122048SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr122060PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr122071RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr122082D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr122093SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr122105PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr122116RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_p5_rperrmrouter_0_5_5_p5_rperrmPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr122375R0_5 register p5_rperrm0x38120R/W0x00000000Pcie_noc_router_0_5_5_p5_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr122139DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr122150SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr122161PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr122172RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr122183CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr122194UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr122205D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr122216SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr122228PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr122239RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr122250D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr122261SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr122273PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr122284RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr122295D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr122306SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr122318PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr122329RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr122340D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr122351SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr122363PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P5_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr122374RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_p6_rperrmrouter_0_5_5_p6_rperrmPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr122633R0_5 register p6_rperrm0x38128R/W0x00000000Pcie_noc_router_0_5_5_p6_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr122397DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr122408SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr122419PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr122430RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr122441CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr122452UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr122463D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr122474SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr122486PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr122497RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr122508D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr122519SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr122531PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr122542RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr122553D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr122564SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr122576PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr122587RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr122598D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr122609SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr122621PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P6_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr122632RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_p7_rperrmrouter_0_5_5_p7_rperrmPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_OFFSETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr122891R0_5 register p7_rperrm0x38130R/W0x00000000Pcie_noc_router_0_5_5_p7_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr122655DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr122666SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr122677PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr122688RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr122699CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr122710UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr122721D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr122732SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr122744PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr122755RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr122766D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr122777SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr122789PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr122800RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr122811D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr122822SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr122834PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr122845RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr122856D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr122867SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr122879PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_5_5_P7_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr122890RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_5_5_roeccrouter_0_5_5_roeccPCIE_NOC_ROUTER_0_5_5_ROECC_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROECC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROECC_OFFSETPCIE_NOC_ROUTER_0_5_5_ROECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr122964R0_5 register roecc0x38138R/W0x00000000Pcie_noc_router_0_5_5_roeccThis register is used to select which hardware events will increment the output event counter.falsefalsefalsefalseOVCPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_WIDTHPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_MSBPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_LSBPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_RANGEPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_RESETPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_GETPCIE_NOC_ROUTER_0_5_5_ROECC_OVC_SETns_noc_io_pcie_soc_ip.csr122909OVCBit map to select output VCs to monitor events on300x0R/WOPPCIE_NOC_ROUTER_0_5_5_ROECC_OP_WIDTHPCIE_NOC_ROUTER_0_5_5_ROECC_OP_MSBPCIE_NOC_ROUTER_0_5_5_ROECC_OP_LSBPCIE_NOC_ROUTER_0_5_5_ROECC_OP_RANGEPCIE_NOC_ROUTER_0_5_5_ROECC_OP_RESETPCIE_NOC_ROUTER_0_5_5_ROECC_OP_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROECC_OP_GETPCIE_NOC_ROUTER_0_5_5_ROECC_OP_SETns_noc_io_pcie_soc_ip.csr122920OPOutput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_GETPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr122931UNSD_7_7770x0REVTPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_WIDTHPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_MSBPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_LSBPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_RANGEPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_RESETPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_GETPCIE_NOC_ROUTER_0_5_5_ROECC_EVT_SETns_noc_io_pcie_soc_ip.csr122952EVT100: Port stalled. Input flits are available for the port, but no output VC has credit011: Generates count event when flits are available to be sent to output VC, but the VC has no credit010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port000: Disable1080x0R/WUNSD_31_11PCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_WIDTHPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_MSBPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_LSBPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_RANGEPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_RESETPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_GETPCIE_NOC_ROUTER_0_5_5_ROECC_UNSD_31_11_SETns_noc_io_pcie_soc_ip.csr122963UNSD_31_1131110x000000Rregisterpcie_noc.router_0_5_5_roecrouter_0_5_5_roecPCIE_NOC_ROUTER_0_5_5_ROEC_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROEC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_5_5_ROEC_OFFSETPCIE_NOC_ROUTER_0_5_5_ROEC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr122989R0_5 register roec0x38140R/W0x00000000Pcie_noc_router_0_5_5_roecThis register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_GETPCIE_NOC_ROUTER_0_5_5_ROEC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr122988EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_0_6_6_rivcs_hrouter_0_6_6_rivcs_hPCIE_NOC_ROUTER_0_6_6_RIVCS_H_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr123318R0_6 register rivcs_h0x3C000R0x00000000Pcie_noc_router_0_6_6_rivcs_hThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_0_SETns_noc_io_pcie_soc_ip.csr123014OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_0_SETns_noc_io_pcie_soc_ip.csr123028UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_0_SETns_noc_io_pcie_soc_ip.csr123044S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_0_SETns_noc_io_pcie_soc_ip.csr123058B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_0_SETns_noc_io_pcie_soc_ip.csr123069F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_0_SETns_noc_io_pcie_soc_ip.csr123080V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_1_SETns_noc_io_pcie_soc_ip.csr123093OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_1_SETns_noc_io_pcie_soc_ip.csr123107UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_1_SETns_noc_io_pcie_soc_ip.csr123123S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_1_SETns_noc_io_pcie_soc_ip.csr123137B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_1_SETns_noc_io_pcie_soc_ip.csr123148F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_1_SETns_noc_io_pcie_soc_ip.csr123159V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_2_SETns_noc_io_pcie_soc_ip.csr123172OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_2_SETns_noc_io_pcie_soc_ip.csr123186UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_2_SETns_noc_io_pcie_soc_ip.csr123202S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_2_SETns_noc_io_pcie_soc_ip.csr123216B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_2_SETns_noc_io_pcie_soc_ip.csr123227F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_2_SETns_noc_io_pcie_soc_ip.csr123238V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_OUTP_3_SETns_noc_io_pcie_soc_ip.csr123251OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_UP_3_SETns_noc_io_pcie_soc_ip.csr123265UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_S_3_SETns_noc_io_pcie_soc_ip.csr123281S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_B_3_SETns_noc_io_pcie_soc_ip.csr123295B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_F_3_SETns_noc_io_pcie_soc_ip.csr123306F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_H_V_3_SETns_noc_io_pcie_soc_ip.csr123317V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_erouter_0_6_6_rivcs_ePCIE_NOC_ROUTER_0_6_6_RIVCS_E_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr123647R0_6 register rivcs_e0x3C008R0x00000000Pcie_noc_router_0_6_6_rivcs_eThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_0_SETns_noc_io_pcie_soc_ip.csr123343OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_0_SETns_noc_io_pcie_soc_ip.csr123357UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_0_SETns_noc_io_pcie_soc_ip.csr123373S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_0_SETns_noc_io_pcie_soc_ip.csr123387B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_0_SETns_noc_io_pcie_soc_ip.csr123398F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_0_SETns_noc_io_pcie_soc_ip.csr123409V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_1_SETns_noc_io_pcie_soc_ip.csr123422OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_1_SETns_noc_io_pcie_soc_ip.csr123436UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_1_SETns_noc_io_pcie_soc_ip.csr123452S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_1_SETns_noc_io_pcie_soc_ip.csr123466B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_1_SETns_noc_io_pcie_soc_ip.csr123477F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_1_SETns_noc_io_pcie_soc_ip.csr123488V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_2_SETns_noc_io_pcie_soc_ip.csr123501OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_2_SETns_noc_io_pcie_soc_ip.csr123515UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_2_SETns_noc_io_pcie_soc_ip.csr123531S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_2_SETns_noc_io_pcie_soc_ip.csr123545B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_2_SETns_noc_io_pcie_soc_ip.csr123556F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_2_SETns_noc_io_pcie_soc_ip.csr123567V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_OUTP_3_SETns_noc_io_pcie_soc_ip.csr123580OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_UP_3_SETns_noc_io_pcie_soc_ip.csr123594UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_S_3_SETns_noc_io_pcie_soc_ip.csr123610S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_B_3_SETns_noc_io_pcie_soc_ip.csr123624B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_F_3_SETns_noc_io_pcie_soc_ip.csr123635F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_E_V_3_SETns_noc_io_pcie_soc_ip.csr123646V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_srouter_0_6_6_rivcs_sPCIE_NOC_ROUTER_0_6_6_RIVCS_S_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr123976R0_6 register rivcs_s0x3C010R0x00000000Pcie_noc_router_0_6_6_rivcs_sThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_0_SETns_noc_io_pcie_soc_ip.csr123672OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_0_SETns_noc_io_pcie_soc_ip.csr123686UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_0_SETns_noc_io_pcie_soc_ip.csr123702S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_0_SETns_noc_io_pcie_soc_ip.csr123716B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_0_SETns_noc_io_pcie_soc_ip.csr123727F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_0_SETns_noc_io_pcie_soc_ip.csr123738V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_1_SETns_noc_io_pcie_soc_ip.csr123751OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_1_SETns_noc_io_pcie_soc_ip.csr123765UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_1_SETns_noc_io_pcie_soc_ip.csr123781S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_1_SETns_noc_io_pcie_soc_ip.csr123795B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_1_SETns_noc_io_pcie_soc_ip.csr123806F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_1_SETns_noc_io_pcie_soc_ip.csr123817V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_2_SETns_noc_io_pcie_soc_ip.csr123830OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_2_SETns_noc_io_pcie_soc_ip.csr123844UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_2_SETns_noc_io_pcie_soc_ip.csr123860S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_2_SETns_noc_io_pcie_soc_ip.csr123874B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_2_SETns_noc_io_pcie_soc_ip.csr123885F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_2_SETns_noc_io_pcie_soc_ip.csr123896V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_OUTP_3_SETns_noc_io_pcie_soc_ip.csr123909OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_UP_3_SETns_noc_io_pcie_soc_ip.csr123923UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_S_3_SETns_noc_io_pcie_soc_ip.csr123939S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_B_3_SETns_noc_io_pcie_soc_ip.csr123953B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_F_3_SETns_noc_io_pcie_soc_ip.csr123964F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_S_V_3_SETns_noc_io_pcie_soc_ip.csr123975V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_wrouter_0_6_6_rivcs_wPCIE_NOC_ROUTER_0_6_6_RIVCS_W_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr124305R0_6 register rivcs_w0x3C018R0x00000000Pcie_noc_router_0_6_6_rivcs_wThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_0_SETns_noc_io_pcie_soc_ip.csr124001OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_0_SETns_noc_io_pcie_soc_ip.csr124015UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_0_SETns_noc_io_pcie_soc_ip.csr124031S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_0_SETns_noc_io_pcie_soc_ip.csr124045B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_0_SETns_noc_io_pcie_soc_ip.csr124056F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_0_SETns_noc_io_pcie_soc_ip.csr124067V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_1_SETns_noc_io_pcie_soc_ip.csr124080OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_1_SETns_noc_io_pcie_soc_ip.csr124094UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_1_SETns_noc_io_pcie_soc_ip.csr124110S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_1_SETns_noc_io_pcie_soc_ip.csr124124B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_1_SETns_noc_io_pcie_soc_ip.csr124135F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_1_SETns_noc_io_pcie_soc_ip.csr124146V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_2_SETns_noc_io_pcie_soc_ip.csr124159OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_2_SETns_noc_io_pcie_soc_ip.csr124173UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_2_SETns_noc_io_pcie_soc_ip.csr124189S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_2_SETns_noc_io_pcie_soc_ip.csr124203B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_2_SETns_noc_io_pcie_soc_ip.csr124214F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_2_SETns_noc_io_pcie_soc_ip.csr124225V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_OUTP_3_SETns_noc_io_pcie_soc_ip.csr124238OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_UP_3_SETns_noc_io_pcie_soc_ip.csr124252UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_S_3_SETns_noc_io_pcie_soc_ip.csr124268S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_B_3_SETns_noc_io_pcie_soc_ip.csr124282B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_F_3_SETns_noc_io_pcie_soc_ip.csr124293F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_W_V_3_SETns_noc_io_pcie_soc_ip.csr124304V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_nrouter_0_6_6_rivcs_nPCIE_NOC_ROUTER_0_6_6_RIVCS_N_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_N_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr124634R0_6 register rivcs_n0x3C020R0x00000000Pcie_noc_router_0_6_6_rivcs_nThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_0_SETns_noc_io_pcie_soc_ip.csr124330OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_0_SETns_noc_io_pcie_soc_ip.csr124344UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_0_SETns_noc_io_pcie_soc_ip.csr124360S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_0_SETns_noc_io_pcie_soc_ip.csr124374B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_0_SETns_noc_io_pcie_soc_ip.csr124385F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_0_SETns_noc_io_pcie_soc_ip.csr124396V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_1_SETns_noc_io_pcie_soc_ip.csr124409OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_1_SETns_noc_io_pcie_soc_ip.csr124423UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_1_SETns_noc_io_pcie_soc_ip.csr124439S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_1_SETns_noc_io_pcie_soc_ip.csr124453B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_1_SETns_noc_io_pcie_soc_ip.csr124464F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_1_SETns_noc_io_pcie_soc_ip.csr124475V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_2_SETns_noc_io_pcie_soc_ip.csr124488OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_2_SETns_noc_io_pcie_soc_ip.csr124502UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_2_SETns_noc_io_pcie_soc_ip.csr124518S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_2_SETns_noc_io_pcie_soc_ip.csr124532B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_2_SETns_noc_io_pcie_soc_ip.csr124543F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_2_SETns_noc_io_pcie_soc_ip.csr124554V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_OUTP_3_SETns_noc_io_pcie_soc_ip.csr124567OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_UP_3_SETns_noc_io_pcie_soc_ip.csr124581UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_S_3_SETns_noc_io_pcie_soc_ip.csr124597S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_B_3_SETns_noc_io_pcie_soc_ip.csr124611B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_F_3_SETns_noc_io_pcie_soc_ip.csr124622F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_N_V_3_SETns_noc_io_pcie_soc_ip.csr124633V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_irouter_0_6_6_rivcs_iPCIE_NOC_ROUTER_0_6_6_RIVCS_I_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr124963R0_6 register rivcs_i0x3C028R0x00000000Pcie_noc_router_0_6_6_rivcs_iThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_0_SETns_noc_io_pcie_soc_ip.csr124659OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_0_SETns_noc_io_pcie_soc_ip.csr124673UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_0_SETns_noc_io_pcie_soc_ip.csr124689S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_0_SETns_noc_io_pcie_soc_ip.csr124703B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_0_SETns_noc_io_pcie_soc_ip.csr124714F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_0_SETns_noc_io_pcie_soc_ip.csr124725V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_1_SETns_noc_io_pcie_soc_ip.csr124738OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_1_SETns_noc_io_pcie_soc_ip.csr124752UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_1_SETns_noc_io_pcie_soc_ip.csr124768S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_1_SETns_noc_io_pcie_soc_ip.csr124782B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_1_SETns_noc_io_pcie_soc_ip.csr124793F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_1_SETns_noc_io_pcie_soc_ip.csr124804V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_2_SETns_noc_io_pcie_soc_ip.csr124817OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_2_SETns_noc_io_pcie_soc_ip.csr124831UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_2_SETns_noc_io_pcie_soc_ip.csr124847S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_2_SETns_noc_io_pcie_soc_ip.csr124861B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_2_SETns_noc_io_pcie_soc_ip.csr124872F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_2_SETns_noc_io_pcie_soc_ip.csr124883V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_OUTP_3_SETns_noc_io_pcie_soc_ip.csr124896OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_UP_3_SETns_noc_io_pcie_soc_ip.csr124910UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_S_3_SETns_noc_io_pcie_soc_ip.csr124926S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_B_3_SETns_noc_io_pcie_soc_ip.csr124940B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_F_3_SETns_noc_io_pcie_soc_ip.csr124951F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_I_V_3_SETns_noc_io_pcie_soc_ip.csr124962V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_jrouter_0_6_6_rivcs_jPCIE_NOC_ROUTER_0_6_6_RIVCS_J_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr125292R0_6 register rivcs_j0x3C030R0x00000000Pcie_noc_router_0_6_6_rivcs_jThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_0_SETns_noc_io_pcie_soc_ip.csr124988OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_0_SETns_noc_io_pcie_soc_ip.csr125002UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_0_SETns_noc_io_pcie_soc_ip.csr125018S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_0_SETns_noc_io_pcie_soc_ip.csr125032B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_0_SETns_noc_io_pcie_soc_ip.csr125043F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_0_SETns_noc_io_pcie_soc_ip.csr125054V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_1_SETns_noc_io_pcie_soc_ip.csr125067OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_1_SETns_noc_io_pcie_soc_ip.csr125081UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_1_SETns_noc_io_pcie_soc_ip.csr125097S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_1_SETns_noc_io_pcie_soc_ip.csr125111B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_1_SETns_noc_io_pcie_soc_ip.csr125122F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_1_SETns_noc_io_pcie_soc_ip.csr125133V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_2_SETns_noc_io_pcie_soc_ip.csr125146OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_2_SETns_noc_io_pcie_soc_ip.csr125160UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_2_SETns_noc_io_pcie_soc_ip.csr125176S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_2_SETns_noc_io_pcie_soc_ip.csr125190B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_2_SETns_noc_io_pcie_soc_ip.csr125201F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_2_SETns_noc_io_pcie_soc_ip.csr125212V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_OUTP_3_SETns_noc_io_pcie_soc_ip.csr125225OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_UP_3_SETns_noc_io_pcie_soc_ip.csr125239UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_S_3_SETns_noc_io_pcie_soc_ip.csr125255S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_B_3_SETns_noc_io_pcie_soc_ip.csr125269B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_F_3_SETns_noc_io_pcie_soc_ip.csr125280F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_J_V_3_SETns_noc_io_pcie_soc_ip.csr125291V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rivcs_krouter_0_6_6_rivcs_kPCIE_NOC_ROUTER_0_6_6_RIVCS_K_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OFFSETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr125621R0_6 register rivcs_k0x3C038R0x00000000Pcie_noc_router_0_6_6_rivcs_kThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_0_SETns_noc_io_pcie_soc_ip.csr125317OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_0_SETns_noc_io_pcie_soc_ip.csr125331UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_0_SETns_noc_io_pcie_soc_ip.csr125347S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_0_SETns_noc_io_pcie_soc_ip.csr125361B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_0_SETns_noc_io_pcie_soc_ip.csr125372F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_0_SETns_noc_io_pcie_soc_ip.csr125383V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_1_SETns_noc_io_pcie_soc_ip.csr125396OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_1_SETns_noc_io_pcie_soc_ip.csr125410UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_1_SETns_noc_io_pcie_soc_ip.csr125426S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_1_SETns_noc_io_pcie_soc_ip.csr125440B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_1_SETns_noc_io_pcie_soc_ip.csr125451F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_1_SETns_noc_io_pcie_soc_ip.csr125462V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_2_SETns_noc_io_pcie_soc_ip.csr125475OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_2_SETns_noc_io_pcie_soc_ip.csr125489UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_2_SETns_noc_io_pcie_soc_ip.csr125505S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_2_SETns_noc_io_pcie_soc_ip.csr125519B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_2_SETns_noc_io_pcie_soc_ip.csr125530F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_2_SETns_noc_io_pcie_soc_ip.csr125541V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_OUTP_3_SETns_noc_io_pcie_soc_ip.csr125554OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_UP_3_SETns_noc_io_pcie_soc_ip.csr125568UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_S_3_SETns_noc_io_pcie_soc_ip.csr125584S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_B_3_SETns_noc_io_pcie_soc_ip.csr125598B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_F_3_SETns_noc_io_pcie_soc_ip.csr125609F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_MSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_LSBPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_RANGEPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_RESETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_GETPCIE_NOC_ROUTER_0_6_6_RIVCS_K_V_3_SETns_noc_io_pcie_soc_ip.csr125620V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_0_6_6_rovcs_hrouter_0_6_6_rovcs_hPCIE_NOC_ROUTER_0_6_6_ROVCS_H_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_H_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr125882R0_6 register rovcs_h0x3C040R0x00000001Pcie_noc_router_0_6_6_rovcs_hThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_0_SETns_noc_io_pcie_soc_ip.csr125645CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_0_SETns_noc_io_pcie_soc_ip.csr125659CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_0_SETns_noc_io_pcie_soc_ip.csr125674VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_0_SETns_noc_io_pcie_soc_ip.csr125685RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_0_SETns_noc_io_pcie_soc_ip.csr125695UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_1_SETns_noc_io_pcie_soc_ip.csr125707CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_1_SETns_noc_io_pcie_soc_ip.csr125721CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_1_SETns_noc_io_pcie_soc_ip.csr125736VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_1_SETns_noc_io_pcie_soc_ip.csr125747RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_1_SETns_noc_io_pcie_soc_ip.csr125757UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_2_SETns_noc_io_pcie_soc_ip.csr125769CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_2_SETns_noc_io_pcie_soc_ip.csr125783CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_2_SETns_noc_io_pcie_soc_ip.csr125798VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_2_SETns_noc_io_pcie_soc_ip.csr125809RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_2_SETns_noc_io_pcie_soc_ip.csr125819UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CF_3_SETns_noc_io_pcie_soc_ip.csr125831CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_CE_3_SETns_noc_io_pcie_soc_ip.csr125845CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_VB_3_SETns_noc_io_pcie_soc_ip.csr125860VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_RSV_3_SETns_noc_io_pcie_soc_ip.csr125871RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_H_UNSD_3_SETns_noc_io_pcie_soc_ip.csr125881UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_erouter_0_6_6_rovcs_ePCIE_NOC_ROUTER_0_6_6_ROVCS_E_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_E_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr126143R0_6 register rovcs_e0x3C048R0x00000001Pcie_noc_router_0_6_6_rovcs_eThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_0_SETns_noc_io_pcie_soc_ip.csr125906CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_0_SETns_noc_io_pcie_soc_ip.csr125920CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_0_SETns_noc_io_pcie_soc_ip.csr125935VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_0_SETns_noc_io_pcie_soc_ip.csr125946RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_0_SETns_noc_io_pcie_soc_ip.csr125956UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_1_SETns_noc_io_pcie_soc_ip.csr125968CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_1_SETns_noc_io_pcie_soc_ip.csr125982CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_1_SETns_noc_io_pcie_soc_ip.csr125997VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_1_SETns_noc_io_pcie_soc_ip.csr126008RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_1_SETns_noc_io_pcie_soc_ip.csr126018UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_2_SETns_noc_io_pcie_soc_ip.csr126030CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_2_SETns_noc_io_pcie_soc_ip.csr126044CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_2_SETns_noc_io_pcie_soc_ip.csr126059VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_2_SETns_noc_io_pcie_soc_ip.csr126070RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_2_SETns_noc_io_pcie_soc_ip.csr126080UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CF_3_SETns_noc_io_pcie_soc_ip.csr126092CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_CE_3_SETns_noc_io_pcie_soc_ip.csr126106CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_VB_3_SETns_noc_io_pcie_soc_ip.csr126121VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_RSV_3_SETns_noc_io_pcie_soc_ip.csr126132RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_E_UNSD_3_SETns_noc_io_pcie_soc_ip.csr126142UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_srouter_0_6_6_rovcs_sPCIE_NOC_ROUTER_0_6_6_ROVCS_S_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_S_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr126404R0_6 register rovcs_s0x3C050R0x00000001Pcie_noc_router_0_6_6_rovcs_sThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_0_SETns_noc_io_pcie_soc_ip.csr126167CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_0_SETns_noc_io_pcie_soc_ip.csr126181CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_0_SETns_noc_io_pcie_soc_ip.csr126196VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_0_SETns_noc_io_pcie_soc_ip.csr126207RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_0_SETns_noc_io_pcie_soc_ip.csr126217UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_1_SETns_noc_io_pcie_soc_ip.csr126229CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_1_SETns_noc_io_pcie_soc_ip.csr126243CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_1_SETns_noc_io_pcie_soc_ip.csr126258VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_1_SETns_noc_io_pcie_soc_ip.csr126269RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_1_SETns_noc_io_pcie_soc_ip.csr126279UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_2_SETns_noc_io_pcie_soc_ip.csr126291CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_2_SETns_noc_io_pcie_soc_ip.csr126305CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_2_SETns_noc_io_pcie_soc_ip.csr126320VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_2_SETns_noc_io_pcie_soc_ip.csr126331RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_2_SETns_noc_io_pcie_soc_ip.csr126341UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CF_3_SETns_noc_io_pcie_soc_ip.csr126353CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_CE_3_SETns_noc_io_pcie_soc_ip.csr126367CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_VB_3_SETns_noc_io_pcie_soc_ip.csr126382VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_RSV_3_SETns_noc_io_pcie_soc_ip.csr126393RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_S_UNSD_3_SETns_noc_io_pcie_soc_ip.csr126403UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_wrouter_0_6_6_rovcs_wPCIE_NOC_ROUTER_0_6_6_ROVCS_W_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_W_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr126665R0_6 register rovcs_w0x3C058R0x00000101Pcie_noc_router_0_6_6_rovcs_wThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_0_SETns_noc_io_pcie_soc_ip.csr126428CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_0_SETns_noc_io_pcie_soc_ip.csr126442CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_0_SETns_noc_io_pcie_soc_ip.csr126457VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_0_SETns_noc_io_pcie_soc_ip.csr126468RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_0_SETns_noc_io_pcie_soc_ip.csr126478UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_1_SETns_noc_io_pcie_soc_ip.csr126490CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_1_SETns_noc_io_pcie_soc_ip.csr126504CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_1_SETns_noc_io_pcie_soc_ip.csr126519VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_1_SETns_noc_io_pcie_soc_ip.csr126530RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_1_SETns_noc_io_pcie_soc_ip.csr126540UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_2_SETns_noc_io_pcie_soc_ip.csr126552CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_2_SETns_noc_io_pcie_soc_ip.csr126566CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_2_SETns_noc_io_pcie_soc_ip.csr126581VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_2_SETns_noc_io_pcie_soc_ip.csr126592RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_2_SETns_noc_io_pcie_soc_ip.csr126602UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CF_3_SETns_noc_io_pcie_soc_ip.csr126614CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_CE_3_SETns_noc_io_pcie_soc_ip.csr126628CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_VB_3_SETns_noc_io_pcie_soc_ip.csr126643VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_RSV_3_SETns_noc_io_pcie_soc_ip.csr126654RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_W_UNSD_3_SETns_noc_io_pcie_soc_ip.csr126664UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_nrouter_0_6_6_rovcs_nPCIE_NOC_ROUTER_0_6_6_ROVCS_N_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_N_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_N_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr126926R0_6 register rovcs_n0x3C060R0x00000001Pcie_noc_router_0_6_6_rovcs_nThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_0_SETns_noc_io_pcie_soc_ip.csr126689CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_0_SETns_noc_io_pcie_soc_ip.csr126703CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_0_SETns_noc_io_pcie_soc_ip.csr126718VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_0_SETns_noc_io_pcie_soc_ip.csr126729RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_0_SETns_noc_io_pcie_soc_ip.csr126739UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_1_SETns_noc_io_pcie_soc_ip.csr126751CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_1_SETns_noc_io_pcie_soc_ip.csr126765CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_1_SETns_noc_io_pcie_soc_ip.csr126780VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_1_SETns_noc_io_pcie_soc_ip.csr126791RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_1_SETns_noc_io_pcie_soc_ip.csr126801UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_2_SETns_noc_io_pcie_soc_ip.csr126813CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_2_SETns_noc_io_pcie_soc_ip.csr126827CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_2_SETns_noc_io_pcie_soc_ip.csr126842VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_2_SETns_noc_io_pcie_soc_ip.csr126853RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_2_SETns_noc_io_pcie_soc_ip.csr126863UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CF_3_SETns_noc_io_pcie_soc_ip.csr126875CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_CE_3_SETns_noc_io_pcie_soc_ip.csr126889CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_VB_3_SETns_noc_io_pcie_soc_ip.csr126904VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_RSV_3_SETns_noc_io_pcie_soc_ip.csr126915RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_N_UNSD_3_SETns_noc_io_pcie_soc_ip.csr126925UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_irouter_0_6_6_rovcs_iPCIE_NOC_ROUTER_0_6_6_ROVCS_I_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_I_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr127187R0_6 register rovcs_i0x3C068R0x00000001Pcie_noc_router_0_6_6_rovcs_iThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_0_SETns_noc_io_pcie_soc_ip.csr126950CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_0_SETns_noc_io_pcie_soc_ip.csr126964CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_0_SETns_noc_io_pcie_soc_ip.csr126979VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_0_SETns_noc_io_pcie_soc_ip.csr126990RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_0_SETns_noc_io_pcie_soc_ip.csr127000UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_1_SETns_noc_io_pcie_soc_ip.csr127012CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_1_SETns_noc_io_pcie_soc_ip.csr127026CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_1_SETns_noc_io_pcie_soc_ip.csr127041VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_1_SETns_noc_io_pcie_soc_ip.csr127052RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_1_SETns_noc_io_pcie_soc_ip.csr127062UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_2_SETns_noc_io_pcie_soc_ip.csr127074CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_2_SETns_noc_io_pcie_soc_ip.csr127088CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_2_SETns_noc_io_pcie_soc_ip.csr127103VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_2_SETns_noc_io_pcie_soc_ip.csr127114RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_2_SETns_noc_io_pcie_soc_ip.csr127124UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CF_3_SETns_noc_io_pcie_soc_ip.csr127136CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_CE_3_SETns_noc_io_pcie_soc_ip.csr127150CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_VB_3_SETns_noc_io_pcie_soc_ip.csr127165VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_RSV_3_SETns_noc_io_pcie_soc_ip.csr127176RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_I_UNSD_3_SETns_noc_io_pcie_soc_ip.csr127186UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_jrouter_0_6_6_rovcs_jPCIE_NOC_ROUTER_0_6_6_ROVCS_J_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_J_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr127448R0_6 register rovcs_j0x3C070R0x00000001Pcie_noc_router_0_6_6_rovcs_jThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_0_SETns_noc_io_pcie_soc_ip.csr127211CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_0_SETns_noc_io_pcie_soc_ip.csr127225CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_0_SETns_noc_io_pcie_soc_ip.csr127240VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_0_SETns_noc_io_pcie_soc_ip.csr127251RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_0_SETns_noc_io_pcie_soc_ip.csr127261UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_1_SETns_noc_io_pcie_soc_ip.csr127273CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_1_SETns_noc_io_pcie_soc_ip.csr127287CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_1_SETns_noc_io_pcie_soc_ip.csr127302VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_1_SETns_noc_io_pcie_soc_ip.csr127313RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_1_SETns_noc_io_pcie_soc_ip.csr127323UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_2_SETns_noc_io_pcie_soc_ip.csr127335CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_2_SETns_noc_io_pcie_soc_ip.csr127349CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_2_SETns_noc_io_pcie_soc_ip.csr127364VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_2_SETns_noc_io_pcie_soc_ip.csr127375RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_2_SETns_noc_io_pcie_soc_ip.csr127385UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CF_3_SETns_noc_io_pcie_soc_ip.csr127397CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_CE_3_SETns_noc_io_pcie_soc_ip.csr127411CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_VB_3_SETns_noc_io_pcie_soc_ip.csr127426VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_RSV_3_SETns_noc_io_pcie_soc_ip.csr127437RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_J_UNSD_3_SETns_noc_io_pcie_soc_ip.csr127447UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rovcs_krouter_0_6_6_rovcs_kPCIE_NOC_ROUTER_0_6_6_ROVCS_K_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROVCS_K_OFFSETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr127709R0_6 register rovcs_k0x3C078R0x00000001Pcie_noc_router_0_6_6_rovcs_kThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_0_SETns_noc_io_pcie_soc_ip.csr127472CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_0_SETns_noc_io_pcie_soc_ip.csr127486CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_0_SETns_noc_io_pcie_soc_ip.csr127501VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_0_SETns_noc_io_pcie_soc_ip.csr127512RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_0_SETns_noc_io_pcie_soc_ip.csr127522UNSD_0740x0RCF_1PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_1_SETns_noc_io_pcie_soc_ip.csr127534CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_1_SETns_noc_io_pcie_soc_ip.csr127548CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_1_SETns_noc_io_pcie_soc_ip.csr127563VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_1_SETns_noc_io_pcie_soc_ip.csr127574RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_1_SETns_noc_io_pcie_soc_ip.csr127584UNSD_115120x0RCF_2PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_2_SETns_noc_io_pcie_soc_ip.csr127596CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_2_SETns_noc_io_pcie_soc_ip.csr127610CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_2_SETns_noc_io_pcie_soc_ip.csr127625VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_2_SETns_noc_io_pcie_soc_ip.csr127636RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_2_SETns_noc_io_pcie_soc_ip.csr127646UNSD_223200x0RCF_3PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CF_3_SETns_noc_io_pcie_soc_ip.csr127658CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_CE_3_SETns_noc_io_pcie_soc_ip.csr127672CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_VB_3_SETns_noc_io_pcie_soc_ip.csr127687VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_RSV_3_SETns_noc_io_pcie_soc_ip.csr127698RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_WIDTHPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_MSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_LSBPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_RANGEPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_RESETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_GETPCIE_NOC_ROUTER_0_6_6_ROVCS_K_UNSD_3_SETns_noc_io_pcie_soc_ip.csr127708UNSD_331280x0Rregisterpcie_noc.router_0_6_6_rerouter_0_6_6_rePCIE_NOC_ROUTER_0_6_6_RE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RE_OFFSETPCIE_NOC_ROUTER_0_6_6_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr127883R0_6 register re0x3C080R/W0x00000000Pcie_noc_router_0_6_6_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_0_6_6_RE_OVFI_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_OVFI_MSBPCIE_NOC_ROUTER_0_6_6_RE_OVFI_LSBPCIE_NOC_ROUTER_0_6_6_RE_OVFI_RANGEPCIE_NOC_ROUTER_0_6_6_RE_OVFI_RESETPCIE_NOC_ROUTER_0_6_6_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_OVFI_GETPCIE_NOC_ROUTER_0_6_6_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr127735OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_0_6_6_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr127746CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_0_6_6_RE_OVFO_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_OVFO_MSBPCIE_NOC_ROUTER_0_6_6_RE_OVFO_LSBPCIE_NOC_ROUTER_0_6_6_RE_OVFO_RANGEPCIE_NOC_ROUTER_0_6_6_RE_OVFO_RESETPCIE_NOC_ROUTER_0_6_6_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_OVFO_GETPCIE_NOC_ROUTER_0_6_6_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr127760OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_0_6_6_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr127771UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_0_6_6_RE_PGE_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_PGE_MSBPCIE_NOC_ROUTER_0_6_6_RE_PGE_LSBPCIE_NOC_ROUTER_0_6_6_RE_PGE_RANGEPCIE_NOC_ROUTER_0_6_6_RE_PGE_RESETPCIE_NOC_ROUTER_0_6_6_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_PGE_GETPCIE_NOC_ROUTER_0_6_6_RE_PGE_SETns_noc_io_pcie_soc_ip.csr127783PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_0_6_6_RE_NLU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_NLU_MSBPCIE_NOC_ROUTER_0_6_6_RE_NLU_LSBPCIE_NOC_ROUTER_0_6_6_RE_NLU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_NLU_RESETPCIE_NOC_ROUTER_0_6_6_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_NLU_GETPCIE_NOC_ROUTER_0_6_6_RE_NLU_SETns_noc_io_pcie_soc_ip.csr127794NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_0_6_6_RE_ELU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_ELU_MSBPCIE_NOC_ROUTER_0_6_6_RE_ELU_LSBPCIE_NOC_ROUTER_0_6_6_RE_ELU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_ELU_RESETPCIE_NOC_ROUTER_0_6_6_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_ELU_GETPCIE_NOC_ROUTER_0_6_6_RE_ELU_SETns_noc_io_pcie_soc_ip.csr127805ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_0_6_6_RE_WLU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_WLU_MSBPCIE_NOC_ROUTER_0_6_6_RE_WLU_LSBPCIE_NOC_ROUTER_0_6_6_RE_WLU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_WLU_RESETPCIE_NOC_ROUTER_0_6_6_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_WLU_GETPCIE_NOC_ROUTER_0_6_6_RE_WLU_SETns_noc_io_pcie_soc_ip.csr127816WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_0_6_6_RE_SLU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_SLU_MSBPCIE_NOC_ROUTER_0_6_6_RE_SLU_LSBPCIE_NOC_ROUTER_0_6_6_RE_SLU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_SLU_RESETPCIE_NOC_ROUTER_0_6_6_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_SLU_GETPCIE_NOC_ROUTER_0_6_6_RE_SLU_SETns_noc_io_pcie_soc_ip.csr127827SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_0_6_6_RE_HLU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_HLU_MSBPCIE_NOC_ROUTER_0_6_6_RE_HLU_LSBPCIE_NOC_ROUTER_0_6_6_RE_HLU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_HLU_RESETPCIE_NOC_ROUTER_0_6_6_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_HLU_GETPCIE_NOC_ROUTER_0_6_6_RE_HLU_SETns_noc_io_pcie_soc_ip.csr127838HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_0_6_6_RE_ILU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_ILU_MSBPCIE_NOC_ROUTER_0_6_6_RE_ILU_LSBPCIE_NOC_ROUTER_0_6_6_RE_ILU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_ILU_RESETPCIE_NOC_ROUTER_0_6_6_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_ILU_GETPCIE_NOC_ROUTER_0_6_6_RE_ILU_SETns_noc_io_pcie_soc_ip.csr127849ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_0_6_6_RE_JLU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_JLU_MSBPCIE_NOC_ROUTER_0_6_6_RE_JLU_LSBPCIE_NOC_ROUTER_0_6_6_RE_JLU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_JLU_RESETPCIE_NOC_ROUTER_0_6_6_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_JLU_GETPCIE_NOC_ROUTER_0_6_6_RE_JLU_SETns_noc_io_pcie_soc_ip.csr127860JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_0_6_6_RE_KLU_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_KLU_MSBPCIE_NOC_ROUTER_0_6_6_RE_KLU_LSBPCIE_NOC_ROUTER_0_6_6_RE_KLU_RANGEPCIE_NOC_ROUTER_0_6_6_RE_KLU_RESETPCIE_NOC_ROUTER_0_6_6_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_KLU_GETPCIE_NOC_ROUTER_0_6_6_RE_KLU_SETns_noc_io_pcie_soc_ip.csr127871KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_0_6_6_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr127882UNSD_31_1431170x0000Rregisterpcie_noc.router_0_6_6_remrouter_0_6_6_remPCIE_NOC_ROUTER_0_6_6_REM_ADDRESSPCIE_NOC_ROUTER_0_6_6_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_REM_OFFSETPCIE_NOC_ROUTER_0_6_6_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128056R0_6 register rem0x3C088R/W0x0001fe00Pcie_noc_router_0_6_6_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_MSBPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_LSBPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_RANGEPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_RESETPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_GETPCIE_NOC_ROUTER_0_6_6_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr127909OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_0_6_6_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr127920CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_MSBPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_LSBPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_RANGEPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_RESETPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_GETPCIE_NOC_ROUTER_0_6_6_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr127934OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_0_6_6_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr127945UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_0_6_6_REM_PGM_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_PGM_MSBPCIE_NOC_ROUTER_0_6_6_REM_PGM_LSBPCIE_NOC_ROUTER_0_6_6_REM_PGM_RANGEPCIE_NOC_ROUTER_0_6_6_REM_PGM_RESETPCIE_NOC_ROUTER_0_6_6_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_PGM_GETPCIE_NOC_ROUTER_0_6_6_REM_PGM_SETns_noc_io_pcie_soc_ip.csr127956PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_0_6_6_REM_MN_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MN_MSBPCIE_NOC_ROUTER_0_6_6_REM_MN_LSBPCIE_NOC_ROUTER_0_6_6_REM_MN_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MN_RESETPCIE_NOC_ROUTER_0_6_6_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MN_GETPCIE_NOC_ROUTER_0_6_6_REM_MN_SETns_noc_io_pcie_soc_ip.csr127967MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_0_6_6_REM_ME_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_ME_MSBPCIE_NOC_ROUTER_0_6_6_REM_ME_LSBPCIE_NOC_ROUTER_0_6_6_REM_ME_RANGEPCIE_NOC_ROUTER_0_6_6_REM_ME_RESETPCIE_NOC_ROUTER_0_6_6_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_ME_GETPCIE_NOC_ROUTER_0_6_6_REM_ME_SETns_noc_io_pcie_soc_ip.csr127978ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_0_6_6_REM_MW_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MW_MSBPCIE_NOC_ROUTER_0_6_6_REM_MW_LSBPCIE_NOC_ROUTER_0_6_6_REM_MW_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MW_RESETPCIE_NOC_ROUTER_0_6_6_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MW_GETPCIE_NOC_ROUTER_0_6_6_REM_MW_SETns_noc_io_pcie_soc_ip.csr127989MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_0_6_6_REM_MS_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MS_MSBPCIE_NOC_ROUTER_0_6_6_REM_MS_LSBPCIE_NOC_ROUTER_0_6_6_REM_MS_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MS_RESETPCIE_NOC_ROUTER_0_6_6_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MS_GETPCIE_NOC_ROUTER_0_6_6_REM_MS_SETns_noc_io_pcie_soc_ip.csr128000MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_0_6_6_REM_MH_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MH_MSBPCIE_NOC_ROUTER_0_6_6_REM_MH_LSBPCIE_NOC_ROUTER_0_6_6_REM_MH_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MH_RESETPCIE_NOC_ROUTER_0_6_6_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MH_GETPCIE_NOC_ROUTER_0_6_6_REM_MH_SETns_noc_io_pcie_soc_ip.csr128011MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_0_6_6_REM_MI_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MI_MSBPCIE_NOC_ROUTER_0_6_6_REM_MI_LSBPCIE_NOC_ROUTER_0_6_6_REM_MI_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MI_RESETPCIE_NOC_ROUTER_0_6_6_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MI_GETPCIE_NOC_ROUTER_0_6_6_REM_MI_SETns_noc_io_pcie_soc_ip.csr128022MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_0_6_6_REM_MJ_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MJ_MSBPCIE_NOC_ROUTER_0_6_6_REM_MJ_LSBPCIE_NOC_ROUTER_0_6_6_REM_MJ_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MJ_RESETPCIE_NOC_ROUTER_0_6_6_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MJ_GETPCIE_NOC_ROUTER_0_6_6_REM_MJ_SETns_noc_io_pcie_soc_ip.csr128033MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_0_6_6_REM_MK_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_MK_MSBPCIE_NOC_ROUTER_0_6_6_REM_MK_LSBPCIE_NOC_ROUTER_0_6_6_REM_MK_RANGEPCIE_NOC_ROUTER_0_6_6_REM_MK_RESETPCIE_NOC_ROUTER_0_6_6_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_MK_GETPCIE_NOC_ROUTER_0_6_6_REM_MK_SETns_noc_io_pcie_soc_ip.csr128044MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_0_6_6_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr128055UNSD_31_1431170x0000Rregisterpcie_noc.router_0_6_6_reccrouter_0_6_6_reccPCIE_NOC_ROUTER_0_6_6_RECC_ADDRESSPCIE_NOC_ROUTER_0_6_6_RECC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RECC_OFFSETPCIE_NOC_ROUTER_0_6_6_RECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128141R0_6 register recc0x3C090R/W0x00000000Pcie_noc_router_0_6_6_reccThis register is used to select which hardware events will increment the event counter.falsefalsefalsefalseIVCPCIE_NOC_ROUTER_0_6_6_RECC_IVC_WIDTHPCIE_NOC_ROUTER_0_6_6_RECC_IVC_MSBPCIE_NOC_ROUTER_0_6_6_RECC_IVC_LSBPCIE_NOC_ROUTER_0_6_6_RECC_IVC_RANGEPCIE_NOC_ROUTER_0_6_6_RECC_IVC_RESETPCIE_NOC_ROUTER_0_6_6_RECC_IVC_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RECC_IVC_GETPCIE_NOC_ROUTER_0_6_6_RECC_IVC_SETns_noc_io_pcie_soc_ip.csr128077IVC11: Input VC 310: Input VC 201: Input VC 100: Input VC 0100x0R/WUNSD_3_2PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_WIDTHPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_MSBPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_LSBPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_RANGEPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_RESETPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_GETPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_3_2_SETns_noc_io_pcie_soc_ip.csr128088UNSD_3_2320x0RINPPCIE_NOC_ROUTER_0_6_6_RECC_INP_WIDTHPCIE_NOC_ROUTER_0_6_6_RECC_INP_MSBPCIE_NOC_ROUTER_0_6_6_RECC_INP_LSBPCIE_NOC_ROUTER_0_6_6_RECC_INP_RANGEPCIE_NOC_ROUTER_0_6_6_RECC_INP_RESETPCIE_NOC_ROUTER_0_6_6_RECC_INP_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RECC_INP_GETPCIE_NOC_ROUTER_0_6_6_RECC_INP_SETns_noc_io_pcie_soc_ip.csr128099INPInput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_GETPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr128110UNSD_7_7770x0REVTPCIE_NOC_ROUTER_0_6_6_RECC_EVT_WIDTHPCIE_NOC_ROUTER_0_6_6_RECC_EVT_MSBPCIE_NOC_ROUTER_0_6_6_RECC_EVT_LSBPCIE_NOC_ROUTER_0_6_6_RECC_EVT_RANGEPCIE_NOC_ROUTER_0_6_6_RECC_EVT_RESETPCIE_NOC_ROUTER_0_6_6_RECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RECC_EVT_GETPCIE_NOC_ROUTER_0_6_6_RECC_EVT_SETns_noc_io_pcie_soc_ip.csr128129EVT11: Generates count event when VC has valid data, but is stalled10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port00: Disable980x0R/WUNSD_31_10PCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_WIDTHPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_MSBPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_LSBPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_RANGEPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_RESETPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_GETPCIE_NOC_ROUTER_0_6_6_RECC_UNSD_31_10_SETns_noc_io_pcie_soc_ip.csr128140UNSD_31_1031100x000000Rregisterpcie_noc.router_0_6_6_recrouter_0_6_6_recPCIE_NOC_ROUTER_0_6_6_REC_ADDRESSPCIE_NOC_ROUTER_0_6_6_REC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_REC_OFFSETPCIE_NOC_ROUTER_0_6_6_REC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128166R0_6 register rec0x3C098R/W0x00000000Pcie_noc_router_0_6_6_recThis register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_GETPCIE_NOC_ROUTER_0_6_6_REC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr128165EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_0_6_6_idrouter_0_6_6_idPCIE_NOC_ROUTER_0_6_6_ID_ADDRESSPCIE_NOC_ROUTER_0_6_6_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ID_OFFSETPCIE_NOC_ROUTER_0_6_6_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128235R0_6 register id0x3C0A0R0x010000c0Pcie_noc_router_0_6_6_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_0_6_6_ID_LAYER_WIDTHPCIE_NOC_ROUTER_0_6_6_ID_LAYER_MSBPCIE_NOC_ROUTER_0_6_6_ID_LAYER_LSBPCIE_NOC_ROUTER_0_6_6_ID_LAYER_RANGEPCIE_NOC_ROUTER_0_6_6_ID_LAYER_RESETPCIE_NOC_ROUTER_0_6_6_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ID_LAYER_GETPCIE_NOC_ROUTER_0_6_6_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr128191LAYER5-bit identifier of the NoC layer on which this router is located400x00RPOSPCIE_NOC_ROUTER_0_6_6_ID_POS_WIDTHPCIE_NOC_ROUTER_0_6_6_ID_POS_MSBPCIE_NOC_ROUTER_0_6_6_ID_POS_LSBPCIE_NOC_ROUTER_0_6_6_ID_POS_RANGEPCIE_NOC_ROUTER_0_6_6_ID_POS_RESETPCIE_NOC_ROUTER_0_6_6_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ID_POS_GETPCIE_NOC_ROUTER_0_6_6_ID_POS_SETns_noc_io_pcie_soc_ip.csr128202POS16-bit position ID of this router in the NoC2050x0006RZEROPCIE_NOC_ROUTER_0_6_6_ID_ZERO_WIDTHPCIE_NOC_ROUTER_0_6_6_ID_ZERO_MSBPCIE_NOC_ROUTER_0_6_6_ID_ZERO_LSBPCIE_NOC_ROUTER_0_6_6_ID_ZERO_RANGEPCIE_NOC_ROUTER_0_6_6_ID_ZERO_RESETPCIE_NOC_ROUTER_0_6_6_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ID_ZERO_GETPCIE_NOC_ROUTER_0_6_6_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr128213ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_0_6_6_ID_ONE_WIDTHPCIE_NOC_ROUTER_0_6_6_ID_ONE_MSBPCIE_NOC_ROUTER_0_6_6_ID_ONE_LSBPCIE_NOC_ROUTER_0_6_6_ID_ONE_RANGEPCIE_NOC_ROUTER_0_6_6_ID_ONE_RESETPCIE_NOC_ROUTER_0_6_6_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ID_ONE_GETPCIE_NOC_ROUTER_0_6_6_ID_ONE_SETns_noc_io_pcie_soc_ip.csr128224ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_0_6_6_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr128234UNSD_31_2531250x00Rregisterpcie_noc.router_0_6_6_rcgcrouter_0_6_6_rcgcPCIE_NOC_ROUTER_0_6_6_RCGC_ADDRESSPCIE_NOC_ROUTER_0_6_6_RCGC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RCGC_OFFSETPCIE_NOC_ROUTER_0_6_6_RCGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128261R0_6 register rcgc0x3C0A8R/W0x00000064Pcie_noc_router_0_6_6_rcgcProgrammable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_GETPCIE_NOC_ROUTER_0_6_6_RCGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr128260HYSTERESIS_COUNTERHysteresis counter3100x00000064R/Wregisterpcie_noc.router_0_6_6_rcgorouter_0_6_6_rcgoPCIE_NOC_ROUTER_0_6_6_RCGO_ADDRESSPCIE_NOC_ROUTER_0_6_6_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_RCGO_OFFSETPCIE_NOC_ROUTER_0_6_6_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128300R0_6 register rcgo0x3C0B0R/W0x00000000Pcie_noc_router_0_6_6_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_MSBPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_LSBPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_RANGEPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_RESETPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_GETPCIE_NOC_ROUTER_0_6_6_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr128288FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_0_6_6_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr128299UNSD_31_13110x00000000Rregisterpcie_noc.router_0_6_6_p0_rperrrouter_0_6_6_p0_rperrPCIE_NOC_ROUTER_0_6_6_P0_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P0_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P0_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128591R0_6 register p0_rperr0x3C0B8R/W0x00000000Pcie_noc_router_0_6_6_p0_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_SETns_noc_io_pcie_soc_ip.csr128343D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr128354SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr128365PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr128376RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr128387CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr128398UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr128409D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr128420SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr128432PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr128443RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr128455D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr128467SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr128480PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr128492RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr128504D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr128516SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr128529PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr128541RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr128553D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr128565SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr128578PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr128590RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p1_rperrrouter_0_6_6_p1_rperrPCIE_NOC_ROUTER_0_6_6_P1_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P1_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P1_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr128878R0_6 register p1_rperr0x3C0C0R/W0x00000000Pcie_noc_router_0_6_6_p1_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_SETns_noc_io_pcie_soc_ip.csr128634D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr128645SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr128656PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr128667RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr128678CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr128689UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr128700D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr128711SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr128723PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr128734RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr128745D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr128756SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr128768PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr128779RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr128791D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr128803SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr128816PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr128828RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr128840D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr128852SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr128865PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr128877RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p2_rperrrouter_0_6_6_p2_rperrPCIE_NOC_ROUTER_0_6_6_P2_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P2_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P2_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr129169R0_6 register p2_rperr0x3C0C8R/W0x00000000Pcie_noc_router_0_6_6_p2_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_SETns_noc_io_pcie_soc_ip.csr128921D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr128932SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr128943PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr128954RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr128965CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr128976UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr128987D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr128998SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr129010PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr129021RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr129033D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr129045SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr129058PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr129070RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr129082D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr129094SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr129107PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr129119RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr129131D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr129143SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr129156PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr129168RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p3_rperrrouter_0_6_6_p3_rperrPCIE_NOC_ROUTER_0_6_6_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P3_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr129460R0_6 register p3_rperr0x3C0D0R/W0x00000000Pcie_noc_router_0_6_6_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr129212D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr129223SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr129234PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr129245RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr129256CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr129267UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr129278D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr129289SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr129301PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr129312RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr129324D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr129336SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr129349PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr129361RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr129373D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr129385SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr129398PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr129410RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr129422D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr129434SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr129447PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr129459RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p4_rperrrouter_0_6_6_p4_rperrPCIE_NOC_ROUTER_0_6_6_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P4_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr129751R0_6 register p4_rperr0x3C0D8R/W0x00000000Pcie_noc_router_0_6_6_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr129503D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr129514SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr129525PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr129536RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr129547CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr129558UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr129570D_01'b1: Parity Error in VC 0 Buffer Data16160x0RSB_0PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr129582SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0RPK_0PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr129595PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0RRI_0PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr129607RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0RD_1PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr129618D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr129629SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr129641PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr129652RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr129664D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr129676SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr129689PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr129701RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr129713D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr129725SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr129738PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr129750RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p5_rperrrouter_0_6_6_p5_rperrPCIE_NOC_ROUTER_0_6_6_P5_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P5_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P5_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr130042R0_6 register p5_rperr0x3C0E0R/W0x00000000Pcie_noc_router_0_6_6_p5_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_SETns_noc_io_pcie_soc_ip.csr129794D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr129805SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr129816PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr129827RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr129838CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr129849UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr129861D_01'b1: Parity Error in VC 0 Buffer Data16160x0RSB_0PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr129873SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0RPK_0PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr129886PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0RRI_0PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr129898RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0RD_1PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr129909D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr129920SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr129932PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr129943RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr129955D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr129967SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr129980PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr129992RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr130004D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr130016SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr130029PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr130041RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p6_rperrrouter_0_6_6_p6_rperrPCIE_NOC_ROUTER_0_6_6_P6_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P6_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P6_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr130333R0_6 register p6_rperr0x3C0E8R/W0x00000000Pcie_noc_router_0_6_6_p6_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_SETns_noc_io_pcie_soc_ip.csr130085D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr130096SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr130107PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr130118RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr130129CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr130140UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr130151D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr130162SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr130174PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr130185RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr130197D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr130209SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr130222PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr130234RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr130246D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr130258SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr130271PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr130283RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr130295D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr130307SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr130320PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr130332RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p7_rperrrouter_0_6_6_p7_rperrPCIE_NOC_ROUTER_0_6_6_P7_RPERR_ADDRESSPCIE_NOC_ROUTER_0_6_6_P7_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P7_RPERR_OFFSETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr130624R0_6 register p7_rperr0x3C0F0R/W0x00000000Pcie_noc_router_0_6_6_p7_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_SETns_noc_io_pcie_soc_ip.csr130376D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr130387SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr130398PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr130409RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr130420CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr130431UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr130442D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr130453SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr130465PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr130476RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr130488D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr130500SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr130513PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr130525RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr130537D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr130549SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr130562PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr130574RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr130586D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr130598SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr130611PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr130623RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_0_6_6_p0_rperrmrouter_0_6_6_p0_rperrmPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr130882R0_6 register p0_rperrm0x3C0F8R/W0x00000000Pcie_noc_router_0_6_6_p0_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr130646DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr130657SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr130668PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr130679RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr130690CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr130701UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr130712D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr130723SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr130735PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr130746RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr130757D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr130768SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr130780PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr130791RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr130802D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr130813SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr130825PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr130836RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr130847D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr130858SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr130870PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P0_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr130881RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p1_rperrmrouter_0_6_6_p1_rperrmPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr131140R0_6 register p1_rperrm0x3C100R/W0x00000000Pcie_noc_router_0_6_6_p1_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr130904DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr130915SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr130926PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr130937RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr130948CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr130959UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr130970D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr130981SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr130993PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr131004RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr131015D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr131026SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr131038PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr131049RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr131060D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr131071SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr131083PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr131094RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr131105D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr131116SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr131128PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P1_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr131139RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p2_rperrmrouter_0_6_6_p2_rperrmPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr131398R0_6 register p2_rperrm0x3C108R/W0x00000000Pcie_noc_router_0_6_6_p2_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr131162DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr131173SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr131184PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr131195RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr131206CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr131217UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr131228D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr131239SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr131251PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr131262RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr131273D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr131284SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr131296PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr131307RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr131318D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr131329SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr131341PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr131352RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr131363D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr131374SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr131386PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P2_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr131397RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p3_rperrmrouter_0_6_6_p3_rperrmPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr131656R0_6 register p3_rperrm0x3C110R/W0x00000000Pcie_noc_router_0_6_6_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr131420DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr131431SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr131442PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr131453RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr131464CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr131475UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr131486D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr131497SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr131509PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr131520RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr131531D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr131542SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr131554PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr131565RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr131576D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr131587SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr131599PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr131610RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr131621D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr131632SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr131644PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr131655RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p4_rperrmrouter_0_6_6_p4_rperrmPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr131914R0_6 register p4_rperrm0x3C118R/W0x00000000Pcie_noc_router_0_6_6_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr131678DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr131689SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr131700PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr131711RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr131722CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr131733UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr131744D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr131755SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr131767PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr131778RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr131789D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr131800SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr131812PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr131823RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr131834D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr131845SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr131857PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr131868RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr131879D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr131890SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr131902PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr131913RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p5_rperrmrouter_0_6_6_p5_rperrmPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr132172R0_6 register p5_rperrm0x3C120R/W0x00000000Pcie_noc_router_0_6_6_p5_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr131936DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr131947SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr131958PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr131969RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr131980CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr131991UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr132002D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr132013SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr132025PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr132036RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr132047D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr132058SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr132070PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr132081RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr132092D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr132103SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr132115PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr132126RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr132137D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr132148SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr132160PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P5_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr132171RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p6_rperrmrouter_0_6_6_p6_rperrmPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr132430R0_6 register p6_rperrm0x3C128R/W0x00000000Pcie_noc_router_0_6_6_p6_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr132194DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr132205SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr132216PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr132227RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr132238CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr132249UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr132260D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr132271SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr132283PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr132294RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr132305D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr132316SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr132328PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr132339RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr132350D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr132361SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr132373PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr132384RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr132395D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr132406SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr132418PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P6_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr132429RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_p7_rperrmrouter_0_6_6_p7_rperrmPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_ADDRESSPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_OFFSETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr132688R0_6 register p7_rperrm0x3C130R/W0x00000000Pcie_noc_router_0_6_6_p7_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr132452DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr132463SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr132474PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr132485RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr132496CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr132507UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr132518D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr132529SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr132541PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr132552RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr132563D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr132574SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr132586PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr132597RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr132608D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr132619SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr132631PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr132642RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr132653D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr132664SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr132676PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_GETPCIE_NOC_ROUTER_0_6_6_P7_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr132687RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_0_6_6_roeccrouter_0_6_6_roeccPCIE_NOC_ROUTER_0_6_6_ROECC_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROECC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROECC_OFFSETPCIE_NOC_ROUTER_0_6_6_ROECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr132761R0_6 register roecc0x3C138R/W0x00000000Pcie_noc_router_0_6_6_roeccThis register is used to select which hardware events will increment the output event counter.falsefalsefalsefalseOVCPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_WIDTHPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_MSBPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_LSBPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_RANGEPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_RESETPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_GETPCIE_NOC_ROUTER_0_6_6_ROECC_OVC_SETns_noc_io_pcie_soc_ip.csr132706OVCBit map to select output VCs to monitor events on300x0R/WOPPCIE_NOC_ROUTER_0_6_6_ROECC_OP_WIDTHPCIE_NOC_ROUTER_0_6_6_ROECC_OP_MSBPCIE_NOC_ROUTER_0_6_6_ROECC_OP_LSBPCIE_NOC_ROUTER_0_6_6_ROECC_OP_RANGEPCIE_NOC_ROUTER_0_6_6_ROECC_OP_RESETPCIE_NOC_ROUTER_0_6_6_ROECC_OP_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROECC_OP_GETPCIE_NOC_ROUTER_0_6_6_ROECC_OP_SETns_noc_io_pcie_soc_ip.csr132717OPOutput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_GETPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr132728UNSD_7_7770x0REVTPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_WIDTHPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_MSBPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_LSBPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_RANGEPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_RESETPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_GETPCIE_NOC_ROUTER_0_6_6_ROECC_EVT_SETns_noc_io_pcie_soc_ip.csr132749EVT100: Port stalled. Input flits are available for the port, but no output VC has credit011: Generates count event when flits are available to be sent to output VC, but the VC has no credit010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port000: Disable1080x0R/WUNSD_31_11PCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_WIDTHPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_MSBPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_LSBPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_RANGEPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_RESETPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_GETPCIE_NOC_ROUTER_0_6_6_ROECC_UNSD_31_11_SETns_noc_io_pcie_soc_ip.csr132760UNSD_31_1131110x000000Rregisterpcie_noc.router_0_6_6_roecrouter_0_6_6_roecPCIE_NOC_ROUTER_0_6_6_ROEC_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROEC_BYTE_ADDRESSPCIE_NOC_ROUTER_0_6_6_ROEC_OFFSETPCIE_NOC_ROUTER_0_6_6_ROEC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr132786R0_6 register roec0x3C140R/W0x00000000Pcie_noc_router_0_6_6_roecThis register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_GETPCIE_NOC_ROUTER_0_6_6_ROEC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr132785EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_1_5_5_rivcs_hrouter_1_5_5_rivcs_hPCIE_NOC_ROUTER_1_5_5_RIVCS_H_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr133115R1_5 register rivcs_h0x40000R0x00000000Pcie_noc_router_1_5_5_rivcs_hThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_0_SETns_noc_io_pcie_soc_ip.csr132811OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_0_SETns_noc_io_pcie_soc_ip.csr132825UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_0_SETns_noc_io_pcie_soc_ip.csr132841S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_0_SETns_noc_io_pcie_soc_ip.csr132855B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_0_SETns_noc_io_pcie_soc_ip.csr132866F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_0_SETns_noc_io_pcie_soc_ip.csr132877V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_1_SETns_noc_io_pcie_soc_ip.csr132890OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_1_SETns_noc_io_pcie_soc_ip.csr132904UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_1_SETns_noc_io_pcie_soc_ip.csr132920S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_1_SETns_noc_io_pcie_soc_ip.csr132934B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_1_SETns_noc_io_pcie_soc_ip.csr132945F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_1_SETns_noc_io_pcie_soc_ip.csr132956V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_2_SETns_noc_io_pcie_soc_ip.csr132969OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_2_SETns_noc_io_pcie_soc_ip.csr132983UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_2_SETns_noc_io_pcie_soc_ip.csr132999S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_2_SETns_noc_io_pcie_soc_ip.csr133013B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_2_SETns_noc_io_pcie_soc_ip.csr133024F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_2_SETns_noc_io_pcie_soc_ip.csr133035V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_OUTP_3_SETns_noc_io_pcie_soc_ip.csr133048OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_UP_3_SETns_noc_io_pcie_soc_ip.csr133062UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_S_3_SETns_noc_io_pcie_soc_ip.csr133078S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_B_3_SETns_noc_io_pcie_soc_ip.csr133092B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_F_3_SETns_noc_io_pcie_soc_ip.csr133103F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_H_V_3_SETns_noc_io_pcie_soc_ip.csr133114V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rivcs_erouter_1_5_5_rivcs_ePCIE_NOC_ROUTER_1_5_5_RIVCS_E_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr133444R1_5 register rivcs_e0x40008R0x00000000Pcie_noc_router_1_5_5_rivcs_eThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_0_SETns_noc_io_pcie_soc_ip.csr133140OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_0_SETns_noc_io_pcie_soc_ip.csr133154UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_0_SETns_noc_io_pcie_soc_ip.csr133170S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_0_SETns_noc_io_pcie_soc_ip.csr133184B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_0_SETns_noc_io_pcie_soc_ip.csr133195F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_0_SETns_noc_io_pcie_soc_ip.csr133206V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_1_SETns_noc_io_pcie_soc_ip.csr133219OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_1_SETns_noc_io_pcie_soc_ip.csr133233UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_1_SETns_noc_io_pcie_soc_ip.csr133249S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_1_SETns_noc_io_pcie_soc_ip.csr133263B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_1_SETns_noc_io_pcie_soc_ip.csr133274F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_1_SETns_noc_io_pcie_soc_ip.csr133285V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_2_SETns_noc_io_pcie_soc_ip.csr133298OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_2_SETns_noc_io_pcie_soc_ip.csr133312UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_2_SETns_noc_io_pcie_soc_ip.csr133328S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_2_SETns_noc_io_pcie_soc_ip.csr133342B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_2_SETns_noc_io_pcie_soc_ip.csr133353F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_2_SETns_noc_io_pcie_soc_ip.csr133364V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_OUTP_3_SETns_noc_io_pcie_soc_ip.csr133377OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_UP_3_SETns_noc_io_pcie_soc_ip.csr133391UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_S_3_SETns_noc_io_pcie_soc_ip.csr133407S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_B_3_SETns_noc_io_pcie_soc_ip.csr133421B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_F_3_SETns_noc_io_pcie_soc_ip.csr133432F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_E_V_3_SETns_noc_io_pcie_soc_ip.csr133443V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rivcs_srouter_1_5_5_rivcs_sPCIE_NOC_ROUTER_1_5_5_RIVCS_S_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr133773R1_5 register rivcs_s0x40010R0x00000000Pcie_noc_router_1_5_5_rivcs_sThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_0_SETns_noc_io_pcie_soc_ip.csr133469OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_0_SETns_noc_io_pcie_soc_ip.csr133483UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_0_SETns_noc_io_pcie_soc_ip.csr133499S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_0_SETns_noc_io_pcie_soc_ip.csr133513B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_0_SETns_noc_io_pcie_soc_ip.csr133524F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_0_SETns_noc_io_pcie_soc_ip.csr133535V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_1_SETns_noc_io_pcie_soc_ip.csr133548OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_1_SETns_noc_io_pcie_soc_ip.csr133562UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_1_SETns_noc_io_pcie_soc_ip.csr133578S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_1_SETns_noc_io_pcie_soc_ip.csr133592B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_1_SETns_noc_io_pcie_soc_ip.csr133603F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_1_SETns_noc_io_pcie_soc_ip.csr133614V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_2_SETns_noc_io_pcie_soc_ip.csr133627OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_2_SETns_noc_io_pcie_soc_ip.csr133641UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_2_SETns_noc_io_pcie_soc_ip.csr133657S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_2_SETns_noc_io_pcie_soc_ip.csr133671B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_2_SETns_noc_io_pcie_soc_ip.csr133682F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_2_SETns_noc_io_pcie_soc_ip.csr133693V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_OUTP_3_SETns_noc_io_pcie_soc_ip.csr133706OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_UP_3_SETns_noc_io_pcie_soc_ip.csr133720UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_S_3_SETns_noc_io_pcie_soc_ip.csr133736S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_B_3_SETns_noc_io_pcie_soc_ip.csr133750B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_F_3_SETns_noc_io_pcie_soc_ip.csr133761F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_S_V_3_SETns_noc_io_pcie_soc_ip.csr133772V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rivcs_wrouter_1_5_5_rivcs_wPCIE_NOC_ROUTER_1_5_5_RIVCS_W_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr134102R1_5 register rivcs_w0x40018R0x00000000Pcie_noc_router_1_5_5_rivcs_wThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_0_SETns_noc_io_pcie_soc_ip.csr133798OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_0_SETns_noc_io_pcie_soc_ip.csr133812UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_0_SETns_noc_io_pcie_soc_ip.csr133828S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_0_SETns_noc_io_pcie_soc_ip.csr133842B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_0_SETns_noc_io_pcie_soc_ip.csr133853F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_0_SETns_noc_io_pcie_soc_ip.csr133864V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_1_SETns_noc_io_pcie_soc_ip.csr133877OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_1_SETns_noc_io_pcie_soc_ip.csr133891UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_1_SETns_noc_io_pcie_soc_ip.csr133907S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_1_SETns_noc_io_pcie_soc_ip.csr133921B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_1_SETns_noc_io_pcie_soc_ip.csr133932F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_1_SETns_noc_io_pcie_soc_ip.csr133943V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_2_SETns_noc_io_pcie_soc_ip.csr133956OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_2_SETns_noc_io_pcie_soc_ip.csr133970UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_2_SETns_noc_io_pcie_soc_ip.csr133986S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_2_SETns_noc_io_pcie_soc_ip.csr134000B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_2_SETns_noc_io_pcie_soc_ip.csr134011F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_2_SETns_noc_io_pcie_soc_ip.csr134022V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_OUTP_3_SETns_noc_io_pcie_soc_ip.csr134035OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_UP_3_SETns_noc_io_pcie_soc_ip.csr134049UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_S_3_SETns_noc_io_pcie_soc_ip.csr134065S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_B_3_SETns_noc_io_pcie_soc_ip.csr134079B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_F_3_SETns_noc_io_pcie_soc_ip.csr134090F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_W_V_3_SETns_noc_io_pcie_soc_ip.csr134101V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rivcs_irouter_1_5_5_rivcs_iPCIE_NOC_ROUTER_1_5_5_RIVCS_I_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr134431R1_5 register rivcs_i0x40028R0x00000000Pcie_noc_router_1_5_5_rivcs_iThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_0_SETns_noc_io_pcie_soc_ip.csr134127OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_0_SETns_noc_io_pcie_soc_ip.csr134141UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_0_SETns_noc_io_pcie_soc_ip.csr134157S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_0_SETns_noc_io_pcie_soc_ip.csr134171B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_0_SETns_noc_io_pcie_soc_ip.csr134182F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_0_SETns_noc_io_pcie_soc_ip.csr134193V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_1_SETns_noc_io_pcie_soc_ip.csr134206OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_1_SETns_noc_io_pcie_soc_ip.csr134220UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_1_SETns_noc_io_pcie_soc_ip.csr134236S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_1_SETns_noc_io_pcie_soc_ip.csr134250B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_1_SETns_noc_io_pcie_soc_ip.csr134261F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_1_SETns_noc_io_pcie_soc_ip.csr134272V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_2_SETns_noc_io_pcie_soc_ip.csr134285OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_2_SETns_noc_io_pcie_soc_ip.csr134299UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_2_SETns_noc_io_pcie_soc_ip.csr134315S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_2_SETns_noc_io_pcie_soc_ip.csr134329B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_2_SETns_noc_io_pcie_soc_ip.csr134340F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_2_SETns_noc_io_pcie_soc_ip.csr134351V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_OUTP_3_SETns_noc_io_pcie_soc_ip.csr134364OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_UP_3_SETns_noc_io_pcie_soc_ip.csr134378UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_S_3_SETns_noc_io_pcie_soc_ip.csr134394S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_B_3_SETns_noc_io_pcie_soc_ip.csr134408B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_F_3_SETns_noc_io_pcie_soc_ip.csr134419F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_I_V_3_SETns_noc_io_pcie_soc_ip.csr134430V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rivcs_jrouter_1_5_5_rivcs_jPCIE_NOC_ROUTER_1_5_5_RIVCS_J_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr134760R1_5 register rivcs_j0x40030R0x00000000Pcie_noc_router_1_5_5_rivcs_jThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_0_SETns_noc_io_pcie_soc_ip.csr134456OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_0_SETns_noc_io_pcie_soc_ip.csr134470UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_0_SETns_noc_io_pcie_soc_ip.csr134486S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_0_SETns_noc_io_pcie_soc_ip.csr134500B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_0_SETns_noc_io_pcie_soc_ip.csr134511F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_0_SETns_noc_io_pcie_soc_ip.csr134522V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_1_SETns_noc_io_pcie_soc_ip.csr134535OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_1_SETns_noc_io_pcie_soc_ip.csr134549UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_1_SETns_noc_io_pcie_soc_ip.csr134565S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_1_SETns_noc_io_pcie_soc_ip.csr134579B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_1_SETns_noc_io_pcie_soc_ip.csr134590F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_1_SETns_noc_io_pcie_soc_ip.csr134601V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_2_SETns_noc_io_pcie_soc_ip.csr134614OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_2_SETns_noc_io_pcie_soc_ip.csr134628UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_2_SETns_noc_io_pcie_soc_ip.csr134644S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_2_SETns_noc_io_pcie_soc_ip.csr134658B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_2_SETns_noc_io_pcie_soc_ip.csr134669F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_2_SETns_noc_io_pcie_soc_ip.csr134680V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_OUTP_3_SETns_noc_io_pcie_soc_ip.csr134693OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_UP_3_SETns_noc_io_pcie_soc_ip.csr134707UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_S_3_SETns_noc_io_pcie_soc_ip.csr134723S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_B_3_SETns_noc_io_pcie_soc_ip.csr134737B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_F_3_SETns_noc_io_pcie_soc_ip.csr134748F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_J_V_3_SETns_noc_io_pcie_soc_ip.csr134759V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rivcs_krouter_1_5_5_rivcs_kPCIE_NOC_ROUTER_1_5_5_RIVCS_K_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OFFSETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr135089R1_5 register rivcs_k0x40038R0x00000000Pcie_noc_router_1_5_5_rivcs_kThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_0_SETns_noc_io_pcie_soc_ip.csr134785OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_0_SETns_noc_io_pcie_soc_ip.csr134799UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_0_SETns_noc_io_pcie_soc_ip.csr134815S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_0_SETns_noc_io_pcie_soc_ip.csr134829B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_0_SETns_noc_io_pcie_soc_ip.csr134840F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_0_SETns_noc_io_pcie_soc_ip.csr134851V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_1_SETns_noc_io_pcie_soc_ip.csr134864OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_1_SETns_noc_io_pcie_soc_ip.csr134878UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_1_SETns_noc_io_pcie_soc_ip.csr134894S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_1_SETns_noc_io_pcie_soc_ip.csr134908B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_1_SETns_noc_io_pcie_soc_ip.csr134919F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_1_SETns_noc_io_pcie_soc_ip.csr134930V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_2_SETns_noc_io_pcie_soc_ip.csr134943OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_2_SETns_noc_io_pcie_soc_ip.csr134957UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_2_SETns_noc_io_pcie_soc_ip.csr134973S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_2_SETns_noc_io_pcie_soc_ip.csr134987B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_2_SETns_noc_io_pcie_soc_ip.csr134998F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_2_SETns_noc_io_pcie_soc_ip.csr135009V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_OUTP_3_SETns_noc_io_pcie_soc_ip.csr135022OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_UP_3_SETns_noc_io_pcie_soc_ip.csr135036UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_S_3_SETns_noc_io_pcie_soc_ip.csr135052S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_B_3_SETns_noc_io_pcie_soc_ip.csr135066B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_F_3_SETns_noc_io_pcie_soc_ip.csr135077F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_MSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_LSBPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_RANGEPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_RESETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_GETPCIE_NOC_ROUTER_1_5_5_RIVCS_K_V_3_SETns_noc_io_pcie_soc_ip.csr135088V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_5_5_rovcs_hrouter_1_5_5_rovcs_hPCIE_NOC_ROUTER_1_5_5_ROVCS_H_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_H_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr135350R1_5 register rovcs_h0x40040R0x00000101Pcie_noc_router_1_5_5_rovcs_hThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_0_SETns_noc_io_pcie_soc_ip.csr135113CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_0_SETns_noc_io_pcie_soc_ip.csr135127CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_0_SETns_noc_io_pcie_soc_ip.csr135142VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_0_SETns_noc_io_pcie_soc_ip.csr135153RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_0_SETns_noc_io_pcie_soc_ip.csr135163UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_1_SETns_noc_io_pcie_soc_ip.csr135175CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_1_SETns_noc_io_pcie_soc_ip.csr135189CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_1_SETns_noc_io_pcie_soc_ip.csr135204VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_1_SETns_noc_io_pcie_soc_ip.csr135215RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_1_SETns_noc_io_pcie_soc_ip.csr135225UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_2_SETns_noc_io_pcie_soc_ip.csr135237CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_2_SETns_noc_io_pcie_soc_ip.csr135251CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_2_SETns_noc_io_pcie_soc_ip.csr135266VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_2_SETns_noc_io_pcie_soc_ip.csr135277RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_2_SETns_noc_io_pcie_soc_ip.csr135287UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CF_3_SETns_noc_io_pcie_soc_ip.csr135299CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_CE_3_SETns_noc_io_pcie_soc_ip.csr135313CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_VB_3_SETns_noc_io_pcie_soc_ip.csr135328VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_RSV_3_SETns_noc_io_pcie_soc_ip.csr135339RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_H_UNSD_3_SETns_noc_io_pcie_soc_ip.csr135349UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rovcs_erouter_1_5_5_rovcs_ePCIE_NOC_ROUTER_1_5_5_ROVCS_E_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_E_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr135611R1_5 register rovcs_e0x40048R0x00000001Pcie_noc_router_1_5_5_rovcs_eThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_0_SETns_noc_io_pcie_soc_ip.csr135374CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_0_SETns_noc_io_pcie_soc_ip.csr135388CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_0_SETns_noc_io_pcie_soc_ip.csr135403VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_0_SETns_noc_io_pcie_soc_ip.csr135414RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_0_SETns_noc_io_pcie_soc_ip.csr135424UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_1_SETns_noc_io_pcie_soc_ip.csr135436CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_1_SETns_noc_io_pcie_soc_ip.csr135450CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_1_SETns_noc_io_pcie_soc_ip.csr135465VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_1_SETns_noc_io_pcie_soc_ip.csr135476RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_1_SETns_noc_io_pcie_soc_ip.csr135486UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_2_SETns_noc_io_pcie_soc_ip.csr135498CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_2_SETns_noc_io_pcie_soc_ip.csr135512CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_2_SETns_noc_io_pcie_soc_ip.csr135527VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_2_SETns_noc_io_pcie_soc_ip.csr135538RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_2_SETns_noc_io_pcie_soc_ip.csr135548UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CF_3_SETns_noc_io_pcie_soc_ip.csr135560CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_CE_3_SETns_noc_io_pcie_soc_ip.csr135574CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_VB_3_SETns_noc_io_pcie_soc_ip.csr135589VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_RSV_3_SETns_noc_io_pcie_soc_ip.csr135600RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_E_UNSD_3_SETns_noc_io_pcie_soc_ip.csr135610UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rovcs_srouter_1_5_5_rovcs_sPCIE_NOC_ROUTER_1_5_5_ROVCS_S_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_S_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr135872R1_5 register rovcs_s0x40050R0x00000001Pcie_noc_router_1_5_5_rovcs_sThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_0_SETns_noc_io_pcie_soc_ip.csr135635CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_0_SETns_noc_io_pcie_soc_ip.csr135649CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_0_SETns_noc_io_pcie_soc_ip.csr135664VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_0_SETns_noc_io_pcie_soc_ip.csr135675RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_0_SETns_noc_io_pcie_soc_ip.csr135685UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_1_SETns_noc_io_pcie_soc_ip.csr135697CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_1_SETns_noc_io_pcie_soc_ip.csr135711CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_1_SETns_noc_io_pcie_soc_ip.csr135726VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_1_SETns_noc_io_pcie_soc_ip.csr135737RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_1_SETns_noc_io_pcie_soc_ip.csr135747UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_2_SETns_noc_io_pcie_soc_ip.csr135759CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_2_SETns_noc_io_pcie_soc_ip.csr135773CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_2_SETns_noc_io_pcie_soc_ip.csr135788VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_2_SETns_noc_io_pcie_soc_ip.csr135799RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_2_SETns_noc_io_pcie_soc_ip.csr135809UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CF_3_SETns_noc_io_pcie_soc_ip.csr135821CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_CE_3_SETns_noc_io_pcie_soc_ip.csr135835CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_VB_3_SETns_noc_io_pcie_soc_ip.csr135850VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_RSV_3_SETns_noc_io_pcie_soc_ip.csr135861RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_S_UNSD_3_SETns_noc_io_pcie_soc_ip.csr135871UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rovcs_wrouter_1_5_5_rovcs_wPCIE_NOC_ROUTER_1_5_5_ROVCS_W_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_W_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr136133R1_5 register rovcs_w0x40058R0x00000101Pcie_noc_router_1_5_5_rovcs_wThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_0_SETns_noc_io_pcie_soc_ip.csr135896CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_0_SETns_noc_io_pcie_soc_ip.csr135910CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_0_SETns_noc_io_pcie_soc_ip.csr135925VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_0_SETns_noc_io_pcie_soc_ip.csr135936RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_0_SETns_noc_io_pcie_soc_ip.csr135946UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_1_SETns_noc_io_pcie_soc_ip.csr135958CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_1_SETns_noc_io_pcie_soc_ip.csr135972CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_1_SETns_noc_io_pcie_soc_ip.csr135987VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_1_SETns_noc_io_pcie_soc_ip.csr135998RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_1_SETns_noc_io_pcie_soc_ip.csr136008UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_2_SETns_noc_io_pcie_soc_ip.csr136020CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_2_SETns_noc_io_pcie_soc_ip.csr136034CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_2_SETns_noc_io_pcie_soc_ip.csr136049VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_2_SETns_noc_io_pcie_soc_ip.csr136060RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_2_SETns_noc_io_pcie_soc_ip.csr136070UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CF_3_SETns_noc_io_pcie_soc_ip.csr136082CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_CE_3_SETns_noc_io_pcie_soc_ip.csr136096CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_VB_3_SETns_noc_io_pcie_soc_ip.csr136111VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_RSV_3_SETns_noc_io_pcie_soc_ip.csr136122RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_W_UNSD_3_SETns_noc_io_pcie_soc_ip.csr136132UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rovcs_irouter_1_5_5_rovcs_iPCIE_NOC_ROUTER_1_5_5_ROVCS_I_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_I_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr136394R1_5 register rovcs_i0x40068R0x00000001Pcie_noc_router_1_5_5_rovcs_iThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_0_SETns_noc_io_pcie_soc_ip.csr136157CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_0_SETns_noc_io_pcie_soc_ip.csr136171CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_0_SETns_noc_io_pcie_soc_ip.csr136186VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_0_SETns_noc_io_pcie_soc_ip.csr136197RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_0_SETns_noc_io_pcie_soc_ip.csr136207UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_1_SETns_noc_io_pcie_soc_ip.csr136219CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_1_SETns_noc_io_pcie_soc_ip.csr136233CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_1_SETns_noc_io_pcie_soc_ip.csr136248VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_1_SETns_noc_io_pcie_soc_ip.csr136259RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_1_SETns_noc_io_pcie_soc_ip.csr136269UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_2_SETns_noc_io_pcie_soc_ip.csr136281CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_2_SETns_noc_io_pcie_soc_ip.csr136295CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_2_SETns_noc_io_pcie_soc_ip.csr136310VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_2_SETns_noc_io_pcie_soc_ip.csr136321RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_2_SETns_noc_io_pcie_soc_ip.csr136331UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CF_3_SETns_noc_io_pcie_soc_ip.csr136343CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_CE_3_SETns_noc_io_pcie_soc_ip.csr136357CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_VB_3_SETns_noc_io_pcie_soc_ip.csr136372VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_RSV_3_SETns_noc_io_pcie_soc_ip.csr136383RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_I_UNSD_3_SETns_noc_io_pcie_soc_ip.csr136393UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rovcs_jrouter_1_5_5_rovcs_jPCIE_NOC_ROUTER_1_5_5_ROVCS_J_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_J_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr136655R1_5 register rovcs_j0x40070R0x00000001Pcie_noc_router_1_5_5_rovcs_jThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_0_SETns_noc_io_pcie_soc_ip.csr136418CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_0_SETns_noc_io_pcie_soc_ip.csr136432CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_0_SETns_noc_io_pcie_soc_ip.csr136447VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_0_SETns_noc_io_pcie_soc_ip.csr136458RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_0_SETns_noc_io_pcie_soc_ip.csr136468UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_1_SETns_noc_io_pcie_soc_ip.csr136480CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_1_SETns_noc_io_pcie_soc_ip.csr136494CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_1_SETns_noc_io_pcie_soc_ip.csr136509VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_1_SETns_noc_io_pcie_soc_ip.csr136520RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_1_SETns_noc_io_pcie_soc_ip.csr136530UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_2_SETns_noc_io_pcie_soc_ip.csr136542CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_2_SETns_noc_io_pcie_soc_ip.csr136556CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_2_SETns_noc_io_pcie_soc_ip.csr136571VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_2_SETns_noc_io_pcie_soc_ip.csr136582RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_2_SETns_noc_io_pcie_soc_ip.csr136592UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CF_3_SETns_noc_io_pcie_soc_ip.csr136604CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_CE_3_SETns_noc_io_pcie_soc_ip.csr136618CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_VB_3_SETns_noc_io_pcie_soc_ip.csr136633VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_RSV_3_SETns_noc_io_pcie_soc_ip.csr136644RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_J_UNSD_3_SETns_noc_io_pcie_soc_ip.csr136654UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rovcs_krouter_1_5_5_rovcs_kPCIE_NOC_ROUTER_1_5_5_ROVCS_K_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROVCS_K_OFFSETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr136916R1_5 register rovcs_k0x40078R0x00000101Pcie_noc_router_1_5_5_rovcs_kThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_0_SETns_noc_io_pcie_soc_ip.csr136679CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_0_SETns_noc_io_pcie_soc_ip.csr136693CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_0_SETns_noc_io_pcie_soc_ip.csr136708VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_0_SETns_noc_io_pcie_soc_ip.csr136719RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_0_SETns_noc_io_pcie_soc_ip.csr136729UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_1_SETns_noc_io_pcie_soc_ip.csr136741CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_1_SETns_noc_io_pcie_soc_ip.csr136755CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_1_SETns_noc_io_pcie_soc_ip.csr136770VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_1_SETns_noc_io_pcie_soc_ip.csr136781RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_1_SETns_noc_io_pcie_soc_ip.csr136791UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_2_SETns_noc_io_pcie_soc_ip.csr136803CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_2_SETns_noc_io_pcie_soc_ip.csr136817CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_2_SETns_noc_io_pcie_soc_ip.csr136832VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_2_SETns_noc_io_pcie_soc_ip.csr136843RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_2_SETns_noc_io_pcie_soc_ip.csr136853UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CF_3_SETns_noc_io_pcie_soc_ip.csr136865CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_CE_3_SETns_noc_io_pcie_soc_ip.csr136879CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_VB_3_SETns_noc_io_pcie_soc_ip.csr136894VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_RSV_3_SETns_noc_io_pcie_soc_ip.csr136905RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_MSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_LSBPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_RANGEPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_RESETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_GETPCIE_NOC_ROUTER_1_5_5_ROVCS_K_UNSD_3_SETns_noc_io_pcie_soc_ip.csr136915UNSD_331280x0Rregisterpcie_noc.router_1_5_5_rerouter_1_5_5_rePCIE_NOC_ROUTER_1_5_5_RE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RE_OFFSETPCIE_NOC_ROUTER_1_5_5_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137090R1_5 register re0x40080R/W0x00000000Pcie_noc_router_1_5_5_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_1_5_5_RE_OVFI_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_OVFI_MSBPCIE_NOC_ROUTER_1_5_5_RE_OVFI_LSBPCIE_NOC_ROUTER_1_5_5_RE_OVFI_RANGEPCIE_NOC_ROUTER_1_5_5_RE_OVFI_RESETPCIE_NOC_ROUTER_1_5_5_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_OVFI_GETPCIE_NOC_ROUTER_1_5_5_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr136942OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_1_5_5_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr136953CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_1_5_5_RE_OVFO_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_OVFO_MSBPCIE_NOC_ROUTER_1_5_5_RE_OVFO_LSBPCIE_NOC_ROUTER_1_5_5_RE_OVFO_RANGEPCIE_NOC_ROUTER_1_5_5_RE_OVFO_RESETPCIE_NOC_ROUTER_1_5_5_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_OVFO_GETPCIE_NOC_ROUTER_1_5_5_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr136967OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_1_5_5_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr136978UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_1_5_5_RE_PGE_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_PGE_MSBPCIE_NOC_ROUTER_1_5_5_RE_PGE_LSBPCIE_NOC_ROUTER_1_5_5_RE_PGE_RANGEPCIE_NOC_ROUTER_1_5_5_RE_PGE_RESETPCIE_NOC_ROUTER_1_5_5_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_PGE_GETPCIE_NOC_ROUTER_1_5_5_RE_PGE_SETns_noc_io_pcie_soc_ip.csr136990PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_1_5_5_RE_NLU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_NLU_MSBPCIE_NOC_ROUTER_1_5_5_RE_NLU_LSBPCIE_NOC_ROUTER_1_5_5_RE_NLU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_NLU_RESETPCIE_NOC_ROUTER_1_5_5_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_NLU_GETPCIE_NOC_ROUTER_1_5_5_RE_NLU_SETns_noc_io_pcie_soc_ip.csr137001NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_1_5_5_RE_ELU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_ELU_MSBPCIE_NOC_ROUTER_1_5_5_RE_ELU_LSBPCIE_NOC_ROUTER_1_5_5_RE_ELU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_ELU_RESETPCIE_NOC_ROUTER_1_5_5_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_ELU_GETPCIE_NOC_ROUTER_1_5_5_RE_ELU_SETns_noc_io_pcie_soc_ip.csr137012ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_1_5_5_RE_WLU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_WLU_MSBPCIE_NOC_ROUTER_1_5_5_RE_WLU_LSBPCIE_NOC_ROUTER_1_5_5_RE_WLU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_WLU_RESETPCIE_NOC_ROUTER_1_5_5_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_WLU_GETPCIE_NOC_ROUTER_1_5_5_RE_WLU_SETns_noc_io_pcie_soc_ip.csr137023WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_1_5_5_RE_SLU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_SLU_MSBPCIE_NOC_ROUTER_1_5_5_RE_SLU_LSBPCIE_NOC_ROUTER_1_5_5_RE_SLU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_SLU_RESETPCIE_NOC_ROUTER_1_5_5_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_SLU_GETPCIE_NOC_ROUTER_1_5_5_RE_SLU_SETns_noc_io_pcie_soc_ip.csr137034SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_1_5_5_RE_HLU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_HLU_MSBPCIE_NOC_ROUTER_1_5_5_RE_HLU_LSBPCIE_NOC_ROUTER_1_5_5_RE_HLU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_HLU_RESETPCIE_NOC_ROUTER_1_5_5_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_HLU_GETPCIE_NOC_ROUTER_1_5_5_RE_HLU_SETns_noc_io_pcie_soc_ip.csr137045HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_1_5_5_RE_ILU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_ILU_MSBPCIE_NOC_ROUTER_1_5_5_RE_ILU_LSBPCIE_NOC_ROUTER_1_5_5_RE_ILU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_ILU_RESETPCIE_NOC_ROUTER_1_5_5_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_ILU_GETPCIE_NOC_ROUTER_1_5_5_RE_ILU_SETns_noc_io_pcie_soc_ip.csr137056ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_1_5_5_RE_JLU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_JLU_MSBPCIE_NOC_ROUTER_1_5_5_RE_JLU_LSBPCIE_NOC_ROUTER_1_5_5_RE_JLU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_JLU_RESETPCIE_NOC_ROUTER_1_5_5_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_JLU_GETPCIE_NOC_ROUTER_1_5_5_RE_JLU_SETns_noc_io_pcie_soc_ip.csr137067JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_1_5_5_RE_KLU_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_KLU_MSBPCIE_NOC_ROUTER_1_5_5_RE_KLU_LSBPCIE_NOC_ROUTER_1_5_5_RE_KLU_RANGEPCIE_NOC_ROUTER_1_5_5_RE_KLU_RESETPCIE_NOC_ROUTER_1_5_5_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_KLU_GETPCIE_NOC_ROUTER_1_5_5_RE_KLU_SETns_noc_io_pcie_soc_ip.csr137078KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_1_5_5_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr137089UNSD_31_1431170x0000Rregisterpcie_noc.router_1_5_5_remrouter_1_5_5_remPCIE_NOC_ROUTER_1_5_5_REM_ADDRESSPCIE_NOC_ROUTER_1_5_5_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_REM_OFFSETPCIE_NOC_ROUTER_1_5_5_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137263R1_5 register rem0x40088R/W0x0001fe00Pcie_noc_router_1_5_5_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_MSBPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_LSBPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_RANGEPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_RESETPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_GETPCIE_NOC_ROUTER_1_5_5_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr137116OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_1_5_5_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr137127CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_MSBPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_LSBPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_RANGEPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_RESETPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_GETPCIE_NOC_ROUTER_1_5_5_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr137141OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_1_5_5_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr137152UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_1_5_5_REM_PGM_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_PGM_MSBPCIE_NOC_ROUTER_1_5_5_REM_PGM_LSBPCIE_NOC_ROUTER_1_5_5_REM_PGM_RANGEPCIE_NOC_ROUTER_1_5_5_REM_PGM_RESETPCIE_NOC_ROUTER_1_5_5_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_PGM_GETPCIE_NOC_ROUTER_1_5_5_REM_PGM_SETns_noc_io_pcie_soc_ip.csr137163PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_1_5_5_REM_MN_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MN_MSBPCIE_NOC_ROUTER_1_5_5_REM_MN_LSBPCIE_NOC_ROUTER_1_5_5_REM_MN_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MN_RESETPCIE_NOC_ROUTER_1_5_5_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MN_GETPCIE_NOC_ROUTER_1_5_5_REM_MN_SETns_noc_io_pcie_soc_ip.csr137174MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_1_5_5_REM_ME_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_ME_MSBPCIE_NOC_ROUTER_1_5_5_REM_ME_LSBPCIE_NOC_ROUTER_1_5_5_REM_ME_RANGEPCIE_NOC_ROUTER_1_5_5_REM_ME_RESETPCIE_NOC_ROUTER_1_5_5_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_ME_GETPCIE_NOC_ROUTER_1_5_5_REM_ME_SETns_noc_io_pcie_soc_ip.csr137185ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_1_5_5_REM_MW_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MW_MSBPCIE_NOC_ROUTER_1_5_5_REM_MW_LSBPCIE_NOC_ROUTER_1_5_5_REM_MW_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MW_RESETPCIE_NOC_ROUTER_1_5_5_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MW_GETPCIE_NOC_ROUTER_1_5_5_REM_MW_SETns_noc_io_pcie_soc_ip.csr137196MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_1_5_5_REM_MS_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MS_MSBPCIE_NOC_ROUTER_1_5_5_REM_MS_LSBPCIE_NOC_ROUTER_1_5_5_REM_MS_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MS_RESETPCIE_NOC_ROUTER_1_5_5_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MS_GETPCIE_NOC_ROUTER_1_5_5_REM_MS_SETns_noc_io_pcie_soc_ip.csr137207MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_1_5_5_REM_MH_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MH_MSBPCIE_NOC_ROUTER_1_5_5_REM_MH_LSBPCIE_NOC_ROUTER_1_5_5_REM_MH_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MH_RESETPCIE_NOC_ROUTER_1_5_5_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MH_GETPCIE_NOC_ROUTER_1_5_5_REM_MH_SETns_noc_io_pcie_soc_ip.csr137218MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_1_5_5_REM_MI_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MI_MSBPCIE_NOC_ROUTER_1_5_5_REM_MI_LSBPCIE_NOC_ROUTER_1_5_5_REM_MI_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MI_RESETPCIE_NOC_ROUTER_1_5_5_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MI_GETPCIE_NOC_ROUTER_1_5_5_REM_MI_SETns_noc_io_pcie_soc_ip.csr137229MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_1_5_5_REM_MJ_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MJ_MSBPCIE_NOC_ROUTER_1_5_5_REM_MJ_LSBPCIE_NOC_ROUTER_1_5_5_REM_MJ_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MJ_RESETPCIE_NOC_ROUTER_1_5_5_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MJ_GETPCIE_NOC_ROUTER_1_5_5_REM_MJ_SETns_noc_io_pcie_soc_ip.csr137240MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_1_5_5_REM_MK_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_MK_MSBPCIE_NOC_ROUTER_1_5_5_REM_MK_LSBPCIE_NOC_ROUTER_1_5_5_REM_MK_RANGEPCIE_NOC_ROUTER_1_5_5_REM_MK_RESETPCIE_NOC_ROUTER_1_5_5_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_MK_GETPCIE_NOC_ROUTER_1_5_5_REM_MK_SETns_noc_io_pcie_soc_ip.csr137251MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_1_5_5_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr137262UNSD_31_1431170x0000Rregisterpcie_noc.router_1_5_5_reccrouter_1_5_5_reccPCIE_NOC_ROUTER_1_5_5_RECC_ADDRESSPCIE_NOC_ROUTER_1_5_5_RECC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RECC_OFFSETPCIE_NOC_ROUTER_1_5_5_RECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137348R1_5 register recc0x40090R/W0x00000000Pcie_noc_router_1_5_5_reccThis register is used to select which hardware events will increment the event counter.falsefalsefalsefalseIVCPCIE_NOC_ROUTER_1_5_5_RECC_IVC_WIDTHPCIE_NOC_ROUTER_1_5_5_RECC_IVC_MSBPCIE_NOC_ROUTER_1_5_5_RECC_IVC_LSBPCIE_NOC_ROUTER_1_5_5_RECC_IVC_RANGEPCIE_NOC_ROUTER_1_5_5_RECC_IVC_RESETPCIE_NOC_ROUTER_1_5_5_RECC_IVC_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RECC_IVC_GETPCIE_NOC_ROUTER_1_5_5_RECC_IVC_SETns_noc_io_pcie_soc_ip.csr137284IVC11: Input VC 310: Input VC 201: Input VC 100: Input VC 0100x0R/WUNSD_3_2PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_WIDTHPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_MSBPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_LSBPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_RANGEPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_RESETPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_GETPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_3_2_SETns_noc_io_pcie_soc_ip.csr137295UNSD_3_2320x0RINPPCIE_NOC_ROUTER_1_5_5_RECC_INP_WIDTHPCIE_NOC_ROUTER_1_5_5_RECC_INP_MSBPCIE_NOC_ROUTER_1_5_5_RECC_INP_LSBPCIE_NOC_ROUTER_1_5_5_RECC_INP_RANGEPCIE_NOC_ROUTER_1_5_5_RECC_INP_RESETPCIE_NOC_ROUTER_1_5_5_RECC_INP_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RECC_INP_GETPCIE_NOC_ROUTER_1_5_5_RECC_INP_SETns_noc_io_pcie_soc_ip.csr137306INPInput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_GETPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr137317UNSD_7_7770x0REVTPCIE_NOC_ROUTER_1_5_5_RECC_EVT_WIDTHPCIE_NOC_ROUTER_1_5_5_RECC_EVT_MSBPCIE_NOC_ROUTER_1_5_5_RECC_EVT_LSBPCIE_NOC_ROUTER_1_5_5_RECC_EVT_RANGEPCIE_NOC_ROUTER_1_5_5_RECC_EVT_RESETPCIE_NOC_ROUTER_1_5_5_RECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RECC_EVT_GETPCIE_NOC_ROUTER_1_5_5_RECC_EVT_SETns_noc_io_pcie_soc_ip.csr137336EVT11: Generates count event when VC has valid data, but is stalled10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port00: Disable980x0R/WUNSD_31_10PCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_WIDTHPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_MSBPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_LSBPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_RANGEPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_RESETPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_GETPCIE_NOC_ROUTER_1_5_5_RECC_UNSD_31_10_SETns_noc_io_pcie_soc_ip.csr137347UNSD_31_1031100x000000Rregisterpcie_noc.router_1_5_5_recrouter_1_5_5_recPCIE_NOC_ROUTER_1_5_5_REC_ADDRESSPCIE_NOC_ROUTER_1_5_5_REC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_REC_OFFSETPCIE_NOC_ROUTER_1_5_5_REC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137373R1_5 register rec0x40098R/W0x00000000Pcie_noc_router_1_5_5_recThis register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_GETPCIE_NOC_ROUTER_1_5_5_REC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr137372EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_1_5_5_idrouter_1_5_5_idPCIE_NOC_ROUTER_1_5_5_ID_ADDRESSPCIE_NOC_ROUTER_1_5_5_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ID_OFFSETPCIE_NOC_ROUTER_1_5_5_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137442R1_5 register id0x400A0R0x010000a1Pcie_noc_router_1_5_5_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_1_5_5_ID_LAYER_WIDTHPCIE_NOC_ROUTER_1_5_5_ID_LAYER_MSBPCIE_NOC_ROUTER_1_5_5_ID_LAYER_LSBPCIE_NOC_ROUTER_1_5_5_ID_LAYER_RANGEPCIE_NOC_ROUTER_1_5_5_ID_LAYER_RESETPCIE_NOC_ROUTER_1_5_5_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ID_LAYER_GETPCIE_NOC_ROUTER_1_5_5_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr137398LAYER5-bit identifier of the NoC layer on which this router is located400x01RPOSPCIE_NOC_ROUTER_1_5_5_ID_POS_WIDTHPCIE_NOC_ROUTER_1_5_5_ID_POS_MSBPCIE_NOC_ROUTER_1_5_5_ID_POS_LSBPCIE_NOC_ROUTER_1_5_5_ID_POS_RANGEPCIE_NOC_ROUTER_1_5_5_ID_POS_RESETPCIE_NOC_ROUTER_1_5_5_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ID_POS_GETPCIE_NOC_ROUTER_1_5_5_ID_POS_SETns_noc_io_pcie_soc_ip.csr137409POS16-bit position ID of this router in the NoC2050x0005RZEROPCIE_NOC_ROUTER_1_5_5_ID_ZERO_WIDTHPCIE_NOC_ROUTER_1_5_5_ID_ZERO_MSBPCIE_NOC_ROUTER_1_5_5_ID_ZERO_LSBPCIE_NOC_ROUTER_1_5_5_ID_ZERO_RANGEPCIE_NOC_ROUTER_1_5_5_ID_ZERO_RESETPCIE_NOC_ROUTER_1_5_5_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ID_ZERO_GETPCIE_NOC_ROUTER_1_5_5_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr137420ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_1_5_5_ID_ONE_WIDTHPCIE_NOC_ROUTER_1_5_5_ID_ONE_MSBPCIE_NOC_ROUTER_1_5_5_ID_ONE_LSBPCIE_NOC_ROUTER_1_5_5_ID_ONE_RANGEPCIE_NOC_ROUTER_1_5_5_ID_ONE_RESETPCIE_NOC_ROUTER_1_5_5_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ID_ONE_GETPCIE_NOC_ROUTER_1_5_5_ID_ONE_SETns_noc_io_pcie_soc_ip.csr137431ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_1_5_5_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr137441UNSD_31_2531250x00Rregisterpcie_noc.router_1_5_5_rcgcrouter_1_5_5_rcgcPCIE_NOC_ROUTER_1_5_5_RCGC_ADDRESSPCIE_NOC_ROUTER_1_5_5_RCGC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RCGC_OFFSETPCIE_NOC_ROUTER_1_5_5_RCGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137468R1_5 register rcgc0x400A8R/W0x00000064Pcie_noc_router_1_5_5_rcgcProgrammable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_GETPCIE_NOC_ROUTER_1_5_5_RCGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr137467HYSTERESIS_COUNTERHysteresis counter3100x00000064R/Wregisterpcie_noc.router_1_5_5_rcgorouter_1_5_5_rcgoPCIE_NOC_ROUTER_1_5_5_RCGO_ADDRESSPCIE_NOC_ROUTER_1_5_5_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_RCGO_OFFSETPCIE_NOC_ROUTER_1_5_5_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137507R1_5 register rcgo0x400B0R/W0x00000000Pcie_noc_router_1_5_5_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_MSBPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_LSBPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_RANGEPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_RESETPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_GETPCIE_NOC_ROUTER_1_5_5_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr137495FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_1_5_5_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr137506UNSD_31_13110x00000000Rregisterpcie_noc.router_1_5_5_p1_rperrrouter_1_5_5_p1_rperrPCIE_NOC_ROUTER_1_5_5_P1_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P1_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P1_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr137794R1_5 register p1_rperr0x400C0R/W0x00000000Pcie_noc_router_1_5_5_p1_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_SETns_noc_io_pcie_soc_ip.csr137550D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr137561SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr137572PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr137583RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr137594CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr137605UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr137616D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr137627SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr137639PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr137650RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr137661D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr137672SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr137684PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr137695RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr137707D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr137719SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr137732PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr137744RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr137756D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr137768SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr137781PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr137793RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p2_rperrrouter_1_5_5_p2_rperrPCIE_NOC_ROUTER_1_5_5_P2_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P2_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P2_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr138085R1_5 register p2_rperr0x400C8R/W0x00000000Pcie_noc_router_1_5_5_p2_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_SETns_noc_io_pcie_soc_ip.csr137837D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr137848SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr137859PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr137870RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr137881CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr137892UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr137903D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr137914SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr137926PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr137937RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr137949D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr137961SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr137974PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr137986RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr137998D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr138010SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr138023PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr138035RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr138047D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr138059SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr138072PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr138084RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p3_rperrrouter_1_5_5_p3_rperrPCIE_NOC_ROUTER_1_5_5_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P3_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr138376R1_5 register p3_rperr0x400D0R/W0x00000000Pcie_noc_router_1_5_5_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr138128D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr138139SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr138150PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr138161RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr138172CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr138183UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr138194D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr138205SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr138217PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr138228RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr138240D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr138252SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr138265PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr138277RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr138289D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr138301SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr138314PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr138326RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr138338D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr138350SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr138363PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr138375RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p4_rperrrouter_1_5_5_p4_rperrPCIE_NOC_ROUTER_1_5_5_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P4_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr138667R1_5 register p4_rperr0x400D8R/W0x00000000Pcie_noc_router_1_5_5_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr138419D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr138430SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr138441PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr138452RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr138463CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr138474UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr138485D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr138496SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr138508PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr138519RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr138531D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr138543SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr138556PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr138568RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr138580D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr138592SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr138605PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr138617RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr138629D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr138641SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr138654PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr138666RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p5_rperrrouter_1_5_5_p5_rperrPCIE_NOC_ROUTER_1_5_5_P5_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P5_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P5_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr138958R1_5 register p5_rperr0x400E0R/W0x00000000Pcie_noc_router_1_5_5_p5_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_SETns_noc_io_pcie_soc_ip.csr138710D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr138721SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr138732PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr138743RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr138754CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr138765UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr138776D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr138787SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr138799PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr138810RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr138822D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr138834SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr138847PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr138859RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr138871D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr138883SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr138896PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr138908RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr138920D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr138932SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr138945PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr138957RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p6_rperrrouter_1_5_5_p6_rperrPCIE_NOC_ROUTER_1_5_5_P6_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P6_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P6_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr139249R1_5 register p6_rperr0x400E8R/W0x00000000Pcie_noc_router_1_5_5_p6_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_SETns_noc_io_pcie_soc_ip.csr139001D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr139012SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr139023PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr139034RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr139045CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr139056UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr139067D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr139078SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr139090PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr139101RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr139113D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr139125SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr139138PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr139150RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr139162D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr139174SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr139187PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr139199RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr139211D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr139223SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr139236PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr139248RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p7_rperrrouter_1_5_5_p7_rperrPCIE_NOC_ROUTER_1_5_5_P7_RPERR_ADDRESSPCIE_NOC_ROUTER_1_5_5_P7_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P7_RPERR_OFFSETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr139540R1_5 register p7_rperr0x400F0R/W0x00000000Pcie_noc_router_1_5_5_p7_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_SETns_noc_io_pcie_soc_ip.csr139292D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr139303SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr139314PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr139325RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr139336CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr139347UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr139358D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr139369SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr139381PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr139392RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr139404D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr139416SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr139429PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr139441RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr139453D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr139465SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr139478PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr139490RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr139502D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr139514SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr139527PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr139539RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_5_5_p1_rperrmrouter_1_5_5_p1_rperrmPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr139798R1_5 register p1_rperrm0x40100R/W0x00000000Pcie_noc_router_1_5_5_p1_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr139562DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr139573SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr139584PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr139595RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr139606CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr139617UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr139628D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr139639SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr139651PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr139662RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr139673D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr139684SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr139696PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr139707RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr139718D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr139729SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr139741PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr139752RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr139763D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr139774SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr139786PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P1_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr139797RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_p2_rperrmrouter_1_5_5_p2_rperrmPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr140056R1_5 register p2_rperrm0x40108R/W0x00000000Pcie_noc_router_1_5_5_p2_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr139820DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr139831SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr139842PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr139853RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr139864CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr139875UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr139886D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr139897SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr139909PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr139920RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr139931D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr139942SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr139954PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr139965RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr139976D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr139987SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr139999PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr140010RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr140021D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr140032SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr140044PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P2_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr140055RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_p3_rperrmrouter_1_5_5_p3_rperrmPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr140314R1_5 register p3_rperrm0x40110R/W0x00000000Pcie_noc_router_1_5_5_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr140078DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr140089SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr140100PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr140111RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr140122CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr140133UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr140144D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr140155SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr140167PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr140178RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr140189D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr140200SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr140212PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr140223RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr140234D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr140245SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr140257PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr140268RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr140279D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr140290SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr140302PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr140313RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_p4_rperrmrouter_1_5_5_p4_rperrmPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr140572R1_5 register p4_rperrm0x40118R/W0x00000000Pcie_noc_router_1_5_5_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr140336DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr140347SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr140358PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr140369RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr140380CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr140391UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr140402D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr140413SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr140425PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr140436RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr140447D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr140458SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr140470PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr140481RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr140492D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr140503SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr140515PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr140526RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr140537D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr140548SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr140560PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr140571RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_p5_rperrmrouter_1_5_5_p5_rperrmPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr140830R1_5 register p5_rperrm0x40120R/W0x00000000Pcie_noc_router_1_5_5_p5_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr140594DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr140605SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr140616PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr140627RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr140638CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr140649UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr140660D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr140671SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr140683PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr140694RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr140705D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr140716SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr140728PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr140739RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr140750D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr140761SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr140773PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr140784RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr140795D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr140806SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr140818PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P5_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr140829RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_p6_rperrmrouter_1_5_5_p6_rperrmPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr141088R1_5 register p6_rperrm0x40128R/W0x00000000Pcie_noc_router_1_5_5_p6_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr140852DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr140863SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr140874PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr140885RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr140896CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr140907UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr140918D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr140929SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr140941PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr140952RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr140963D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr140974SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr140986PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr140997RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr141008D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr141019SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr141031PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr141042RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr141053D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr141064SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr141076PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P6_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr141087RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_p7_rperrmrouter_1_5_5_p7_rperrmPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_OFFSETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr141346R1_5 register p7_rperrm0x40130R/W0x00000000Pcie_noc_router_1_5_5_p7_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr141110DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr141121SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr141132PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr141143RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr141154CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr141165UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr141176D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr141187SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr141199PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr141210RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr141221D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr141232SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr141244PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr141255RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr141266D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr141277SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr141289PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr141300RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr141311D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr141322SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr141334PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_5_5_P7_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr141345RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_5_5_roeccrouter_1_5_5_roeccPCIE_NOC_ROUTER_1_5_5_ROECC_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROECC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROECC_OFFSETPCIE_NOC_ROUTER_1_5_5_ROECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr141419R1_5 register roecc0x40138R/W0x00000000Pcie_noc_router_1_5_5_roeccThis register is used to select which hardware events will increment the output event counter.falsefalsefalsefalseOVCPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_WIDTHPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_MSBPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_LSBPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_RANGEPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_RESETPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_GETPCIE_NOC_ROUTER_1_5_5_ROECC_OVC_SETns_noc_io_pcie_soc_ip.csr141364OVCBit map to select output VCs to monitor events on300x0R/WOPPCIE_NOC_ROUTER_1_5_5_ROECC_OP_WIDTHPCIE_NOC_ROUTER_1_5_5_ROECC_OP_MSBPCIE_NOC_ROUTER_1_5_5_ROECC_OP_LSBPCIE_NOC_ROUTER_1_5_5_ROECC_OP_RANGEPCIE_NOC_ROUTER_1_5_5_ROECC_OP_RESETPCIE_NOC_ROUTER_1_5_5_ROECC_OP_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROECC_OP_GETPCIE_NOC_ROUTER_1_5_5_ROECC_OP_SETns_noc_io_pcie_soc_ip.csr141375OPOutput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_GETPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr141386UNSD_7_7770x0REVTPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_WIDTHPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_MSBPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_LSBPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_RANGEPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_RESETPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_GETPCIE_NOC_ROUTER_1_5_5_ROECC_EVT_SETns_noc_io_pcie_soc_ip.csr141407EVT100: Port stalled. Input flits are available for the port, but no output VC has credit011: Generates count event when flits are available to be sent to output VC, but the VC has no credit010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port000: Disable1080x0R/WUNSD_31_11PCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_WIDTHPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_MSBPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_LSBPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_RANGEPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_RESETPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_GETPCIE_NOC_ROUTER_1_5_5_ROECC_UNSD_31_11_SETns_noc_io_pcie_soc_ip.csr141418UNSD_31_1131110x000000Rregisterpcie_noc.router_1_5_5_roecrouter_1_5_5_roecPCIE_NOC_ROUTER_1_5_5_ROEC_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROEC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_5_5_ROEC_OFFSETPCIE_NOC_ROUTER_1_5_5_ROEC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr141444R1_5 register roec0x40140R/W0x00000000Pcie_noc_router_1_5_5_roecThis register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_GETPCIE_NOC_ROUTER_1_5_5_ROEC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr141443EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_1_6_6_rivcs_hrouter_1_6_6_rivcs_hPCIE_NOC_ROUTER_1_6_6_RIVCS_H_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr141773R1_6 register rivcs_h0x44000R0x00000000Pcie_noc_router_1_6_6_rivcs_hThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_0_SETns_noc_io_pcie_soc_ip.csr141469OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_0_SETns_noc_io_pcie_soc_ip.csr141483UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_0_SETns_noc_io_pcie_soc_ip.csr141499S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_0_SETns_noc_io_pcie_soc_ip.csr141513B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_0_SETns_noc_io_pcie_soc_ip.csr141524F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_0_SETns_noc_io_pcie_soc_ip.csr141535V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_1_SETns_noc_io_pcie_soc_ip.csr141548OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_1_SETns_noc_io_pcie_soc_ip.csr141562UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_1_SETns_noc_io_pcie_soc_ip.csr141578S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_1_SETns_noc_io_pcie_soc_ip.csr141592B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_1_SETns_noc_io_pcie_soc_ip.csr141603F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_1_SETns_noc_io_pcie_soc_ip.csr141614V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_2_SETns_noc_io_pcie_soc_ip.csr141627OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_2_SETns_noc_io_pcie_soc_ip.csr141641UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_2_SETns_noc_io_pcie_soc_ip.csr141657S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_2_SETns_noc_io_pcie_soc_ip.csr141671B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_2_SETns_noc_io_pcie_soc_ip.csr141682F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_2_SETns_noc_io_pcie_soc_ip.csr141693V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_OUTP_3_SETns_noc_io_pcie_soc_ip.csr141706OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_UP_3_SETns_noc_io_pcie_soc_ip.csr141720UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_S_3_SETns_noc_io_pcie_soc_ip.csr141736S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_B_3_SETns_noc_io_pcie_soc_ip.csr141750B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_F_3_SETns_noc_io_pcie_soc_ip.csr141761F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_H_V_3_SETns_noc_io_pcie_soc_ip.csr141772V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_erouter_1_6_6_rivcs_ePCIE_NOC_ROUTER_1_6_6_RIVCS_E_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr142102R1_6 register rivcs_e0x44008R0x00000000Pcie_noc_router_1_6_6_rivcs_eThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_0_SETns_noc_io_pcie_soc_ip.csr141798OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_0_SETns_noc_io_pcie_soc_ip.csr141812UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_0_SETns_noc_io_pcie_soc_ip.csr141828S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_0_SETns_noc_io_pcie_soc_ip.csr141842B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_0_SETns_noc_io_pcie_soc_ip.csr141853F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_0_SETns_noc_io_pcie_soc_ip.csr141864V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_1_SETns_noc_io_pcie_soc_ip.csr141877OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_1_SETns_noc_io_pcie_soc_ip.csr141891UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_1_SETns_noc_io_pcie_soc_ip.csr141907S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_1_SETns_noc_io_pcie_soc_ip.csr141921B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_1_SETns_noc_io_pcie_soc_ip.csr141932F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_1_SETns_noc_io_pcie_soc_ip.csr141943V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_2_SETns_noc_io_pcie_soc_ip.csr141956OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_2_SETns_noc_io_pcie_soc_ip.csr141970UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_2_SETns_noc_io_pcie_soc_ip.csr141986S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_2_SETns_noc_io_pcie_soc_ip.csr142000B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_2_SETns_noc_io_pcie_soc_ip.csr142011F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_2_SETns_noc_io_pcie_soc_ip.csr142022V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_OUTP_3_SETns_noc_io_pcie_soc_ip.csr142035OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_UP_3_SETns_noc_io_pcie_soc_ip.csr142049UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_S_3_SETns_noc_io_pcie_soc_ip.csr142065S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_B_3_SETns_noc_io_pcie_soc_ip.csr142079B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_F_3_SETns_noc_io_pcie_soc_ip.csr142090F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_E_V_3_SETns_noc_io_pcie_soc_ip.csr142101V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_srouter_1_6_6_rivcs_sPCIE_NOC_ROUTER_1_6_6_RIVCS_S_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr142431R1_6 register rivcs_s0x44010R0x00000000Pcie_noc_router_1_6_6_rivcs_sThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_0_SETns_noc_io_pcie_soc_ip.csr142127OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_0_SETns_noc_io_pcie_soc_ip.csr142141UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_0_SETns_noc_io_pcie_soc_ip.csr142157S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_0_SETns_noc_io_pcie_soc_ip.csr142171B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_0_SETns_noc_io_pcie_soc_ip.csr142182F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_0_SETns_noc_io_pcie_soc_ip.csr142193V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_1_SETns_noc_io_pcie_soc_ip.csr142206OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_1_SETns_noc_io_pcie_soc_ip.csr142220UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_1_SETns_noc_io_pcie_soc_ip.csr142236S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_1_SETns_noc_io_pcie_soc_ip.csr142250B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_1_SETns_noc_io_pcie_soc_ip.csr142261F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_1_SETns_noc_io_pcie_soc_ip.csr142272V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_2_SETns_noc_io_pcie_soc_ip.csr142285OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_2_SETns_noc_io_pcie_soc_ip.csr142299UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_2_SETns_noc_io_pcie_soc_ip.csr142315S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_2_SETns_noc_io_pcie_soc_ip.csr142329B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_2_SETns_noc_io_pcie_soc_ip.csr142340F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_2_SETns_noc_io_pcie_soc_ip.csr142351V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_OUTP_3_SETns_noc_io_pcie_soc_ip.csr142364OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_UP_3_SETns_noc_io_pcie_soc_ip.csr142378UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_S_3_SETns_noc_io_pcie_soc_ip.csr142394S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_B_3_SETns_noc_io_pcie_soc_ip.csr142408B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_F_3_SETns_noc_io_pcie_soc_ip.csr142419F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_S_V_3_SETns_noc_io_pcie_soc_ip.csr142430V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_wrouter_1_6_6_rivcs_wPCIE_NOC_ROUTER_1_6_6_RIVCS_W_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr142760R1_6 register rivcs_w0x44018R0x00000000Pcie_noc_router_1_6_6_rivcs_wThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_0_SETns_noc_io_pcie_soc_ip.csr142456OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_0_SETns_noc_io_pcie_soc_ip.csr142470UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_0_SETns_noc_io_pcie_soc_ip.csr142486S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_0_SETns_noc_io_pcie_soc_ip.csr142500B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_0_SETns_noc_io_pcie_soc_ip.csr142511F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_0_SETns_noc_io_pcie_soc_ip.csr142522V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_1_SETns_noc_io_pcie_soc_ip.csr142535OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_1_SETns_noc_io_pcie_soc_ip.csr142549UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_1_SETns_noc_io_pcie_soc_ip.csr142565S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_1_SETns_noc_io_pcie_soc_ip.csr142579B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_1_SETns_noc_io_pcie_soc_ip.csr142590F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_1_SETns_noc_io_pcie_soc_ip.csr142601V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_2_SETns_noc_io_pcie_soc_ip.csr142614OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_2_SETns_noc_io_pcie_soc_ip.csr142628UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_2_SETns_noc_io_pcie_soc_ip.csr142644S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_2_SETns_noc_io_pcie_soc_ip.csr142658B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_2_SETns_noc_io_pcie_soc_ip.csr142669F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_2_SETns_noc_io_pcie_soc_ip.csr142680V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_OUTP_3_SETns_noc_io_pcie_soc_ip.csr142693OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_UP_3_SETns_noc_io_pcie_soc_ip.csr142707UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_S_3_SETns_noc_io_pcie_soc_ip.csr142723S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_B_3_SETns_noc_io_pcie_soc_ip.csr142737B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_F_3_SETns_noc_io_pcie_soc_ip.csr142748F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_W_V_3_SETns_noc_io_pcie_soc_ip.csr142759V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_nrouter_1_6_6_rivcs_nPCIE_NOC_ROUTER_1_6_6_RIVCS_N_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_N_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr143089R1_6 register rivcs_n0x44020R0x00000000Pcie_noc_router_1_6_6_rivcs_nThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_0_SETns_noc_io_pcie_soc_ip.csr142785OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_0_SETns_noc_io_pcie_soc_ip.csr142799UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_0_SETns_noc_io_pcie_soc_ip.csr142815S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_0_SETns_noc_io_pcie_soc_ip.csr142829B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_0_SETns_noc_io_pcie_soc_ip.csr142840F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_0_SETns_noc_io_pcie_soc_ip.csr142851V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_1_SETns_noc_io_pcie_soc_ip.csr142864OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_1_SETns_noc_io_pcie_soc_ip.csr142878UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_1_SETns_noc_io_pcie_soc_ip.csr142894S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_1_SETns_noc_io_pcie_soc_ip.csr142908B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_1_SETns_noc_io_pcie_soc_ip.csr142919F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_1_SETns_noc_io_pcie_soc_ip.csr142930V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_2_SETns_noc_io_pcie_soc_ip.csr142943OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_2_SETns_noc_io_pcie_soc_ip.csr142957UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_2_SETns_noc_io_pcie_soc_ip.csr142973S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_2_SETns_noc_io_pcie_soc_ip.csr142987B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_2_SETns_noc_io_pcie_soc_ip.csr142998F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_2_SETns_noc_io_pcie_soc_ip.csr143009V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_OUTP_3_SETns_noc_io_pcie_soc_ip.csr143022OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_UP_3_SETns_noc_io_pcie_soc_ip.csr143036UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_S_3_SETns_noc_io_pcie_soc_ip.csr143052S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_B_3_SETns_noc_io_pcie_soc_ip.csr143066B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_F_3_SETns_noc_io_pcie_soc_ip.csr143077F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_N_V_3_SETns_noc_io_pcie_soc_ip.csr143088V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_irouter_1_6_6_rivcs_iPCIE_NOC_ROUTER_1_6_6_RIVCS_I_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr143418R1_6 register rivcs_i0x44028R0x00000000Pcie_noc_router_1_6_6_rivcs_iThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_0_SETns_noc_io_pcie_soc_ip.csr143114OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_0_SETns_noc_io_pcie_soc_ip.csr143128UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_0_SETns_noc_io_pcie_soc_ip.csr143144S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_0_SETns_noc_io_pcie_soc_ip.csr143158B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_0_SETns_noc_io_pcie_soc_ip.csr143169F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_0_SETns_noc_io_pcie_soc_ip.csr143180V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_1_SETns_noc_io_pcie_soc_ip.csr143193OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_1_SETns_noc_io_pcie_soc_ip.csr143207UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_1_SETns_noc_io_pcie_soc_ip.csr143223S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_1_SETns_noc_io_pcie_soc_ip.csr143237B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_1_SETns_noc_io_pcie_soc_ip.csr143248F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_1_SETns_noc_io_pcie_soc_ip.csr143259V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_2_SETns_noc_io_pcie_soc_ip.csr143272OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_2_SETns_noc_io_pcie_soc_ip.csr143286UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_2_SETns_noc_io_pcie_soc_ip.csr143302S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_2_SETns_noc_io_pcie_soc_ip.csr143316B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_2_SETns_noc_io_pcie_soc_ip.csr143327F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_2_SETns_noc_io_pcie_soc_ip.csr143338V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_OUTP_3_SETns_noc_io_pcie_soc_ip.csr143351OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_UP_3_SETns_noc_io_pcie_soc_ip.csr143365UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_S_3_SETns_noc_io_pcie_soc_ip.csr143381S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_B_3_SETns_noc_io_pcie_soc_ip.csr143395B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_F_3_SETns_noc_io_pcie_soc_ip.csr143406F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_I_V_3_SETns_noc_io_pcie_soc_ip.csr143417V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_jrouter_1_6_6_rivcs_jPCIE_NOC_ROUTER_1_6_6_RIVCS_J_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr143747R1_6 register rivcs_j0x44030R0x00000000Pcie_noc_router_1_6_6_rivcs_jThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_0_SETns_noc_io_pcie_soc_ip.csr143443OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_0_SETns_noc_io_pcie_soc_ip.csr143457UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_0_SETns_noc_io_pcie_soc_ip.csr143473S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_0_SETns_noc_io_pcie_soc_ip.csr143487B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_0_SETns_noc_io_pcie_soc_ip.csr143498F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_0_SETns_noc_io_pcie_soc_ip.csr143509V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_1_SETns_noc_io_pcie_soc_ip.csr143522OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_1_SETns_noc_io_pcie_soc_ip.csr143536UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_1_SETns_noc_io_pcie_soc_ip.csr143552S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_1_SETns_noc_io_pcie_soc_ip.csr143566B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_1_SETns_noc_io_pcie_soc_ip.csr143577F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_1_SETns_noc_io_pcie_soc_ip.csr143588V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_2_SETns_noc_io_pcie_soc_ip.csr143601OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_2_SETns_noc_io_pcie_soc_ip.csr143615UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_2_SETns_noc_io_pcie_soc_ip.csr143631S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_2_SETns_noc_io_pcie_soc_ip.csr143645B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_2_SETns_noc_io_pcie_soc_ip.csr143656F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_2_SETns_noc_io_pcie_soc_ip.csr143667V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_OUTP_3_SETns_noc_io_pcie_soc_ip.csr143680OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_UP_3_SETns_noc_io_pcie_soc_ip.csr143694UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_S_3_SETns_noc_io_pcie_soc_ip.csr143710S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_B_3_SETns_noc_io_pcie_soc_ip.csr143724B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_F_3_SETns_noc_io_pcie_soc_ip.csr143735F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_J_V_3_SETns_noc_io_pcie_soc_ip.csr143746V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rivcs_krouter_1_6_6_rivcs_kPCIE_NOC_ROUTER_1_6_6_RIVCS_K_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OFFSETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr144076R1_6 register rivcs_k0x44038R0x00000000Pcie_noc_router_1_6_6_rivcs_kThis register indicates the current status of a single input port of a router. Each register tracks the status of up to 4 virtual channels for the input port. There are 8 RIVCS per router, one for each router's input port.falsefalsefalsefalseOUTP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_0_SETns_noc_io_pcie_soc_ip.csr143772OUTP_0Value indicates the router output port to which the packet at the head of the VC 0 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K200x0RUP_0PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_0_SETns_noc_io_pcie_soc_ip.csr143786UP_01'b1: Indicates that the flit accumulator on this VC 0 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 0330x0RS_0PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_0_SETns_noc_io_pcie_soc_ip.csr143802S_01'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 0 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 0 has already acquired the VC on the output port440x0RB_0PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_0_SETns_noc_io_pcie_soc_ip.csr143816B_01'b1: Indicates that the head flit of the VC 0 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 0 is of the 'QoS Normal' type550x0RF_0PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_0_SETns_noc_io_pcie_soc_ip.csr143827F_01'b1: Buffer full in VC 0660x0RV_0PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_0_SETns_noc_io_pcie_soc_ip.csr143838V_01'b1: Head flit valid (buffer ready) in VC 0770x0ROUTP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_1_SETns_noc_io_pcie_soc_ip.csr143851OUTP_1Value indicates the router output port to which the packet at the head of the VC 1 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K1080x0RUP_1PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_1_SETns_noc_io_pcie_soc_ip.csr143865UP_11'b1: Indicates that the flit accumulator on this VC 1 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 111110x0RS_1PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_1_SETns_noc_io_pcie_soc_ip.csr143881S_11'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 1 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 1 has already acquired the VC on the output port12120x0RB_1PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_1_SETns_noc_io_pcie_soc_ip.csr143895B_11'b1: Indicates that the head flit of the VC 1 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 1 is of the 'QoS Normal' type13130x0RF_1PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_1_SETns_noc_io_pcie_soc_ip.csr143906F_11'b1: Buffer full in VC 114140x0RV_1PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_1_SETns_noc_io_pcie_soc_ip.csr143917V_11'b1: Head flit valid (buffer ready) in VC 115150x0ROUTP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_2_SETns_noc_io_pcie_soc_ip.csr143930OUTP_2Value indicates the router output port to which the packet at the head of the VC 2 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K18160x0RUP_2PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_2_SETns_noc_io_pcie_soc_ip.csr143944UP_21'b1: Indicates that the flit accumulator on this VC 2 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 219190x0RS_2PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_2_SETns_noc_io_pcie_soc_ip.csr143960S_21'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 2 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 2 has already acquired the VC on the output port20200x0RB_2PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_2_SETns_noc_io_pcie_soc_ip.csr143974B_21'b1: Indicates that the head flit of the VC 2 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 2 is of the 'QoS Normal' type21210x0RF_2PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_2_SETns_noc_io_pcie_soc_ip.csr143985F_21'b1: Buffer full in VC 222220x0RV_2PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_2_SETns_noc_io_pcie_soc_ip.csr143996V_21'b1: Head flit valid (buffer ready) in VC 223230x0ROUTP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_OUTP_3_SETns_noc_io_pcie_soc_ip.csr144009OUTP_3Value indicates the router output port to which the packet at the head of the VC 3 is destined to: 3'd0:N, 3'd1:E, 3'd2:W, 3'd3:S, 3'd4:H, 3'd5:I, 3'd6:J, 3'd7:K26240x0RUP_3PCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_UP_3_SETns_noc_io_pcie_soc_ip.csr144023UP_31'b1: Indicates that the flit accumulator on this VC 3 for upsizing to an output port is currently holding a flit1'b0: Indicates that either the upsizing accumulator is empty or there is no upsizing from the VC 327270x0RS_3PCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_S_3_SETns_noc_io_pcie_soc_ip.csr144039S_31'b1: Indicates that the head flit is a start of packet. This also indicates that this input VC 3 has not yet acquired its corresponding output VC1'b0: Indicates that the head flit is not a start of packet. Also indicates that this input VC 3 has already acquired the VC on the output port28280x0RB_3PCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_B_3_SETns_noc_io_pcie_soc_ip.csr144053B_31'b1: Indicates that the head flit of the VC 3 is of the 'QoS Barrier' type1'b0: Indicates that the head flit of the VC 3 is of the 'QoS Normal' type29290x0RF_3PCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_F_3_SETns_noc_io_pcie_soc_ip.csr144064F_31'b1: Buffer full in VC 330300x0RV_3PCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_MSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_LSBPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_RANGEPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_RESETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_GETPCIE_NOC_ROUTER_1_6_6_RIVCS_K_V_3_SETns_noc_io_pcie_soc_ip.csr144075V_31'b1: Head flit valid (buffer ready) in VC 331310x0Rregisterpcie_noc.router_1_6_6_rovcs_hrouter_1_6_6_rovcs_hPCIE_NOC_ROUTER_1_6_6_ROVCS_H_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_H_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_H_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr144337R1_6 register rovcs_h0x44040R0x00000001Pcie_noc_router_1_6_6_rovcs_hThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_0_SETns_noc_io_pcie_soc_ip.csr144100CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_0_SETns_noc_io_pcie_soc_ip.csr144114CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_0_SETns_noc_io_pcie_soc_ip.csr144129VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_0_SETns_noc_io_pcie_soc_ip.csr144140RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_0_SETns_noc_io_pcie_soc_ip.csr144150UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_1_SETns_noc_io_pcie_soc_ip.csr144162CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_1_SETns_noc_io_pcie_soc_ip.csr144176CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_1_SETns_noc_io_pcie_soc_ip.csr144191VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_1_SETns_noc_io_pcie_soc_ip.csr144202RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_1_SETns_noc_io_pcie_soc_ip.csr144212UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_2_SETns_noc_io_pcie_soc_ip.csr144224CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_2_SETns_noc_io_pcie_soc_ip.csr144238CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_2_SETns_noc_io_pcie_soc_ip.csr144253VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_2_SETns_noc_io_pcie_soc_ip.csr144264RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_2_SETns_noc_io_pcie_soc_ip.csr144274UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CF_3_SETns_noc_io_pcie_soc_ip.csr144286CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_CE_3_SETns_noc_io_pcie_soc_ip.csr144300CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_VB_3_SETns_noc_io_pcie_soc_ip.csr144315VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_RSV_3_SETns_noc_io_pcie_soc_ip.csr144326RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_H_UNSD_3_SETns_noc_io_pcie_soc_ip.csr144336UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_erouter_1_6_6_rovcs_ePCIE_NOC_ROUTER_1_6_6_ROVCS_E_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_E_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_E_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr144598R1_6 register rovcs_e0x44048R0x00000001Pcie_noc_router_1_6_6_rovcs_eThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_0_SETns_noc_io_pcie_soc_ip.csr144361CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_0_SETns_noc_io_pcie_soc_ip.csr144375CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_0_SETns_noc_io_pcie_soc_ip.csr144390VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_0_SETns_noc_io_pcie_soc_ip.csr144401RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_0_SETns_noc_io_pcie_soc_ip.csr144411UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_1_SETns_noc_io_pcie_soc_ip.csr144423CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_1_SETns_noc_io_pcie_soc_ip.csr144437CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_1_SETns_noc_io_pcie_soc_ip.csr144452VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_1_SETns_noc_io_pcie_soc_ip.csr144463RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_1_SETns_noc_io_pcie_soc_ip.csr144473UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_2_SETns_noc_io_pcie_soc_ip.csr144485CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_2_SETns_noc_io_pcie_soc_ip.csr144499CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_2_SETns_noc_io_pcie_soc_ip.csr144514VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_2_SETns_noc_io_pcie_soc_ip.csr144525RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_2_SETns_noc_io_pcie_soc_ip.csr144535UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CF_3_SETns_noc_io_pcie_soc_ip.csr144547CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_CE_3_SETns_noc_io_pcie_soc_ip.csr144561CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_VB_3_SETns_noc_io_pcie_soc_ip.csr144576VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_RSV_3_SETns_noc_io_pcie_soc_ip.csr144587RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_E_UNSD_3_SETns_noc_io_pcie_soc_ip.csr144597UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_srouter_1_6_6_rovcs_sPCIE_NOC_ROUTER_1_6_6_ROVCS_S_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_S_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_S_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr144859R1_6 register rovcs_s0x44050R0x00000001Pcie_noc_router_1_6_6_rovcs_sThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_0_SETns_noc_io_pcie_soc_ip.csr144622CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_0_SETns_noc_io_pcie_soc_ip.csr144636CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_0_SETns_noc_io_pcie_soc_ip.csr144651VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_0_SETns_noc_io_pcie_soc_ip.csr144662RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_0_SETns_noc_io_pcie_soc_ip.csr144672UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_1_SETns_noc_io_pcie_soc_ip.csr144684CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_1_SETns_noc_io_pcie_soc_ip.csr144698CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_1_SETns_noc_io_pcie_soc_ip.csr144713VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_1_SETns_noc_io_pcie_soc_ip.csr144724RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_1_SETns_noc_io_pcie_soc_ip.csr144734UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_2_SETns_noc_io_pcie_soc_ip.csr144746CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_2_SETns_noc_io_pcie_soc_ip.csr144760CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_2_SETns_noc_io_pcie_soc_ip.csr144775VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_2_SETns_noc_io_pcie_soc_ip.csr144786RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_2_SETns_noc_io_pcie_soc_ip.csr144796UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CF_3_SETns_noc_io_pcie_soc_ip.csr144808CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_CE_3_SETns_noc_io_pcie_soc_ip.csr144822CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_VB_3_SETns_noc_io_pcie_soc_ip.csr144837VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_RSV_3_SETns_noc_io_pcie_soc_ip.csr144848RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_S_UNSD_3_SETns_noc_io_pcie_soc_ip.csr144858UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_wrouter_1_6_6_rovcs_wPCIE_NOC_ROUTER_1_6_6_ROVCS_W_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_W_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_W_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr145120R1_6 register rovcs_w0x44058R0x00000101Pcie_noc_router_1_6_6_rovcs_wThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_0_SETns_noc_io_pcie_soc_ip.csr144883CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_0_SETns_noc_io_pcie_soc_ip.csr144897CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_0_SETns_noc_io_pcie_soc_ip.csr144912VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_0_SETns_noc_io_pcie_soc_ip.csr144923RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_0_SETns_noc_io_pcie_soc_ip.csr144933UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_1_SETns_noc_io_pcie_soc_ip.csr144945CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x1RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_1_SETns_noc_io_pcie_soc_ip.csr144959CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_1_SETns_noc_io_pcie_soc_ip.csr144974VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_1_SETns_noc_io_pcie_soc_ip.csr144985RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_1_SETns_noc_io_pcie_soc_ip.csr144995UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_2_SETns_noc_io_pcie_soc_ip.csr145007CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_2_SETns_noc_io_pcie_soc_ip.csr145021CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_2_SETns_noc_io_pcie_soc_ip.csr145036VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_2_SETns_noc_io_pcie_soc_ip.csr145047RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_2_SETns_noc_io_pcie_soc_ip.csr145057UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CF_3_SETns_noc_io_pcie_soc_ip.csr145069CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_CE_3_SETns_noc_io_pcie_soc_ip.csr145083CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_VB_3_SETns_noc_io_pcie_soc_ip.csr145098VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_RSV_3_SETns_noc_io_pcie_soc_ip.csr145109RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_W_UNSD_3_SETns_noc_io_pcie_soc_ip.csr145119UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_nrouter_1_6_6_rovcs_nPCIE_NOC_ROUTER_1_6_6_ROVCS_N_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_N_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_N_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr145381R1_6 register rovcs_n0x44060R0x00000001Pcie_noc_router_1_6_6_rovcs_nThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_0_SETns_noc_io_pcie_soc_ip.csr145144CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_0_SETns_noc_io_pcie_soc_ip.csr145158CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_0_SETns_noc_io_pcie_soc_ip.csr145173VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_0_SETns_noc_io_pcie_soc_ip.csr145184RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_0_SETns_noc_io_pcie_soc_ip.csr145194UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_1_SETns_noc_io_pcie_soc_ip.csr145206CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_1_SETns_noc_io_pcie_soc_ip.csr145220CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_1_SETns_noc_io_pcie_soc_ip.csr145235VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_1_SETns_noc_io_pcie_soc_ip.csr145246RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_1_SETns_noc_io_pcie_soc_ip.csr145256UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_2_SETns_noc_io_pcie_soc_ip.csr145268CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_2_SETns_noc_io_pcie_soc_ip.csr145282CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_2_SETns_noc_io_pcie_soc_ip.csr145297VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_2_SETns_noc_io_pcie_soc_ip.csr145308RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_2_SETns_noc_io_pcie_soc_ip.csr145318UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CF_3_SETns_noc_io_pcie_soc_ip.csr145330CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_CE_3_SETns_noc_io_pcie_soc_ip.csr145344CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_VB_3_SETns_noc_io_pcie_soc_ip.csr145359VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_RSV_3_SETns_noc_io_pcie_soc_ip.csr145370RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_N_UNSD_3_SETns_noc_io_pcie_soc_ip.csr145380UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_irouter_1_6_6_rovcs_iPCIE_NOC_ROUTER_1_6_6_ROVCS_I_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_I_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_I_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr145642R1_6 register rovcs_i0x44068R0x00000001Pcie_noc_router_1_6_6_rovcs_iThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_0_SETns_noc_io_pcie_soc_ip.csr145405CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_0_SETns_noc_io_pcie_soc_ip.csr145419CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_0_SETns_noc_io_pcie_soc_ip.csr145434VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_0_SETns_noc_io_pcie_soc_ip.csr145445RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_0_SETns_noc_io_pcie_soc_ip.csr145455UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_1_SETns_noc_io_pcie_soc_ip.csr145467CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_1_SETns_noc_io_pcie_soc_ip.csr145481CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_1_SETns_noc_io_pcie_soc_ip.csr145496VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_1_SETns_noc_io_pcie_soc_ip.csr145507RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_1_SETns_noc_io_pcie_soc_ip.csr145517UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_2_SETns_noc_io_pcie_soc_ip.csr145529CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_2_SETns_noc_io_pcie_soc_ip.csr145543CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_2_SETns_noc_io_pcie_soc_ip.csr145558VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_2_SETns_noc_io_pcie_soc_ip.csr145569RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_2_SETns_noc_io_pcie_soc_ip.csr145579UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CF_3_SETns_noc_io_pcie_soc_ip.csr145591CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_CE_3_SETns_noc_io_pcie_soc_ip.csr145605CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_VB_3_SETns_noc_io_pcie_soc_ip.csr145620VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_RSV_3_SETns_noc_io_pcie_soc_ip.csr145631RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_I_UNSD_3_SETns_noc_io_pcie_soc_ip.csr145641UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_jrouter_1_6_6_rovcs_jPCIE_NOC_ROUTER_1_6_6_ROVCS_J_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_J_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_J_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr145903R1_6 register rovcs_j0x44070R0x00000001Pcie_noc_router_1_6_6_rovcs_jThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_0_SETns_noc_io_pcie_soc_ip.csr145666CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_0_SETns_noc_io_pcie_soc_ip.csr145680CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_0_SETns_noc_io_pcie_soc_ip.csr145695VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_0_SETns_noc_io_pcie_soc_ip.csr145706RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_0_SETns_noc_io_pcie_soc_ip.csr145716UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_1_SETns_noc_io_pcie_soc_ip.csr145728CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_1_SETns_noc_io_pcie_soc_ip.csr145742CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_1_SETns_noc_io_pcie_soc_ip.csr145757VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_1_SETns_noc_io_pcie_soc_ip.csr145768RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_1_SETns_noc_io_pcie_soc_ip.csr145778UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_2_SETns_noc_io_pcie_soc_ip.csr145790CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_2_SETns_noc_io_pcie_soc_ip.csr145804CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_2_SETns_noc_io_pcie_soc_ip.csr145819VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_2_SETns_noc_io_pcie_soc_ip.csr145830RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_2_SETns_noc_io_pcie_soc_ip.csr145840UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CF_3_SETns_noc_io_pcie_soc_ip.csr145852CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_CE_3_SETns_noc_io_pcie_soc_ip.csr145866CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_VB_3_SETns_noc_io_pcie_soc_ip.csr145881VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_RSV_3_SETns_noc_io_pcie_soc_ip.csr145892RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_J_UNSD_3_SETns_noc_io_pcie_soc_ip.csr145902UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rovcs_krouter_1_6_6_rovcs_kPCIE_NOC_ROUTER_1_6_6_ROVCS_K_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_K_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROVCS_K_OFFSETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146164R1_6 register rovcs_k0x44078R0x00000001Pcie_noc_router_1_6_6_rovcs_kThis register indicates the current status of one of the output ports of a router. Each register tracks the status of up to 4 virtual channels for the output port. There are 8 ROVCS per router, one for each router's output port (only 5 are active registers, while the other 3 are reserved).falsefalsefalsefalseCF_0PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_0_SETns_noc_io_pcie_soc_ip.csr145927CF_01'b1: Indicates that the credit level with this VC 0 is at the maximum provisioned value.000x1RCE_0PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_0_SETns_noc_io_pcie_soc_ip.csr145941CE_01'b1: Indicates that this output VC 0 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.110x0RVB_0PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_0_SETns_noc_io_pcie_soc_ip.csr145956VB_01'b1: Indicates that this output VC 0 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 0 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.220x0RRSV_0PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_0_SETns_noc_io_pcie_soc_ip.csr145967RSV_0Reserved330x0RUNSD_0PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_0_SETns_noc_io_pcie_soc_ip.csr145977UNSD_0740x0RCF_1PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_1_SETns_noc_io_pcie_soc_ip.csr145989CF_11'b1: Indicates that the credit level with this VC 1 is at the maximum provisioned value.880x0RCE_1PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_1_SETns_noc_io_pcie_soc_ip.csr146003CE_11'b1: Indicates that this output VC 1 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.990x0RVB_1PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_1_SETns_noc_io_pcie_soc_ip.csr146018VB_11'b1: Indicates that this output VC 1 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 1 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.10100x0RRSV_1PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_1_SETns_noc_io_pcie_soc_ip.csr146029RSV_1Reserved11110x0RUNSD_1PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_1_SETns_noc_io_pcie_soc_ip.csr146039UNSD_115120x0RCF_2PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_2_SETns_noc_io_pcie_soc_ip.csr146051CF_21'b1: Indicates that the credit level with this VC 2 is at the maximum provisioned value.16160x0RCE_2PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_2_SETns_noc_io_pcie_soc_ip.csr146065CE_21'b1: Indicates that this output VC 2 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.17170x0RVB_2PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_2_SETns_noc_io_pcie_soc_ip.csr146080VB_21'b1: Indicates that this output VC 2 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 2 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.18180x0RRSV_2PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_2_SETns_noc_io_pcie_soc_ip.csr146091RSV_2Reserved19190x0RUNSD_2PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_2_SETns_noc_io_pcie_soc_ip.csr146101UNSD_223200x0RCF_3PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CF_3_SETns_noc_io_pcie_soc_ip.csr146113CF_31'b1: Indicates that the credit level with this VC 3 is at the maximum provisioned value.24240x0RCE_3PCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_CE_3_SETns_noc_io_pcie_soc_ip.csr146127CE_31'b1: Indicates that this output VC 3 has no credit for transmission of flits to the downstream link.1'b0: Indicates that credits are available for transmission to downstream link.25250x0RVB_3PCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_VB_3_SETns_noc_io_pcie_soc_ip.csr146142VB_31'b1: Indicates that this output VC 3 is currently locked to the corresponding VC on one of the input ports.1'b0: Indicates that this output VC 3 is free and can be acquired by the corresponding VC on one of the input port for the transmission of a packet.26260x0RRSV_3PCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_RSV_3_SETns_noc_io_pcie_soc_ip.csr146153RSV_3Reserved27270x0RUNSD_3PCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_WIDTHPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_MSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_LSBPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_RANGEPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_RESETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_GETPCIE_NOC_ROUTER_1_6_6_ROVCS_K_UNSD_3_SETns_noc_io_pcie_soc_ip.csr146163UNSD_331280x0Rregisterpcie_noc.router_1_6_6_rerouter_1_6_6_rePCIE_NOC_ROUTER_1_6_6_RE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RE_OFFSETPCIE_NOC_ROUTER_1_6_6_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146338R1_6 register re0x44080R/W0x00000000Pcie_noc_router_1_6_6_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_1_6_6_RE_OVFI_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_OVFI_MSBPCIE_NOC_ROUTER_1_6_6_RE_OVFI_LSBPCIE_NOC_ROUTER_1_6_6_RE_OVFI_RANGEPCIE_NOC_ROUTER_1_6_6_RE_OVFI_RESETPCIE_NOC_ROUTER_1_6_6_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_OVFI_GETPCIE_NOC_ROUTER_1_6_6_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr146190OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_1_6_6_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr146201CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_1_6_6_RE_OVFO_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_OVFO_MSBPCIE_NOC_ROUTER_1_6_6_RE_OVFO_LSBPCIE_NOC_ROUTER_1_6_6_RE_OVFO_RANGEPCIE_NOC_ROUTER_1_6_6_RE_OVFO_RESETPCIE_NOC_ROUTER_1_6_6_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_OVFO_GETPCIE_NOC_ROUTER_1_6_6_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr146215OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_1_6_6_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr146226UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_1_6_6_RE_PGE_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_PGE_MSBPCIE_NOC_ROUTER_1_6_6_RE_PGE_LSBPCIE_NOC_ROUTER_1_6_6_RE_PGE_RANGEPCIE_NOC_ROUTER_1_6_6_RE_PGE_RESETPCIE_NOC_ROUTER_1_6_6_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_PGE_GETPCIE_NOC_ROUTER_1_6_6_RE_PGE_SETns_noc_io_pcie_soc_ip.csr146238PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_1_6_6_RE_NLU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_NLU_MSBPCIE_NOC_ROUTER_1_6_6_RE_NLU_LSBPCIE_NOC_ROUTER_1_6_6_RE_NLU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_NLU_RESETPCIE_NOC_ROUTER_1_6_6_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_NLU_GETPCIE_NOC_ROUTER_1_6_6_RE_NLU_SETns_noc_io_pcie_soc_ip.csr146249NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_1_6_6_RE_ELU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_ELU_MSBPCIE_NOC_ROUTER_1_6_6_RE_ELU_LSBPCIE_NOC_ROUTER_1_6_6_RE_ELU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_ELU_RESETPCIE_NOC_ROUTER_1_6_6_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_ELU_GETPCIE_NOC_ROUTER_1_6_6_RE_ELU_SETns_noc_io_pcie_soc_ip.csr146260ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_1_6_6_RE_WLU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_WLU_MSBPCIE_NOC_ROUTER_1_6_6_RE_WLU_LSBPCIE_NOC_ROUTER_1_6_6_RE_WLU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_WLU_RESETPCIE_NOC_ROUTER_1_6_6_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_WLU_GETPCIE_NOC_ROUTER_1_6_6_RE_WLU_SETns_noc_io_pcie_soc_ip.csr146271WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_1_6_6_RE_SLU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_SLU_MSBPCIE_NOC_ROUTER_1_6_6_RE_SLU_LSBPCIE_NOC_ROUTER_1_6_6_RE_SLU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_SLU_RESETPCIE_NOC_ROUTER_1_6_6_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_SLU_GETPCIE_NOC_ROUTER_1_6_6_RE_SLU_SETns_noc_io_pcie_soc_ip.csr146282SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_1_6_6_RE_HLU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_HLU_MSBPCIE_NOC_ROUTER_1_6_6_RE_HLU_LSBPCIE_NOC_ROUTER_1_6_6_RE_HLU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_HLU_RESETPCIE_NOC_ROUTER_1_6_6_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_HLU_GETPCIE_NOC_ROUTER_1_6_6_RE_HLU_SETns_noc_io_pcie_soc_ip.csr146293HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_1_6_6_RE_ILU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_ILU_MSBPCIE_NOC_ROUTER_1_6_6_RE_ILU_LSBPCIE_NOC_ROUTER_1_6_6_RE_ILU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_ILU_RESETPCIE_NOC_ROUTER_1_6_6_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_ILU_GETPCIE_NOC_ROUTER_1_6_6_RE_ILU_SETns_noc_io_pcie_soc_ip.csr146304ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_1_6_6_RE_JLU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_JLU_MSBPCIE_NOC_ROUTER_1_6_6_RE_JLU_LSBPCIE_NOC_ROUTER_1_6_6_RE_JLU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_JLU_RESETPCIE_NOC_ROUTER_1_6_6_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_JLU_GETPCIE_NOC_ROUTER_1_6_6_RE_JLU_SETns_noc_io_pcie_soc_ip.csr146315JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_1_6_6_RE_KLU_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_KLU_MSBPCIE_NOC_ROUTER_1_6_6_RE_KLU_LSBPCIE_NOC_ROUTER_1_6_6_RE_KLU_RANGEPCIE_NOC_ROUTER_1_6_6_RE_KLU_RESETPCIE_NOC_ROUTER_1_6_6_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_KLU_GETPCIE_NOC_ROUTER_1_6_6_RE_KLU_SETns_noc_io_pcie_soc_ip.csr146326KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_1_6_6_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr146337UNSD_31_1431170x0000Rregisterpcie_noc.router_1_6_6_remrouter_1_6_6_remPCIE_NOC_ROUTER_1_6_6_REM_ADDRESSPCIE_NOC_ROUTER_1_6_6_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_REM_OFFSETPCIE_NOC_ROUTER_1_6_6_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146511R1_6 register rem0x44088R/W0x0001fe00Pcie_noc_router_1_6_6_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_MSBPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_LSBPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_RANGEPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_RESETPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_GETPCIE_NOC_ROUTER_1_6_6_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr146364OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_1_6_6_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr146375CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_MSBPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_LSBPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_RANGEPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_RESETPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_GETPCIE_NOC_ROUTER_1_6_6_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr146389OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_1_6_6_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr146400UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_1_6_6_REM_PGM_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_PGM_MSBPCIE_NOC_ROUTER_1_6_6_REM_PGM_LSBPCIE_NOC_ROUTER_1_6_6_REM_PGM_RANGEPCIE_NOC_ROUTER_1_6_6_REM_PGM_RESETPCIE_NOC_ROUTER_1_6_6_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_PGM_GETPCIE_NOC_ROUTER_1_6_6_REM_PGM_SETns_noc_io_pcie_soc_ip.csr146411PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_1_6_6_REM_MN_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MN_MSBPCIE_NOC_ROUTER_1_6_6_REM_MN_LSBPCIE_NOC_ROUTER_1_6_6_REM_MN_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MN_RESETPCIE_NOC_ROUTER_1_6_6_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MN_GETPCIE_NOC_ROUTER_1_6_6_REM_MN_SETns_noc_io_pcie_soc_ip.csr146422MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_1_6_6_REM_ME_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_ME_MSBPCIE_NOC_ROUTER_1_6_6_REM_ME_LSBPCIE_NOC_ROUTER_1_6_6_REM_ME_RANGEPCIE_NOC_ROUTER_1_6_6_REM_ME_RESETPCIE_NOC_ROUTER_1_6_6_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_ME_GETPCIE_NOC_ROUTER_1_6_6_REM_ME_SETns_noc_io_pcie_soc_ip.csr146433ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_1_6_6_REM_MW_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MW_MSBPCIE_NOC_ROUTER_1_6_6_REM_MW_LSBPCIE_NOC_ROUTER_1_6_6_REM_MW_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MW_RESETPCIE_NOC_ROUTER_1_6_6_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MW_GETPCIE_NOC_ROUTER_1_6_6_REM_MW_SETns_noc_io_pcie_soc_ip.csr146444MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_1_6_6_REM_MS_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MS_MSBPCIE_NOC_ROUTER_1_6_6_REM_MS_LSBPCIE_NOC_ROUTER_1_6_6_REM_MS_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MS_RESETPCIE_NOC_ROUTER_1_6_6_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MS_GETPCIE_NOC_ROUTER_1_6_6_REM_MS_SETns_noc_io_pcie_soc_ip.csr146455MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_1_6_6_REM_MH_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MH_MSBPCIE_NOC_ROUTER_1_6_6_REM_MH_LSBPCIE_NOC_ROUTER_1_6_6_REM_MH_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MH_RESETPCIE_NOC_ROUTER_1_6_6_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MH_GETPCIE_NOC_ROUTER_1_6_6_REM_MH_SETns_noc_io_pcie_soc_ip.csr146466MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_1_6_6_REM_MI_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MI_MSBPCIE_NOC_ROUTER_1_6_6_REM_MI_LSBPCIE_NOC_ROUTER_1_6_6_REM_MI_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MI_RESETPCIE_NOC_ROUTER_1_6_6_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MI_GETPCIE_NOC_ROUTER_1_6_6_REM_MI_SETns_noc_io_pcie_soc_ip.csr146477MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_1_6_6_REM_MJ_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MJ_MSBPCIE_NOC_ROUTER_1_6_6_REM_MJ_LSBPCIE_NOC_ROUTER_1_6_6_REM_MJ_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MJ_RESETPCIE_NOC_ROUTER_1_6_6_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MJ_GETPCIE_NOC_ROUTER_1_6_6_REM_MJ_SETns_noc_io_pcie_soc_ip.csr146488MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_1_6_6_REM_MK_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_MK_MSBPCIE_NOC_ROUTER_1_6_6_REM_MK_LSBPCIE_NOC_ROUTER_1_6_6_REM_MK_RANGEPCIE_NOC_ROUTER_1_6_6_REM_MK_RESETPCIE_NOC_ROUTER_1_6_6_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_MK_GETPCIE_NOC_ROUTER_1_6_6_REM_MK_SETns_noc_io_pcie_soc_ip.csr146499MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_1_6_6_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr146510UNSD_31_1431170x0000Rregisterpcie_noc.router_1_6_6_reccrouter_1_6_6_reccPCIE_NOC_ROUTER_1_6_6_RECC_ADDRESSPCIE_NOC_ROUTER_1_6_6_RECC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RECC_OFFSETPCIE_NOC_ROUTER_1_6_6_RECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146596R1_6 register recc0x44090R/W0x00000000Pcie_noc_router_1_6_6_reccThis register is used to select which hardware events will increment the event counter.falsefalsefalsefalseIVCPCIE_NOC_ROUTER_1_6_6_RECC_IVC_WIDTHPCIE_NOC_ROUTER_1_6_6_RECC_IVC_MSBPCIE_NOC_ROUTER_1_6_6_RECC_IVC_LSBPCIE_NOC_ROUTER_1_6_6_RECC_IVC_RANGEPCIE_NOC_ROUTER_1_6_6_RECC_IVC_RESETPCIE_NOC_ROUTER_1_6_6_RECC_IVC_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RECC_IVC_GETPCIE_NOC_ROUTER_1_6_6_RECC_IVC_SETns_noc_io_pcie_soc_ip.csr146532IVC11: Input VC 310: Input VC 201: Input VC 100: Input VC 0100x0R/WUNSD_3_2PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_WIDTHPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_MSBPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_LSBPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_RANGEPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_RESETPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_GETPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_3_2_SETns_noc_io_pcie_soc_ip.csr146543UNSD_3_2320x0RINPPCIE_NOC_ROUTER_1_6_6_RECC_INP_WIDTHPCIE_NOC_ROUTER_1_6_6_RECC_INP_MSBPCIE_NOC_ROUTER_1_6_6_RECC_INP_LSBPCIE_NOC_ROUTER_1_6_6_RECC_INP_RANGEPCIE_NOC_ROUTER_1_6_6_RECC_INP_RESETPCIE_NOC_ROUTER_1_6_6_RECC_INP_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RECC_INP_GETPCIE_NOC_ROUTER_1_6_6_RECC_INP_SETns_noc_io_pcie_soc_ip.csr146554INPInput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_GETPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr146565UNSD_7_7770x0REVTPCIE_NOC_ROUTER_1_6_6_RECC_EVT_WIDTHPCIE_NOC_ROUTER_1_6_6_RECC_EVT_MSBPCIE_NOC_ROUTER_1_6_6_RECC_EVT_LSBPCIE_NOC_ROUTER_1_6_6_RECC_EVT_RANGEPCIE_NOC_ROUTER_1_6_6_RECC_EVT_RESETPCIE_NOC_ROUTER_1_6_6_RECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RECC_EVT_GETPCIE_NOC_ROUTER_1_6_6_RECC_EVT_SETns_noc_io_pcie_soc_ip.csr146584EVT11: Generates count event when VC has valid data, but is stalled10: Generates count event on every flit received for the selected input port and selected input VCs, this can be used to count total flits received on a router input port01: Generates count event on every EOP received for the selected input port and selected input VCs, this can be used to count packets received on a router input port00: Disable980x0R/WUNSD_31_10PCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_WIDTHPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_MSBPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_LSBPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_RANGEPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_RESETPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_GETPCIE_NOC_ROUTER_1_6_6_RECC_UNSD_31_10_SETns_noc_io_pcie_soc_ip.csr146595UNSD_31_1031100x000000Rregisterpcie_noc.router_1_6_6_recrouter_1_6_6_recPCIE_NOC_ROUTER_1_6_6_REC_ADDRESSPCIE_NOC_ROUTER_1_6_6_REC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_REC_OFFSETPCIE_NOC_ROUTER_1_6_6_REC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146621R1_6 register rec0x44098R/W0x00000000Pcie_noc_router_1_6_6_recThis register holds the event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_GETPCIE_NOC_ROUTER_1_6_6_REC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr146620EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_1_6_6_idrouter_1_6_6_idPCIE_NOC_ROUTER_1_6_6_ID_ADDRESSPCIE_NOC_ROUTER_1_6_6_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ID_OFFSETPCIE_NOC_ROUTER_1_6_6_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146690R1_6 register id0x440A0R0x010000c1Pcie_noc_router_1_6_6_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_1_6_6_ID_LAYER_WIDTHPCIE_NOC_ROUTER_1_6_6_ID_LAYER_MSBPCIE_NOC_ROUTER_1_6_6_ID_LAYER_LSBPCIE_NOC_ROUTER_1_6_6_ID_LAYER_RANGEPCIE_NOC_ROUTER_1_6_6_ID_LAYER_RESETPCIE_NOC_ROUTER_1_6_6_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ID_LAYER_GETPCIE_NOC_ROUTER_1_6_6_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr146646LAYER5-bit identifier of the NoC layer on which this router is located400x01RPOSPCIE_NOC_ROUTER_1_6_6_ID_POS_WIDTHPCIE_NOC_ROUTER_1_6_6_ID_POS_MSBPCIE_NOC_ROUTER_1_6_6_ID_POS_LSBPCIE_NOC_ROUTER_1_6_6_ID_POS_RANGEPCIE_NOC_ROUTER_1_6_6_ID_POS_RESETPCIE_NOC_ROUTER_1_6_6_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ID_POS_GETPCIE_NOC_ROUTER_1_6_6_ID_POS_SETns_noc_io_pcie_soc_ip.csr146657POS16-bit position ID of this router in the NoC2050x0006RZEROPCIE_NOC_ROUTER_1_6_6_ID_ZERO_WIDTHPCIE_NOC_ROUTER_1_6_6_ID_ZERO_MSBPCIE_NOC_ROUTER_1_6_6_ID_ZERO_LSBPCIE_NOC_ROUTER_1_6_6_ID_ZERO_RANGEPCIE_NOC_ROUTER_1_6_6_ID_ZERO_RESETPCIE_NOC_ROUTER_1_6_6_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ID_ZERO_GETPCIE_NOC_ROUTER_1_6_6_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr146668ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_1_6_6_ID_ONE_WIDTHPCIE_NOC_ROUTER_1_6_6_ID_ONE_MSBPCIE_NOC_ROUTER_1_6_6_ID_ONE_LSBPCIE_NOC_ROUTER_1_6_6_ID_ONE_RANGEPCIE_NOC_ROUTER_1_6_6_ID_ONE_RESETPCIE_NOC_ROUTER_1_6_6_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ID_ONE_GETPCIE_NOC_ROUTER_1_6_6_ID_ONE_SETns_noc_io_pcie_soc_ip.csr146679ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_1_6_6_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr146689UNSD_31_2531250x00Rregisterpcie_noc.router_1_6_6_rcgcrouter_1_6_6_rcgcPCIE_NOC_ROUTER_1_6_6_RCGC_ADDRESSPCIE_NOC_ROUTER_1_6_6_RCGC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RCGC_OFFSETPCIE_NOC_ROUTER_1_6_6_RCGC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146716R1_6 register rcgc0x440A8R/W0x00000064Pcie_noc_router_1_6_6_rcgcProgrammable interval used by coarse clock gating logic in routers.This count determines the consecutive number of idle cycle after which a router output port initiates coarse clock gating of the local port clock and de-asserts the 'busy' signal to the downstream router. This signal indicates inactivity to the downstream router and allows it to initiate coarse clock gating of its corresponding input port.falsefalsefalsefalseHYSTERESIS_COUNTERPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_WIDTHPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_MSBPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_LSBPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_RANGEPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_RESETPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_GETPCIE_NOC_ROUTER_1_6_6_RCGC_HYSTERESIS_COUNTER_SETns_noc_io_pcie_soc_ip.csr146715HYSTERESIS_COUNTERHysteresis counter3100x00000064R/Wregisterpcie_noc.router_1_6_6_rcgorouter_1_6_6_rcgoPCIE_NOC_ROUTER_1_6_6_RCGO_ADDRESSPCIE_NOC_ROUTER_1_6_6_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_RCGO_OFFSETPCIE_NOC_ROUTER_1_6_6_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr146755R1_6 register rcgo0x440B0R/W0x00000000Pcie_noc_router_1_6_6_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_MSBPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_LSBPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_RANGEPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_RESETPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_GETPCIE_NOC_ROUTER_1_6_6_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr146743FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_1_6_6_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr146754UNSD_31_13110x00000000Rregisterpcie_noc.router_1_6_6_p0_rperrrouter_1_6_6_p0_rperrPCIE_NOC_ROUTER_1_6_6_P0_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P0_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P0_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr147046R1_6 register p0_rperr0x440B8R/W0x00000000Pcie_noc_router_1_6_6_p0_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_SETns_noc_io_pcie_soc_ip.csr146798D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr146809SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr146820PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr146831RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr146842CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr146853UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr146864D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr146875SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr146887PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr146898RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr146910D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr146922SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr146935PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr146947RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr146959D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr146971SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr146984PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr146996RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr147008D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr147020SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr147033PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr147045RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p1_rperrrouter_1_6_6_p1_rperrPCIE_NOC_ROUTER_1_6_6_P1_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P1_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P1_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr147333R1_6 register p1_rperr0x440C0R/W0x00000000Pcie_noc_router_1_6_6_p1_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_SETns_noc_io_pcie_soc_ip.csr147089D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr147100SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr147111PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr147122RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr147133CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr147144UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr147155D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr147166SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr147178PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr147189RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr147200D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr147211SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr147223PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr147234RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr147246D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr147258SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr147271PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr147283RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr147295D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr147307SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr147320PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr147332RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p2_rperrrouter_1_6_6_p2_rperrPCIE_NOC_ROUTER_1_6_6_P2_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P2_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P2_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr147624R1_6 register p2_rperr0x440C8R/W0x00000000Pcie_noc_router_1_6_6_p2_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_SETns_noc_io_pcie_soc_ip.csr147376D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr147387SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr147398PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr147409RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr147420CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr147431UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr147442D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr147453SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr147465PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr147476RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr147488D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr147500SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr147513PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr147525RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr147537D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr147549SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr147562PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr147574RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr147586D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr147598SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr147611PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr147623RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p3_rperrrouter_1_6_6_p3_rperrPCIE_NOC_ROUTER_1_6_6_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P3_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr147915R1_6 register p3_rperr0x440D0R/W0x00000000Pcie_noc_router_1_6_6_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr147667D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr147678SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr147689PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr147700RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr147711CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr147722UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr147733D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr147744SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr147756PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr147767RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr147779D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr147791SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr147804PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr147816RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr147828D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr147840SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr147853PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr147865RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr147877D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr147889SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr147902PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr147914RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p4_rperrrouter_1_6_6_p4_rperrPCIE_NOC_ROUTER_1_6_6_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P4_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr148206R1_6 register p4_rperr0x440D8R/W0x00000000Pcie_noc_router_1_6_6_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr147958D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr147969SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr147980PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr147991RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr148002CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr148013UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr148025D_01'b1: Parity Error in VC 0 Buffer Data16160x0RSB_0PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr148037SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0RPK_0PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr148050PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0RRI_0PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr148062RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0RD_1PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr148073D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr148084SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr148096PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr148107RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr148119D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr148131SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr148144PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr148156RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr148168D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr148180SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr148193PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr148205RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p5_rperrrouter_1_6_6_p5_rperrPCIE_NOC_ROUTER_1_6_6_P5_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P5_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P5_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr148497R1_6 register p5_rperr0x440E0R/W0x00000000Pcie_noc_router_1_6_6_p5_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_SETns_noc_io_pcie_soc_ip.csr148249D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr148260SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr148271PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr148282RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr148293CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr148304UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr148316D_01'b1: Parity Error in VC 0 Buffer Data16160x0RSB_0PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr148328SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0RPK_0PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr148341PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0RRI_0PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr148353RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0RD_1PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr148364D_11'b1: Parity Error in VC 1 Buffer Data20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr148375SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr148387PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr148398RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr148410D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr148422SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr148435PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr148447RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr148459D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr148471SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr148484PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr148496RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p6_rperrrouter_1_6_6_p6_rperrPCIE_NOC_ROUTER_1_6_6_P6_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P6_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P6_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr148788R1_6 register p6_rperr0x440E8R/W0x00000000Pcie_noc_router_1_6_6_p6_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_SETns_noc_io_pcie_soc_ip.csr148540D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr148551SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr148562PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr148573RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr148584CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr148595UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr148606D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr148617SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr148629PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr148640RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr148652D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr148664SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr148677PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr148689RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr148701D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr148713SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr148726PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr148738RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr148750D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr148762SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr148775PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr148787RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p7_rperrrouter_1_6_6_p7_rperrPCIE_NOC_ROUTER_1_6_6_P7_RPERR_ADDRESSPCIE_NOC_ROUTER_1_6_6_P7_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P7_RPERR_OFFSETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr149079R1_6 register p7_rperr0x440F0R/W0x00000000Pcie_noc_router_1_6_6_p7_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_SETns_noc_io_pcie_soc_ip.csr148831D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr148842SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr148853PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr148864RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr148875CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr148886UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr148897D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr148908SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr148920PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr148931RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr148943D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr148955SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr148968PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr148980RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr148992D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr149004SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr149017PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr149029RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr149041D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr149053SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr149066PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr149078RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_1_6_6_p0_rperrmrouter_1_6_6_p0_rperrmPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr149337R1_6 register p0_rperrm0x440F8R/W0x00000000Pcie_noc_router_1_6_6_p0_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr149101DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr149112SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr149123PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr149134RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr149145CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr149156UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr149167D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr149178SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr149190PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr149201RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr149212D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr149223SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr149235PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr149246RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr149257D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr149268SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr149280PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr149291RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr149302D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr149313SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr149325PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P0_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr149336RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p1_rperrmrouter_1_6_6_p1_rperrmPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr149595R1_6 register p1_rperrm0x44100R/W0x00000000Pcie_noc_router_1_6_6_p1_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr149359DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr149370SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr149381PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr149392RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr149403CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr149414UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr149425D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr149436SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr149448PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr149459RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr149470D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr149481SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr149493PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr149504RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr149515D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr149526SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr149538PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr149549RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr149560D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr149571SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr149583PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P1_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr149594RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p2_rperrmrouter_1_6_6_p2_rperrmPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr149853R1_6 register p2_rperrm0x44108R/W0x00000000Pcie_noc_router_1_6_6_p2_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr149617DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr149628SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr149639PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr149650RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr149661CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr149672UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr149683D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr149694SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr149706PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr149717RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr149728D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr149739SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr149751PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr149762RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr149773D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr149784SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr149796PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr149807RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr149818D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr149829SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr149841PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P2_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr149852RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p3_rperrmrouter_1_6_6_p3_rperrmPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr150111R1_6 register p3_rperrm0x44110R/W0x00000000Pcie_noc_router_1_6_6_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr149875DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr149886SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr149897PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr149908RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr149919CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr149930UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr149941D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr149952SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr149964PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr149975RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr149986D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr149997SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr150009PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr150020RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr150031D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr150042SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr150054PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr150065RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr150076D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr150087SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr150099PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr150110RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p4_rperrmrouter_1_6_6_p4_rperrmPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr150369R1_6 register p4_rperrm0x44118R/W0x00000000Pcie_noc_router_1_6_6_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr150133DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr150144SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr150155PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr150166RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr150177CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr150188UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr150199D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr150210SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr150222PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr150233RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr150244D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr150255SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr150267PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr150278RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr150289D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr150300SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr150312PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr150323RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr150334D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr150345SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr150357PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr150368RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p5_rperrmrouter_1_6_6_p5_rperrmPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr150627R1_6 register p5_rperrm0x44120R/W0x00000000Pcie_noc_router_1_6_6_p5_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr150391DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr150402SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr150413PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr150424RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr150435CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr150446UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr150457D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr150468SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr150480PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr150491RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr150502D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr150513SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr150525PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr150536RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr150547D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr150558SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr150570PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr150581RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr150592D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr150603SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr150615PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P5_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr150626RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p6_rperrmrouter_1_6_6_p6_rperrmPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr150885R1_6 register p6_rperrm0x44128R/W0x00000000Pcie_noc_router_1_6_6_p6_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr150649DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr150660SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr150671PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr150682RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr150693CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr150704UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr150715D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr150726SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr150738PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr150749RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr150760D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr150771SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr150783PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr150794RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr150805D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr150816SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr150828PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr150839RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr150850D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr150861SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr150873PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P6_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr150884RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_p7_rperrmrouter_1_6_6_p7_rperrmPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_ADDRESSPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_OFFSETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151143R1_6 register p7_rperrm0x44130R/W0x00000000Pcie_noc_router_1_6_6_p7_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr150907DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr150918SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr150929PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr150940RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr150951CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr150962UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr150973D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr150984SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr150996PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr151007RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr151018D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr151029SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr151041PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr151052RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr151063D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr151074SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr151086PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr151097RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr151108D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr151119SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr151131PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_GETPCIE_NOC_ROUTER_1_6_6_P7_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr151142RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_1_6_6_roeccrouter_1_6_6_roeccPCIE_NOC_ROUTER_1_6_6_ROECC_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROECC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROECC_OFFSETPCIE_NOC_ROUTER_1_6_6_ROECC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151216R1_6 register roecc0x44138R/W0x00000000Pcie_noc_router_1_6_6_roeccThis register is used to select which hardware events will increment the output event counter.falsefalsefalsefalseOVCPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_WIDTHPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_MSBPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_LSBPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_RANGEPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_RESETPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_GETPCIE_NOC_ROUTER_1_6_6_ROECC_OVC_SETns_noc_io_pcie_soc_ip.csr151161OVCBit map to select output VCs to monitor events on300x0R/WOPPCIE_NOC_ROUTER_1_6_6_ROECC_OP_WIDTHPCIE_NOC_ROUTER_1_6_6_ROECC_OP_MSBPCIE_NOC_ROUTER_1_6_6_ROECC_OP_LSBPCIE_NOC_ROUTER_1_6_6_ROECC_OP_RANGEPCIE_NOC_ROUTER_1_6_6_ROECC_OP_RESETPCIE_NOC_ROUTER_1_6_6_ROECC_OP_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROECC_OP_GETPCIE_NOC_ROUTER_1_6_6_ROECC_OP_SETns_noc_io_pcie_soc_ip.csr151172OPOutput port on which the event is captured640x0R/WUNSD_7_7PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_WIDTHPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_MSBPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_LSBPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_RANGEPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_RESETPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_GETPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_7_7_SETns_noc_io_pcie_soc_ip.csr151183UNSD_7_7770x0REVTPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_WIDTHPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_MSBPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_LSBPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_RANGEPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_RESETPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_GETPCIE_NOC_ROUTER_1_6_6_ROECC_EVT_SETns_noc_io_pcie_soc_ip.csr151204EVT100: Port stalled. Input flits are available for the port, but no output VC has credit011: Generates count event when flits are available to be sent to output VC, but the VC has no credit010: Generates count event on every flit sent on the selected output port and selected outpt VCs, this can be used to count total flits sent on a router output port001: Generates count event on every EOP sent on the selected output port and selected output VCs, this can be used to count packets sent on a router output port000: Disable1080x0R/WUNSD_31_11PCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_WIDTHPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_MSBPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_LSBPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_RANGEPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_RESETPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_GETPCIE_NOC_ROUTER_1_6_6_ROECC_UNSD_31_11_SETns_noc_io_pcie_soc_ip.csr151215UNSD_31_1131110x000000Rregisterpcie_noc.router_1_6_6_roecrouter_1_6_6_roecPCIE_NOC_ROUTER_1_6_6_ROEC_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROEC_BYTE_ADDRESSPCIE_NOC_ROUTER_1_6_6_ROEC_OFFSETPCIE_NOC_ROUTER_1_6_6_ROEC_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151241R1_6 register roec0x44140R/W0x00000000Pcie_noc_router_1_6_6_roecThis register holds the output event counter. The value can be read to determine the current count value. The value can be written to initialize the counter. When events trigger a count, the counter will increment. When the counter increments at its highest value, it will roll over to zero and the overflow will mark the Router output Event Interrupt Status register, which could trigger an interrupt.falsefalsefalsefalseEVENT_CNTRPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_WIDTHPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_MSBPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_LSBPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_RANGEPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_RESETPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_FIELD_MASKPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_GETPCIE_NOC_ROUTER_1_6_6_ROEC_EVENT_CNTR_SETns_noc_io_pcie_soc_ip.csr151240EVENT_CNTR32'bit event incrementing counter. Rollover from 32'hFFFFF -> 32'd0 sets the rollover status bit RE3100x00000000R/Wregisterpcie_noc.router_2_1_1_rerouter_2_1_1_rePCIE_NOC_ROUTER_2_1_1_RE_ADDRESSPCIE_NOC_ROUTER_2_1_1_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_RE_OFFSETPCIE_NOC_ROUTER_2_1_1_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151415R2_1 register re0x48080R/W0x00000000Pcie_noc_router_2_1_1_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_2_1_1_RE_OVFI_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_OVFI_MSBPCIE_NOC_ROUTER_2_1_1_RE_OVFI_LSBPCIE_NOC_ROUTER_2_1_1_RE_OVFI_RANGEPCIE_NOC_ROUTER_2_1_1_RE_OVFI_RESETPCIE_NOC_ROUTER_2_1_1_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_OVFI_GETPCIE_NOC_ROUTER_2_1_1_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr151267OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_2_1_1_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr151278CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_2_1_1_RE_OVFO_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_OVFO_MSBPCIE_NOC_ROUTER_2_1_1_RE_OVFO_LSBPCIE_NOC_ROUTER_2_1_1_RE_OVFO_RANGEPCIE_NOC_ROUTER_2_1_1_RE_OVFO_RESETPCIE_NOC_ROUTER_2_1_1_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_OVFO_GETPCIE_NOC_ROUTER_2_1_1_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr151292OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_2_1_1_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr151303UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_2_1_1_RE_PGE_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_PGE_MSBPCIE_NOC_ROUTER_2_1_1_RE_PGE_LSBPCIE_NOC_ROUTER_2_1_1_RE_PGE_RANGEPCIE_NOC_ROUTER_2_1_1_RE_PGE_RESETPCIE_NOC_ROUTER_2_1_1_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_PGE_GETPCIE_NOC_ROUTER_2_1_1_RE_PGE_SETns_noc_io_pcie_soc_ip.csr151315PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_2_1_1_RE_NLU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_NLU_MSBPCIE_NOC_ROUTER_2_1_1_RE_NLU_LSBPCIE_NOC_ROUTER_2_1_1_RE_NLU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_NLU_RESETPCIE_NOC_ROUTER_2_1_1_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_NLU_GETPCIE_NOC_ROUTER_2_1_1_RE_NLU_SETns_noc_io_pcie_soc_ip.csr151326NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_2_1_1_RE_ELU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_ELU_MSBPCIE_NOC_ROUTER_2_1_1_RE_ELU_LSBPCIE_NOC_ROUTER_2_1_1_RE_ELU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_ELU_RESETPCIE_NOC_ROUTER_2_1_1_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_ELU_GETPCIE_NOC_ROUTER_2_1_1_RE_ELU_SETns_noc_io_pcie_soc_ip.csr151337ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_2_1_1_RE_WLU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_WLU_MSBPCIE_NOC_ROUTER_2_1_1_RE_WLU_LSBPCIE_NOC_ROUTER_2_1_1_RE_WLU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_WLU_RESETPCIE_NOC_ROUTER_2_1_1_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_WLU_GETPCIE_NOC_ROUTER_2_1_1_RE_WLU_SETns_noc_io_pcie_soc_ip.csr151348WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_2_1_1_RE_SLU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_SLU_MSBPCIE_NOC_ROUTER_2_1_1_RE_SLU_LSBPCIE_NOC_ROUTER_2_1_1_RE_SLU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_SLU_RESETPCIE_NOC_ROUTER_2_1_1_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_SLU_GETPCIE_NOC_ROUTER_2_1_1_RE_SLU_SETns_noc_io_pcie_soc_ip.csr151359SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_2_1_1_RE_HLU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_HLU_MSBPCIE_NOC_ROUTER_2_1_1_RE_HLU_LSBPCIE_NOC_ROUTER_2_1_1_RE_HLU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_HLU_RESETPCIE_NOC_ROUTER_2_1_1_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_HLU_GETPCIE_NOC_ROUTER_2_1_1_RE_HLU_SETns_noc_io_pcie_soc_ip.csr151370HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_2_1_1_RE_ILU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_ILU_MSBPCIE_NOC_ROUTER_2_1_1_RE_ILU_LSBPCIE_NOC_ROUTER_2_1_1_RE_ILU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_ILU_RESETPCIE_NOC_ROUTER_2_1_1_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_ILU_GETPCIE_NOC_ROUTER_2_1_1_RE_ILU_SETns_noc_io_pcie_soc_ip.csr151381ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_2_1_1_RE_JLU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_JLU_MSBPCIE_NOC_ROUTER_2_1_1_RE_JLU_LSBPCIE_NOC_ROUTER_2_1_1_RE_JLU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_JLU_RESETPCIE_NOC_ROUTER_2_1_1_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_JLU_GETPCIE_NOC_ROUTER_2_1_1_RE_JLU_SETns_noc_io_pcie_soc_ip.csr151392JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_2_1_1_RE_KLU_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_KLU_MSBPCIE_NOC_ROUTER_2_1_1_RE_KLU_LSBPCIE_NOC_ROUTER_2_1_1_RE_KLU_RANGEPCIE_NOC_ROUTER_2_1_1_RE_KLU_RESETPCIE_NOC_ROUTER_2_1_1_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_KLU_GETPCIE_NOC_ROUTER_2_1_1_RE_KLU_SETns_noc_io_pcie_soc_ip.csr151403KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_2_1_1_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr151414UNSD_31_1431170x0000Rregisterpcie_noc.router_2_1_1_remrouter_2_1_1_remPCIE_NOC_ROUTER_2_1_1_REM_ADDRESSPCIE_NOC_ROUTER_2_1_1_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_REM_OFFSETPCIE_NOC_ROUTER_2_1_1_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151588R2_1 register rem0x48088R/W0x0001fe00Pcie_noc_router_2_1_1_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_MSBPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_LSBPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_RANGEPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_RESETPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_GETPCIE_NOC_ROUTER_2_1_1_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr151441OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_2_1_1_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr151452CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_MSBPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_LSBPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_RANGEPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_RESETPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_GETPCIE_NOC_ROUTER_2_1_1_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr151466OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_2_1_1_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr151477UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_2_1_1_REM_PGM_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_PGM_MSBPCIE_NOC_ROUTER_2_1_1_REM_PGM_LSBPCIE_NOC_ROUTER_2_1_1_REM_PGM_RANGEPCIE_NOC_ROUTER_2_1_1_REM_PGM_RESETPCIE_NOC_ROUTER_2_1_1_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_PGM_GETPCIE_NOC_ROUTER_2_1_1_REM_PGM_SETns_noc_io_pcie_soc_ip.csr151488PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_2_1_1_REM_MN_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MN_MSBPCIE_NOC_ROUTER_2_1_1_REM_MN_LSBPCIE_NOC_ROUTER_2_1_1_REM_MN_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MN_RESETPCIE_NOC_ROUTER_2_1_1_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MN_GETPCIE_NOC_ROUTER_2_1_1_REM_MN_SETns_noc_io_pcie_soc_ip.csr151499MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_2_1_1_REM_ME_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_ME_MSBPCIE_NOC_ROUTER_2_1_1_REM_ME_LSBPCIE_NOC_ROUTER_2_1_1_REM_ME_RANGEPCIE_NOC_ROUTER_2_1_1_REM_ME_RESETPCIE_NOC_ROUTER_2_1_1_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_ME_GETPCIE_NOC_ROUTER_2_1_1_REM_ME_SETns_noc_io_pcie_soc_ip.csr151510ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_2_1_1_REM_MW_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MW_MSBPCIE_NOC_ROUTER_2_1_1_REM_MW_LSBPCIE_NOC_ROUTER_2_1_1_REM_MW_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MW_RESETPCIE_NOC_ROUTER_2_1_1_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MW_GETPCIE_NOC_ROUTER_2_1_1_REM_MW_SETns_noc_io_pcie_soc_ip.csr151521MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_2_1_1_REM_MS_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MS_MSBPCIE_NOC_ROUTER_2_1_1_REM_MS_LSBPCIE_NOC_ROUTER_2_1_1_REM_MS_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MS_RESETPCIE_NOC_ROUTER_2_1_1_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MS_GETPCIE_NOC_ROUTER_2_1_1_REM_MS_SETns_noc_io_pcie_soc_ip.csr151532MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_2_1_1_REM_MH_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MH_MSBPCIE_NOC_ROUTER_2_1_1_REM_MH_LSBPCIE_NOC_ROUTER_2_1_1_REM_MH_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MH_RESETPCIE_NOC_ROUTER_2_1_1_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MH_GETPCIE_NOC_ROUTER_2_1_1_REM_MH_SETns_noc_io_pcie_soc_ip.csr151543MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_2_1_1_REM_MI_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MI_MSBPCIE_NOC_ROUTER_2_1_1_REM_MI_LSBPCIE_NOC_ROUTER_2_1_1_REM_MI_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MI_RESETPCIE_NOC_ROUTER_2_1_1_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MI_GETPCIE_NOC_ROUTER_2_1_1_REM_MI_SETns_noc_io_pcie_soc_ip.csr151554MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_2_1_1_REM_MJ_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MJ_MSBPCIE_NOC_ROUTER_2_1_1_REM_MJ_LSBPCIE_NOC_ROUTER_2_1_1_REM_MJ_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MJ_RESETPCIE_NOC_ROUTER_2_1_1_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MJ_GETPCIE_NOC_ROUTER_2_1_1_REM_MJ_SETns_noc_io_pcie_soc_ip.csr151565MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_2_1_1_REM_MK_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_MK_MSBPCIE_NOC_ROUTER_2_1_1_REM_MK_LSBPCIE_NOC_ROUTER_2_1_1_REM_MK_RANGEPCIE_NOC_ROUTER_2_1_1_REM_MK_RESETPCIE_NOC_ROUTER_2_1_1_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_MK_GETPCIE_NOC_ROUTER_2_1_1_REM_MK_SETns_noc_io_pcie_soc_ip.csr151576MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_2_1_1_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr151587UNSD_31_1431170x0000Rregisterpcie_noc.router_2_1_1_idrouter_2_1_1_idPCIE_NOC_ROUTER_2_1_1_ID_ADDRESSPCIE_NOC_ROUTER_2_1_1_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_ID_OFFSETPCIE_NOC_ROUTER_2_1_1_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151657R2_1 register id0x480A0R0x01000022Pcie_noc_router_2_1_1_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_2_1_1_ID_LAYER_WIDTHPCIE_NOC_ROUTER_2_1_1_ID_LAYER_MSBPCIE_NOC_ROUTER_2_1_1_ID_LAYER_LSBPCIE_NOC_ROUTER_2_1_1_ID_LAYER_RANGEPCIE_NOC_ROUTER_2_1_1_ID_LAYER_RESETPCIE_NOC_ROUTER_2_1_1_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_ID_LAYER_GETPCIE_NOC_ROUTER_2_1_1_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr151613LAYER5-bit identifier of the NoC layer on which this router is located400x02RPOSPCIE_NOC_ROUTER_2_1_1_ID_POS_WIDTHPCIE_NOC_ROUTER_2_1_1_ID_POS_MSBPCIE_NOC_ROUTER_2_1_1_ID_POS_LSBPCIE_NOC_ROUTER_2_1_1_ID_POS_RANGEPCIE_NOC_ROUTER_2_1_1_ID_POS_RESETPCIE_NOC_ROUTER_2_1_1_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_ID_POS_GETPCIE_NOC_ROUTER_2_1_1_ID_POS_SETns_noc_io_pcie_soc_ip.csr151624POS16-bit position ID of this router in the NoC2050x0001RZEROPCIE_NOC_ROUTER_2_1_1_ID_ZERO_WIDTHPCIE_NOC_ROUTER_2_1_1_ID_ZERO_MSBPCIE_NOC_ROUTER_2_1_1_ID_ZERO_LSBPCIE_NOC_ROUTER_2_1_1_ID_ZERO_RANGEPCIE_NOC_ROUTER_2_1_1_ID_ZERO_RESETPCIE_NOC_ROUTER_2_1_1_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_ID_ZERO_GETPCIE_NOC_ROUTER_2_1_1_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr151635ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_2_1_1_ID_ONE_WIDTHPCIE_NOC_ROUTER_2_1_1_ID_ONE_MSBPCIE_NOC_ROUTER_2_1_1_ID_ONE_LSBPCIE_NOC_ROUTER_2_1_1_ID_ONE_RANGEPCIE_NOC_ROUTER_2_1_1_ID_ONE_RESETPCIE_NOC_ROUTER_2_1_1_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_ID_ONE_GETPCIE_NOC_ROUTER_2_1_1_ID_ONE_SETns_noc_io_pcie_soc_ip.csr151646ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_2_1_1_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr151656UNSD_31_2531250x00Rregisterpcie_noc.router_2_1_1_rcgorouter_2_1_1_rcgoPCIE_NOC_ROUTER_2_1_1_RCGO_ADDRESSPCIE_NOC_ROUTER_2_1_1_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_RCGO_OFFSETPCIE_NOC_ROUTER_2_1_1_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151696R2_1 register rcgo0x480B0R/W0x00000000Pcie_noc_router_2_1_1_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_MSBPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_LSBPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_RANGEPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_RESETPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_GETPCIE_NOC_ROUTER_2_1_1_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr151684FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_2_1_1_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr151695UNSD_31_13110x00000000Rregisterpcie_noc.router_2_1_1_p1_rperrrouter_2_1_1_p1_rperrPCIE_NOC_ROUTER_2_1_1_P1_RPERR_ADDRESSPCIE_NOC_ROUTER_2_1_1_P1_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P1_RPERR_OFFSETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr151987R2_1 register p1_rperr0x480C0R/W0x00000000Pcie_noc_router_2_1_1_p1_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_SETns_noc_io_pcie_soc_ip.csr151739D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr151750SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr151761PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr151772RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr151783CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr151794UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr151805D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr151816SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr151828PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr151839RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr151851D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr151863SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr151876PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr151888RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr151900D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr151912SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr151925PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr151937RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr151949D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr151961SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr151974PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr151986RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_1_1_p2_rperrrouter_2_1_1_p2_rperrPCIE_NOC_ROUTER_2_1_1_P2_RPERR_ADDRESSPCIE_NOC_ROUTER_2_1_1_P2_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P2_RPERR_OFFSETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr152278R2_1 register p2_rperr0x480C8R/W0x00000000Pcie_noc_router_2_1_1_p2_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_SETns_noc_io_pcie_soc_ip.csr152030D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr152041SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr152052PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr152063RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr152074CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr152085UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr152096D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr152107SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr152119PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr152130RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr152142D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr152154SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr152167PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr152179RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr152191D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr152203SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr152216PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr152228RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr152240D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr152252SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr152265PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr152277RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_1_1_p3_rperrrouter_2_1_1_p3_rperrPCIE_NOC_ROUTER_2_1_1_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_2_1_1_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P3_RPERR_OFFSETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr152569R2_1 register p3_rperr0x480D0R/W0x00000000Pcie_noc_router_2_1_1_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr152321D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr152332SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr152343PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr152354RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr152365CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr152376UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr152387D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr152398SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr152410PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr152421RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr152433D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr152445SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr152458PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr152470RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr152482D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr152494SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr152507PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr152519RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr152531D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr152543SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr152556PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr152568RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_1_1_p4_rperrrouter_2_1_1_p4_rperrPCIE_NOC_ROUTER_2_1_1_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_2_1_1_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P4_RPERR_OFFSETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr152860R2_1 register p4_rperr0x480D8R/W0x00000000Pcie_noc_router_2_1_1_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr152612D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr152623SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr152634PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr152645RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr152656CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr152667UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr152678D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr152689SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr152701PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr152712RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr152724D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr152736SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr152749PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr152761RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr152773D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr152785SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr152798PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr152810RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr152822D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr152834SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr152847PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr152859RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_1_1_p1_rperrmrouter_2_1_1_p1_rperrmPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_OFFSETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr153118R2_1 register p1_rperrm0x48100R/W0x00000000Pcie_noc_router_2_1_1_p1_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr152882DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr152893SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr152904PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr152915RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr152926CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr152937UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr152948D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr152959SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr152971PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr152982RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr152993D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr153004SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr153016PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr153027RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr153038D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr153049SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr153061PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr153072RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr153083D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr153094SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr153106PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P1_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr153117RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_1_1_p2_rperrmrouter_2_1_1_p2_rperrmPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_OFFSETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr153376R2_1 register p2_rperrm0x48108R/W0x00000000Pcie_noc_router_2_1_1_p2_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr153140DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr153151SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr153162PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr153173RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr153184CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr153195UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr153206D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr153217SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr153229PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr153240RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr153251D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr153262SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr153274PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr153285RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr153296D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr153307SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr153319PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr153330RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr153341D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr153352SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr153364PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P2_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr153375RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_1_1_p3_rperrmrouter_2_1_1_p3_rperrmPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr153634R2_1 register p3_rperrm0x48110R/W0x00000000Pcie_noc_router_2_1_1_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr153398DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr153409SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr153420PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr153431RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr153442CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr153453UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr153464D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr153475SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr153487PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr153498RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr153509D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr153520SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr153532PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr153543RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr153554D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr153565SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr153577PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr153588RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr153599D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr153610SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr153622PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr153633RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_1_1_p4_rperrmrouter_2_1_1_p4_rperrmPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr153892R2_1 register p4_rperrm0x48118R/W0x00000000Pcie_noc_router_2_1_1_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr153656DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr153667SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr153678PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr153689RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr153700CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr153711UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr153722D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr153733SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr153745PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr153756RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr153767D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr153778SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr153790PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr153801RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr153812D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr153823SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr153835PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr153846RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr153857D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr153868SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr153880PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_1_1_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr153891RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_3_3_rerouter_2_3_3_rePCIE_NOC_ROUTER_2_3_3_RE_ADDRESSPCIE_NOC_ROUTER_2_3_3_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_RE_OFFSETPCIE_NOC_ROUTER_2_3_3_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr154066R2_3 register re0x4C080R/W0x00000000Pcie_noc_router_2_3_3_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_2_3_3_RE_OVFI_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_OVFI_MSBPCIE_NOC_ROUTER_2_3_3_RE_OVFI_LSBPCIE_NOC_ROUTER_2_3_3_RE_OVFI_RANGEPCIE_NOC_ROUTER_2_3_3_RE_OVFI_RESETPCIE_NOC_ROUTER_2_3_3_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_OVFI_GETPCIE_NOC_ROUTER_2_3_3_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr153918OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_2_3_3_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr153929CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_2_3_3_RE_OVFO_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_OVFO_MSBPCIE_NOC_ROUTER_2_3_3_RE_OVFO_LSBPCIE_NOC_ROUTER_2_3_3_RE_OVFO_RANGEPCIE_NOC_ROUTER_2_3_3_RE_OVFO_RESETPCIE_NOC_ROUTER_2_3_3_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_OVFO_GETPCIE_NOC_ROUTER_2_3_3_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr153943OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_2_3_3_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr153954UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_2_3_3_RE_PGE_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_PGE_MSBPCIE_NOC_ROUTER_2_3_3_RE_PGE_LSBPCIE_NOC_ROUTER_2_3_3_RE_PGE_RANGEPCIE_NOC_ROUTER_2_3_3_RE_PGE_RESETPCIE_NOC_ROUTER_2_3_3_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_PGE_GETPCIE_NOC_ROUTER_2_3_3_RE_PGE_SETns_noc_io_pcie_soc_ip.csr153966PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_2_3_3_RE_NLU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_NLU_MSBPCIE_NOC_ROUTER_2_3_3_RE_NLU_LSBPCIE_NOC_ROUTER_2_3_3_RE_NLU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_NLU_RESETPCIE_NOC_ROUTER_2_3_3_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_NLU_GETPCIE_NOC_ROUTER_2_3_3_RE_NLU_SETns_noc_io_pcie_soc_ip.csr153977NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_2_3_3_RE_ELU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_ELU_MSBPCIE_NOC_ROUTER_2_3_3_RE_ELU_LSBPCIE_NOC_ROUTER_2_3_3_RE_ELU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_ELU_RESETPCIE_NOC_ROUTER_2_3_3_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_ELU_GETPCIE_NOC_ROUTER_2_3_3_RE_ELU_SETns_noc_io_pcie_soc_ip.csr153988ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_2_3_3_RE_WLU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_WLU_MSBPCIE_NOC_ROUTER_2_3_3_RE_WLU_LSBPCIE_NOC_ROUTER_2_3_3_RE_WLU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_WLU_RESETPCIE_NOC_ROUTER_2_3_3_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_WLU_GETPCIE_NOC_ROUTER_2_3_3_RE_WLU_SETns_noc_io_pcie_soc_ip.csr153999WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_2_3_3_RE_SLU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_SLU_MSBPCIE_NOC_ROUTER_2_3_3_RE_SLU_LSBPCIE_NOC_ROUTER_2_3_3_RE_SLU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_SLU_RESETPCIE_NOC_ROUTER_2_3_3_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_SLU_GETPCIE_NOC_ROUTER_2_3_3_RE_SLU_SETns_noc_io_pcie_soc_ip.csr154010SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_2_3_3_RE_HLU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_HLU_MSBPCIE_NOC_ROUTER_2_3_3_RE_HLU_LSBPCIE_NOC_ROUTER_2_3_3_RE_HLU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_HLU_RESETPCIE_NOC_ROUTER_2_3_3_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_HLU_GETPCIE_NOC_ROUTER_2_3_3_RE_HLU_SETns_noc_io_pcie_soc_ip.csr154021HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_2_3_3_RE_ILU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_ILU_MSBPCIE_NOC_ROUTER_2_3_3_RE_ILU_LSBPCIE_NOC_ROUTER_2_3_3_RE_ILU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_ILU_RESETPCIE_NOC_ROUTER_2_3_3_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_ILU_GETPCIE_NOC_ROUTER_2_3_3_RE_ILU_SETns_noc_io_pcie_soc_ip.csr154032ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_2_3_3_RE_JLU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_JLU_MSBPCIE_NOC_ROUTER_2_3_3_RE_JLU_LSBPCIE_NOC_ROUTER_2_3_3_RE_JLU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_JLU_RESETPCIE_NOC_ROUTER_2_3_3_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_JLU_GETPCIE_NOC_ROUTER_2_3_3_RE_JLU_SETns_noc_io_pcie_soc_ip.csr154043JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_2_3_3_RE_KLU_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_KLU_MSBPCIE_NOC_ROUTER_2_3_3_RE_KLU_LSBPCIE_NOC_ROUTER_2_3_3_RE_KLU_RANGEPCIE_NOC_ROUTER_2_3_3_RE_KLU_RESETPCIE_NOC_ROUTER_2_3_3_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_KLU_GETPCIE_NOC_ROUTER_2_3_3_RE_KLU_SETns_noc_io_pcie_soc_ip.csr154054KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_2_3_3_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr154065UNSD_31_1431170x0000Rregisterpcie_noc.router_2_3_3_remrouter_2_3_3_remPCIE_NOC_ROUTER_2_3_3_REM_ADDRESSPCIE_NOC_ROUTER_2_3_3_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_REM_OFFSETPCIE_NOC_ROUTER_2_3_3_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr154239R2_3 register rem0x4C088R/W0x0001fe00Pcie_noc_router_2_3_3_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_MSBPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_LSBPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_RANGEPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_RESETPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_GETPCIE_NOC_ROUTER_2_3_3_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr154092OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_2_3_3_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr154103CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_MSBPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_LSBPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_RANGEPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_RESETPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_GETPCIE_NOC_ROUTER_2_3_3_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr154117OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_2_3_3_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr154128UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_2_3_3_REM_PGM_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_PGM_MSBPCIE_NOC_ROUTER_2_3_3_REM_PGM_LSBPCIE_NOC_ROUTER_2_3_3_REM_PGM_RANGEPCIE_NOC_ROUTER_2_3_3_REM_PGM_RESETPCIE_NOC_ROUTER_2_3_3_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_PGM_GETPCIE_NOC_ROUTER_2_3_3_REM_PGM_SETns_noc_io_pcie_soc_ip.csr154139PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_2_3_3_REM_MN_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MN_MSBPCIE_NOC_ROUTER_2_3_3_REM_MN_LSBPCIE_NOC_ROUTER_2_3_3_REM_MN_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MN_RESETPCIE_NOC_ROUTER_2_3_3_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MN_GETPCIE_NOC_ROUTER_2_3_3_REM_MN_SETns_noc_io_pcie_soc_ip.csr154150MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_2_3_3_REM_ME_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_ME_MSBPCIE_NOC_ROUTER_2_3_3_REM_ME_LSBPCIE_NOC_ROUTER_2_3_3_REM_ME_RANGEPCIE_NOC_ROUTER_2_3_3_REM_ME_RESETPCIE_NOC_ROUTER_2_3_3_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_ME_GETPCIE_NOC_ROUTER_2_3_3_REM_ME_SETns_noc_io_pcie_soc_ip.csr154161ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_2_3_3_REM_MW_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MW_MSBPCIE_NOC_ROUTER_2_3_3_REM_MW_LSBPCIE_NOC_ROUTER_2_3_3_REM_MW_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MW_RESETPCIE_NOC_ROUTER_2_3_3_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MW_GETPCIE_NOC_ROUTER_2_3_3_REM_MW_SETns_noc_io_pcie_soc_ip.csr154172MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_2_3_3_REM_MS_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MS_MSBPCIE_NOC_ROUTER_2_3_3_REM_MS_LSBPCIE_NOC_ROUTER_2_3_3_REM_MS_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MS_RESETPCIE_NOC_ROUTER_2_3_3_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MS_GETPCIE_NOC_ROUTER_2_3_3_REM_MS_SETns_noc_io_pcie_soc_ip.csr154183MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_2_3_3_REM_MH_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MH_MSBPCIE_NOC_ROUTER_2_3_3_REM_MH_LSBPCIE_NOC_ROUTER_2_3_3_REM_MH_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MH_RESETPCIE_NOC_ROUTER_2_3_3_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MH_GETPCIE_NOC_ROUTER_2_3_3_REM_MH_SETns_noc_io_pcie_soc_ip.csr154194MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_2_3_3_REM_MI_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MI_MSBPCIE_NOC_ROUTER_2_3_3_REM_MI_LSBPCIE_NOC_ROUTER_2_3_3_REM_MI_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MI_RESETPCIE_NOC_ROUTER_2_3_3_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MI_GETPCIE_NOC_ROUTER_2_3_3_REM_MI_SETns_noc_io_pcie_soc_ip.csr154205MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_2_3_3_REM_MJ_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MJ_MSBPCIE_NOC_ROUTER_2_3_3_REM_MJ_LSBPCIE_NOC_ROUTER_2_3_3_REM_MJ_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MJ_RESETPCIE_NOC_ROUTER_2_3_3_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MJ_GETPCIE_NOC_ROUTER_2_3_3_REM_MJ_SETns_noc_io_pcie_soc_ip.csr154216MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_2_3_3_REM_MK_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_MK_MSBPCIE_NOC_ROUTER_2_3_3_REM_MK_LSBPCIE_NOC_ROUTER_2_3_3_REM_MK_RANGEPCIE_NOC_ROUTER_2_3_3_REM_MK_RESETPCIE_NOC_ROUTER_2_3_3_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_MK_GETPCIE_NOC_ROUTER_2_3_3_REM_MK_SETns_noc_io_pcie_soc_ip.csr154227MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_2_3_3_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr154238UNSD_31_1431170x0000Rregisterpcie_noc.router_2_3_3_idrouter_2_3_3_idPCIE_NOC_ROUTER_2_3_3_ID_ADDRESSPCIE_NOC_ROUTER_2_3_3_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_ID_OFFSETPCIE_NOC_ROUTER_2_3_3_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr154308R2_3 register id0x4C0A0R0x01000062Pcie_noc_router_2_3_3_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_2_3_3_ID_LAYER_WIDTHPCIE_NOC_ROUTER_2_3_3_ID_LAYER_MSBPCIE_NOC_ROUTER_2_3_3_ID_LAYER_LSBPCIE_NOC_ROUTER_2_3_3_ID_LAYER_RANGEPCIE_NOC_ROUTER_2_3_3_ID_LAYER_RESETPCIE_NOC_ROUTER_2_3_3_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_ID_LAYER_GETPCIE_NOC_ROUTER_2_3_3_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr154264LAYER5-bit identifier of the NoC layer on which this router is located400x02RPOSPCIE_NOC_ROUTER_2_3_3_ID_POS_WIDTHPCIE_NOC_ROUTER_2_3_3_ID_POS_MSBPCIE_NOC_ROUTER_2_3_3_ID_POS_LSBPCIE_NOC_ROUTER_2_3_3_ID_POS_RANGEPCIE_NOC_ROUTER_2_3_3_ID_POS_RESETPCIE_NOC_ROUTER_2_3_3_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_ID_POS_GETPCIE_NOC_ROUTER_2_3_3_ID_POS_SETns_noc_io_pcie_soc_ip.csr154275POS16-bit position ID of this router in the NoC2050x0003RZEROPCIE_NOC_ROUTER_2_3_3_ID_ZERO_WIDTHPCIE_NOC_ROUTER_2_3_3_ID_ZERO_MSBPCIE_NOC_ROUTER_2_3_3_ID_ZERO_LSBPCIE_NOC_ROUTER_2_3_3_ID_ZERO_RANGEPCIE_NOC_ROUTER_2_3_3_ID_ZERO_RESETPCIE_NOC_ROUTER_2_3_3_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_ID_ZERO_GETPCIE_NOC_ROUTER_2_3_3_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr154286ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_2_3_3_ID_ONE_WIDTHPCIE_NOC_ROUTER_2_3_3_ID_ONE_MSBPCIE_NOC_ROUTER_2_3_3_ID_ONE_LSBPCIE_NOC_ROUTER_2_3_3_ID_ONE_RANGEPCIE_NOC_ROUTER_2_3_3_ID_ONE_RESETPCIE_NOC_ROUTER_2_3_3_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_ID_ONE_GETPCIE_NOC_ROUTER_2_3_3_ID_ONE_SETns_noc_io_pcie_soc_ip.csr154297ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_2_3_3_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr154307UNSD_31_2531250x00Rregisterpcie_noc.router_2_3_3_rcgorouter_2_3_3_rcgoPCIE_NOC_ROUTER_2_3_3_RCGO_ADDRESSPCIE_NOC_ROUTER_2_3_3_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_RCGO_OFFSETPCIE_NOC_ROUTER_2_3_3_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr154347R2_3 register rcgo0x4C0B0R/W0x00000000Pcie_noc_router_2_3_3_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_MSBPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_LSBPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_RANGEPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_RESETPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_GETPCIE_NOC_ROUTER_2_3_3_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr154335FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_2_3_3_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr154346UNSD_31_13110x00000000Rregisterpcie_noc.router_2_3_3_p2_rperrrouter_2_3_3_p2_rperrPCIE_NOC_ROUTER_2_3_3_P2_RPERR_ADDRESSPCIE_NOC_ROUTER_2_3_3_P2_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_P2_RPERR_OFFSETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr154638R2_3 register p2_rperr0x4C0C8R/W0x00000000Pcie_noc_router_2_3_3_p2_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_SETns_noc_io_pcie_soc_ip.csr154390D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr154401SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr154412PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr154423RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr154434CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr154445UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr154456D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr154467SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr154479PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr154490RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr154502D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr154514SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr154527PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr154539RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr154551D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr154563SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr154576PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr154588RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr154600D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr154612SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr154625PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr154637RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_3_3_p3_rperrrouter_2_3_3_p3_rperrPCIE_NOC_ROUTER_2_3_3_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_2_3_3_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_P3_RPERR_OFFSETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr154929R2_3 register p3_rperr0x4C0D0R/W0x00000000Pcie_noc_router_2_3_3_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr154681D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr154692SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr154703PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr154714RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr154725CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr154736UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr154747D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr154758SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr154770PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr154781RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr154793D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr154805SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr154818PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr154830RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr154842D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr154854SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr154867PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr154879RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr154891D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr154903SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr154916PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr154928RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_3_3_p4_rperrrouter_2_3_3_p4_rperrPCIE_NOC_ROUTER_2_3_3_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_2_3_3_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_P4_RPERR_OFFSETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr155220R2_3 register p4_rperr0x4C0D8R/W0x00000000Pcie_noc_router_2_3_3_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr154972D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr154983SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr154994PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr155005RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr155016CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr155027UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr155038D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr155049SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr155061PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr155072RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr155084D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr155096SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr155109PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr155121RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr155133D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr155145SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr155158PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr155170RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr155182D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr155194SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr155207PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr155219RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_3_3_p2_rperrmrouter_2_3_3_p2_rperrmPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_OFFSETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr155478R2_3 register p2_rperrm0x4C108R/W0x00000000Pcie_noc_router_2_3_3_p2_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr155242DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr155253SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr155264PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr155275RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr155286CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr155297UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr155308D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr155319SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr155331PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr155342RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr155353D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr155364SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr155376PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr155387RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr155398D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr155409SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr155421PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr155432RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr155443D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr155454SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr155466PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_3_3_P2_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr155477RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_3_3_p3_rperrmrouter_2_3_3_p3_rperrmPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr155736R2_3 register p3_rperrm0x4C110R/W0x00000000Pcie_noc_router_2_3_3_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr155500DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr155511SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr155522PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr155533RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr155544CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr155555UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr155566D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr155577SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr155589PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr155600RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr155611D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr155622SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr155634PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr155645RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr155656D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr155667SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr155679PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr155690RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr155701D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr155712SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr155724PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_3_3_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr155735RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_3_3_p4_rperrmrouter_2_3_3_p4_rperrmPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr155994R2_3 register p4_rperrm0x4C118R/W0x00000000Pcie_noc_router_2_3_3_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr155758DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr155769SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr155780PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr155791RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr155802CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr155813UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr155824D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr155835SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr155847PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr155858RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr155869D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr155880SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr155892PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr155903RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr155914D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr155925SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr155937PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr155948RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr155959D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr155970SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr155982PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_3_3_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr155993RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_5_5_rerouter_2_5_5_rePCIE_NOC_ROUTER_2_5_5_RE_ADDRESSPCIE_NOC_ROUTER_2_5_5_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_RE_OFFSETPCIE_NOC_ROUTER_2_5_5_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr156168R2_5 register re0x50080R/W0x00000000Pcie_noc_router_2_5_5_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_2_5_5_RE_OVFI_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_OVFI_MSBPCIE_NOC_ROUTER_2_5_5_RE_OVFI_LSBPCIE_NOC_ROUTER_2_5_5_RE_OVFI_RANGEPCIE_NOC_ROUTER_2_5_5_RE_OVFI_RESETPCIE_NOC_ROUTER_2_5_5_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_OVFI_GETPCIE_NOC_ROUTER_2_5_5_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr156020OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_2_5_5_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr156031CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_2_5_5_RE_OVFO_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_OVFO_MSBPCIE_NOC_ROUTER_2_5_5_RE_OVFO_LSBPCIE_NOC_ROUTER_2_5_5_RE_OVFO_RANGEPCIE_NOC_ROUTER_2_5_5_RE_OVFO_RESETPCIE_NOC_ROUTER_2_5_5_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_OVFO_GETPCIE_NOC_ROUTER_2_5_5_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr156045OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_2_5_5_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr156056UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_2_5_5_RE_PGE_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_PGE_MSBPCIE_NOC_ROUTER_2_5_5_RE_PGE_LSBPCIE_NOC_ROUTER_2_5_5_RE_PGE_RANGEPCIE_NOC_ROUTER_2_5_5_RE_PGE_RESETPCIE_NOC_ROUTER_2_5_5_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_PGE_GETPCIE_NOC_ROUTER_2_5_5_RE_PGE_SETns_noc_io_pcie_soc_ip.csr156068PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_2_5_5_RE_NLU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_NLU_MSBPCIE_NOC_ROUTER_2_5_5_RE_NLU_LSBPCIE_NOC_ROUTER_2_5_5_RE_NLU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_NLU_RESETPCIE_NOC_ROUTER_2_5_5_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_NLU_GETPCIE_NOC_ROUTER_2_5_5_RE_NLU_SETns_noc_io_pcie_soc_ip.csr156079NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_2_5_5_RE_ELU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_ELU_MSBPCIE_NOC_ROUTER_2_5_5_RE_ELU_LSBPCIE_NOC_ROUTER_2_5_5_RE_ELU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_ELU_RESETPCIE_NOC_ROUTER_2_5_5_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_ELU_GETPCIE_NOC_ROUTER_2_5_5_RE_ELU_SETns_noc_io_pcie_soc_ip.csr156090ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_2_5_5_RE_WLU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_WLU_MSBPCIE_NOC_ROUTER_2_5_5_RE_WLU_LSBPCIE_NOC_ROUTER_2_5_5_RE_WLU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_WLU_RESETPCIE_NOC_ROUTER_2_5_5_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_WLU_GETPCIE_NOC_ROUTER_2_5_5_RE_WLU_SETns_noc_io_pcie_soc_ip.csr156101WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_2_5_5_RE_SLU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_SLU_MSBPCIE_NOC_ROUTER_2_5_5_RE_SLU_LSBPCIE_NOC_ROUTER_2_5_5_RE_SLU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_SLU_RESETPCIE_NOC_ROUTER_2_5_5_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_SLU_GETPCIE_NOC_ROUTER_2_5_5_RE_SLU_SETns_noc_io_pcie_soc_ip.csr156112SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_2_5_5_RE_HLU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_HLU_MSBPCIE_NOC_ROUTER_2_5_5_RE_HLU_LSBPCIE_NOC_ROUTER_2_5_5_RE_HLU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_HLU_RESETPCIE_NOC_ROUTER_2_5_5_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_HLU_GETPCIE_NOC_ROUTER_2_5_5_RE_HLU_SETns_noc_io_pcie_soc_ip.csr156123HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_2_5_5_RE_ILU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_ILU_MSBPCIE_NOC_ROUTER_2_5_5_RE_ILU_LSBPCIE_NOC_ROUTER_2_5_5_RE_ILU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_ILU_RESETPCIE_NOC_ROUTER_2_5_5_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_ILU_GETPCIE_NOC_ROUTER_2_5_5_RE_ILU_SETns_noc_io_pcie_soc_ip.csr156134ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_2_5_5_RE_JLU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_JLU_MSBPCIE_NOC_ROUTER_2_5_5_RE_JLU_LSBPCIE_NOC_ROUTER_2_5_5_RE_JLU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_JLU_RESETPCIE_NOC_ROUTER_2_5_5_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_JLU_GETPCIE_NOC_ROUTER_2_5_5_RE_JLU_SETns_noc_io_pcie_soc_ip.csr156145JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_2_5_5_RE_KLU_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_KLU_MSBPCIE_NOC_ROUTER_2_5_5_RE_KLU_LSBPCIE_NOC_ROUTER_2_5_5_RE_KLU_RANGEPCIE_NOC_ROUTER_2_5_5_RE_KLU_RESETPCIE_NOC_ROUTER_2_5_5_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_KLU_GETPCIE_NOC_ROUTER_2_5_5_RE_KLU_SETns_noc_io_pcie_soc_ip.csr156156KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_2_5_5_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr156167UNSD_31_1431170x0000Rregisterpcie_noc.router_2_5_5_remrouter_2_5_5_remPCIE_NOC_ROUTER_2_5_5_REM_ADDRESSPCIE_NOC_ROUTER_2_5_5_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_REM_OFFSETPCIE_NOC_ROUTER_2_5_5_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr156341R2_5 register rem0x50088R/W0x0001fe00Pcie_noc_router_2_5_5_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_MSBPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_LSBPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_RANGEPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_RESETPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_GETPCIE_NOC_ROUTER_2_5_5_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr156194OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_2_5_5_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr156205CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_MSBPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_LSBPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_RANGEPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_RESETPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_GETPCIE_NOC_ROUTER_2_5_5_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr156219OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_2_5_5_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr156230UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_2_5_5_REM_PGM_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_PGM_MSBPCIE_NOC_ROUTER_2_5_5_REM_PGM_LSBPCIE_NOC_ROUTER_2_5_5_REM_PGM_RANGEPCIE_NOC_ROUTER_2_5_5_REM_PGM_RESETPCIE_NOC_ROUTER_2_5_5_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_PGM_GETPCIE_NOC_ROUTER_2_5_5_REM_PGM_SETns_noc_io_pcie_soc_ip.csr156241PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_2_5_5_REM_MN_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MN_MSBPCIE_NOC_ROUTER_2_5_5_REM_MN_LSBPCIE_NOC_ROUTER_2_5_5_REM_MN_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MN_RESETPCIE_NOC_ROUTER_2_5_5_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MN_GETPCIE_NOC_ROUTER_2_5_5_REM_MN_SETns_noc_io_pcie_soc_ip.csr156252MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_2_5_5_REM_ME_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_ME_MSBPCIE_NOC_ROUTER_2_5_5_REM_ME_LSBPCIE_NOC_ROUTER_2_5_5_REM_ME_RANGEPCIE_NOC_ROUTER_2_5_5_REM_ME_RESETPCIE_NOC_ROUTER_2_5_5_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_ME_GETPCIE_NOC_ROUTER_2_5_5_REM_ME_SETns_noc_io_pcie_soc_ip.csr156263ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_2_5_5_REM_MW_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MW_MSBPCIE_NOC_ROUTER_2_5_5_REM_MW_LSBPCIE_NOC_ROUTER_2_5_5_REM_MW_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MW_RESETPCIE_NOC_ROUTER_2_5_5_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MW_GETPCIE_NOC_ROUTER_2_5_5_REM_MW_SETns_noc_io_pcie_soc_ip.csr156274MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_2_5_5_REM_MS_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MS_MSBPCIE_NOC_ROUTER_2_5_5_REM_MS_LSBPCIE_NOC_ROUTER_2_5_5_REM_MS_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MS_RESETPCIE_NOC_ROUTER_2_5_5_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MS_GETPCIE_NOC_ROUTER_2_5_5_REM_MS_SETns_noc_io_pcie_soc_ip.csr156285MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_2_5_5_REM_MH_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MH_MSBPCIE_NOC_ROUTER_2_5_5_REM_MH_LSBPCIE_NOC_ROUTER_2_5_5_REM_MH_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MH_RESETPCIE_NOC_ROUTER_2_5_5_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MH_GETPCIE_NOC_ROUTER_2_5_5_REM_MH_SETns_noc_io_pcie_soc_ip.csr156296MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_2_5_5_REM_MI_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MI_MSBPCIE_NOC_ROUTER_2_5_5_REM_MI_LSBPCIE_NOC_ROUTER_2_5_5_REM_MI_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MI_RESETPCIE_NOC_ROUTER_2_5_5_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MI_GETPCIE_NOC_ROUTER_2_5_5_REM_MI_SETns_noc_io_pcie_soc_ip.csr156307MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_2_5_5_REM_MJ_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MJ_MSBPCIE_NOC_ROUTER_2_5_5_REM_MJ_LSBPCIE_NOC_ROUTER_2_5_5_REM_MJ_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MJ_RESETPCIE_NOC_ROUTER_2_5_5_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MJ_GETPCIE_NOC_ROUTER_2_5_5_REM_MJ_SETns_noc_io_pcie_soc_ip.csr156318MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_2_5_5_REM_MK_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_MK_MSBPCIE_NOC_ROUTER_2_5_5_REM_MK_LSBPCIE_NOC_ROUTER_2_5_5_REM_MK_RANGEPCIE_NOC_ROUTER_2_5_5_REM_MK_RESETPCIE_NOC_ROUTER_2_5_5_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_MK_GETPCIE_NOC_ROUTER_2_5_5_REM_MK_SETns_noc_io_pcie_soc_ip.csr156329MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_2_5_5_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr156340UNSD_31_1431170x0000Rregisterpcie_noc.router_2_5_5_idrouter_2_5_5_idPCIE_NOC_ROUTER_2_5_5_ID_ADDRESSPCIE_NOC_ROUTER_2_5_5_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_ID_OFFSETPCIE_NOC_ROUTER_2_5_5_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr156410R2_5 register id0x500A0R0x010000a2Pcie_noc_router_2_5_5_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_2_5_5_ID_LAYER_WIDTHPCIE_NOC_ROUTER_2_5_5_ID_LAYER_MSBPCIE_NOC_ROUTER_2_5_5_ID_LAYER_LSBPCIE_NOC_ROUTER_2_5_5_ID_LAYER_RANGEPCIE_NOC_ROUTER_2_5_5_ID_LAYER_RESETPCIE_NOC_ROUTER_2_5_5_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_ID_LAYER_GETPCIE_NOC_ROUTER_2_5_5_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr156366LAYER5-bit identifier of the NoC layer on which this router is located400x02RPOSPCIE_NOC_ROUTER_2_5_5_ID_POS_WIDTHPCIE_NOC_ROUTER_2_5_5_ID_POS_MSBPCIE_NOC_ROUTER_2_5_5_ID_POS_LSBPCIE_NOC_ROUTER_2_5_5_ID_POS_RANGEPCIE_NOC_ROUTER_2_5_5_ID_POS_RESETPCIE_NOC_ROUTER_2_5_5_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_ID_POS_GETPCIE_NOC_ROUTER_2_5_5_ID_POS_SETns_noc_io_pcie_soc_ip.csr156377POS16-bit position ID of this router in the NoC2050x0005RZEROPCIE_NOC_ROUTER_2_5_5_ID_ZERO_WIDTHPCIE_NOC_ROUTER_2_5_5_ID_ZERO_MSBPCIE_NOC_ROUTER_2_5_5_ID_ZERO_LSBPCIE_NOC_ROUTER_2_5_5_ID_ZERO_RANGEPCIE_NOC_ROUTER_2_5_5_ID_ZERO_RESETPCIE_NOC_ROUTER_2_5_5_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_ID_ZERO_GETPCIE_NOC_ROUTER_2_5_5_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr156388ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_2_5_5_ID_ONE_WIDTHPCIE_NOC_ROUTER_2_5_5_ID_ONE_MSBPCIE_NOC_ROUTER_2_5_5_ID_ONE_LSBPCIE_NOC_ROUTER_2_5_5_ID_ONE_RANGEPCIE_NOC_ROUTER_2_5_5_ID_ONE_RESETPCIE_NOC_ROUTER_2_5_5_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_ID_ONE_GETPCIE_NOC_ROUTER_2_5_5_ID_ONE_SETns_noc_io_pcie_soc_ip.csr156399ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_2_5_5_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr156409UNSD_31_2531250x00Rregisterpcie_noc.router_2_5_5_rcgorouter_2_5_5_rcgoPCIE_NOC_ROUTER_2_5_5_RCGO_ADDRESSPCIE_NOC_ROUTER_2_5_5_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_RCGO_OFFSETPCIE_NOC_ROUTER_2_5_5_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr156449R2_5 register rcgo0x500B0R/W0x00000000Pcie_noc_router_2_5_5_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_MSBPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_LSBPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_RANGEPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_RESETPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_GETPCIE_NOC_ROUTER_2_5_5_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr156437FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_2_5_5_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr156448UNSD_31_13110x00000000Rregisterpcie_noc.router_2_5_5_p0_rperrrouter_2_5_5_p0_rperrPCIE_NOC_ROUTER_2_5_5_P0_RPERR_ADDRESSPCIE_NOC_ROUTER_2_5_5_P0_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_P0_RPERR_OFFSETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr156740R2_5 register p0_rperr0x500B8R/W0x00000000Pcie_noc_router_2_5_5_p0_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_SETns_noc_io_pcie_soc_ip.csr156492D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr156503SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr156514PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr156525RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr156536CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr156547UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr156558D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr156569SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr156581PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr156592RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr156604D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr156616SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr156629PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr156641RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr156653D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr156665SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr156678PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr156690RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr156702D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr156714SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr156727PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr156739RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_5_5_p1_rperrrouter_2_5_5_p1_rperrPCIE_NOC_ROUTER_2_5_5_P1_RPERR_ADDRESSPCIE_NOC_ROUTER_2_5_5_P1_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_P1_RPERR_OFFSETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr157031R2_5 register p1_rperr0x500C0R/W0x00000000Pcie_noc_router_2_5_5_p1_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_SETns_noc_io_pcie_soc_ip.csr156783D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr156794SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr156805PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr156816RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr156827CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr156838UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr156849D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr156860SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr156872PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr156883RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr156895D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr156907SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr156920PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr156932RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr156944D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr156956SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr156969PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr156981RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr156993D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr157005SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr157018PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr157030RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_5_5_p4_rperrrouter_2_5_5_p4_rperrPCIE_NOC_ROUTER_2_5_5_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_2_5_5_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_P4_RPERR_OFFSETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr157322R2_5 register p4_rperr0x500D8R/W0x00000000Pcie_noc_router_2_5_5_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr157074D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr157085SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr157096PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr157107RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr157118CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr157129UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr157140D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr157151SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr157163PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr157174RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr157186D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr157198SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr157211PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr157223RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr157235D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr157247SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr157260PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr157272RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr157284D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr157296SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr157309PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr157321RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_5_5_p0_rperrmrouter_2_5_5_p0_rperrmPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_OFFSETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr157580R2_5 register p0_rperrm0x500F8R/W0x00000000Pcie_noc_router_2_5_5_p0_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr157344DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr157355SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr157366PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr157377RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr157388CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr157399UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr157410D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr157421SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr157433PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr157444RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr157455D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr157466SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr157478PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr157489RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr157500D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr157511SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr157523PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr157534RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr157545D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr157556SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr157568PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_5_5_P0_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr157579RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_5_5_p1_rperrmrouter_2_5_5_p1_rperrmPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_OFFSETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr157838R2_5 register p1_rperrm0x50100R/W0x00000000Pcie_noc_router_2_5_5_p1_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr157602DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr157613SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr157624PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr157635RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr157646CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr157657UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr157668D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr157679SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr157691PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr157702RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr157713D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr157724SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr157736PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr157747RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr157758D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr157769SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr157781PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr157792RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr157803D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr157814SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr157826PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_5_5_P1_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr157837RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_5_5_p4_rperrmrouter_2_5_5_p4_rperrmPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr158096R2_5 register p4_rperrm0x50118R/W0x00000000Pcie_noc_router_2_5_5_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr157860DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr157871SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr157882PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr157893RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr157904CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr157915UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr157926D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr157937SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr157949PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr157960RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr157971D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr157982SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr157994PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr158005RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr158016D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr158027SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr158039PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr158050RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr158061D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr158072SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr158084PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_5_5_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr158095RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_7_7_rerouter_2_7_7_rePCIE_NOC_ROUTER_2_7_7_RE_ADDRESSPCIE_NOC_ROUTER_2_7_7_RE_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_RE_OFFSETPCIE_NOC_ROUTER_2_7_7_RE_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr158270R2_7 register re0x54080R/W0x00000000Pcie_noc_router_2_7_7_reThis register tracks the interrupt or error events that can occur in the router. The only interrupt event is the event counter overflow. This register is readable, and can be cleared by performing a write with the write data bits set to 0 for the bits that should be cleared.falsefalsefalsefalseOVFIPCIE_NOC_ROUTER_2_7_7_RE_OVFI_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_OVFI_MSBPCIE_NOC_ROUTER_2_7_7_RE_OVFI_LSBPCIE_NOC_ROUTER_2_7_7_RE_OVFI_RANGEPCIE_NOC_ROUTER_2_7_7_RE_OVFI_RESETPCIE_NOC_ROUTER_2_7_7_RE_OVFI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_OVFI_GETPCIE_NOC_ROUTER_2_7_7_RE_OVFI_SETns_noc_io_pcie_soc_ip.csr158122OVFI1'b1: In this status bit indicates that the router input event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear000x0R/WCSR_PARERRPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_MSBPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_LSBPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_RANGEPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_RESETPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_GETPCIE_NOC_ROUTER_2_7_7_RE_CSR_PARERR_SETns_noc_io_pcie_soc_ip.csr158133CSR_PARERR1'b1: Parity error in config/status registers110x0R/WOVFOPCIE_NOC_ROUTER_2_7_7_RE_OVFO_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_OVFO_MSBPCIE_NOC_ROUTER_2_7_7_RE_OVFO_LSBPCIE_NOC_ROUTER_2_7_7_RE_OVFO_RANGEPCIE_NOC_ROUTER_2_7_7_RE_OVFO_RESETPCIE_NOC_ROUTER_2_7_7_RE_OVFO_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_OVFO_GETPCIE_NOC_ROUTER_2_7_7_RE_OVFO_SETns_noc_io_pcie_soc_ip.csr158147OVFO1'b1: In this status bit indicates that the router output event counter has overflowed (32'hFFFFFFFF -> 32'dh0), this is a sticky status bit1'b0: To clear220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_GETPCIE_NOC_ROUTER_2_7_7_RE_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr158158UNSD_7_3730x00RPGEPCIE_NOC_ROUTER_2_7_7_RE_PGE_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_PGE_MSBPCIE_NOC_ROUTER_2_7_7_RE_PGE_LSBPCIE_NOC_ROUTER_2_7_7_RE_PGE_RANGEPCIE_NOC_ROUTER_2_7_7_RE_PGE_RESETPCIE_NOC_ROUTER_2_7_7_RE_PGE_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_PGE_GETPCIE_NOC_ROUTER_2_7_7_RE_PGE_SETns_noc_io_pcie_soc_ip.csr158170PGE1'b1: Power gating error, traffic received after router commited to power down880x0R/WNLUPCIE_NOC_ROUTER_2_7_7_RE_NLU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_NLU_MSBPCIE_NOC_ROUTER_2_7_7_RE_NLU_LSBPCIE_NOC_ROUTER_2_7_7_RE_NLU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_NLU_RESETPCIE_NOC_ROUTER_2_7_7_RE_NLU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_NLU_GETPCIE_NOC_ROUTER_2_7_7_RE_NLU_SETns_noc_io_pcie_soc_ip.csr158181NLU1'b1: Traffic destined for North link which is unavailable990x0R/WELUPCIE_NOC_ROUTER_2_7_7_RE_ELU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_ELU_MSBPCIE_NOC_ROUTER_2_7_7_RE_ELU_LSBPCIE_NOC_ROUTER_2_7_7_RE_ELU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_ELU_RESETPCIE_NOC_ROUTER_2_7_7_RE_ELU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_ELU_GETPCIE_NOC_ROUTER_2_7_7_RE_ELU_SETns_noc_io_pcie_soc_ip.csr158192ELU1'b1: Traffic destined for East link which is unavailable10100x0R/WWLUPCIE_NOC_ROUTER_2_7_7_RE_WLU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_WLU_MSBPCIE_NOC_ROUTER_2_7_7_RE_WLU_LSBPCIE_NOC_ROUTER_2_7_7_RE_WLU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_WLU_RESETPCIE_NOC_ROUTER_2_7_7_RE_WLU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_WLU_GETPCIE_NOC_ROUTER_2_7_7_RE_WLU_SETns_noc_io_pcie_soc_ip.csr158203WLU1'b1: Traffic destined for West link which is unavailable11110x0R/WSLUPCIE_NOC_ROUTER_2_7_7_RE_SLU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_SLU_MSBPCIE_NOC_ROUTER_2_7_7_RE_SLU_LSBPCIE_NOC_ROUTER_2_7_7_RE_SLU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_SLU_RESETPCIE_NOC_ROUTER_2_7_7_RE_SLU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_SLU_GETPCIE_NOC_ROUTER_2_7_7_RE_SLU_SETns_noc_io_pcie_soc_ip.csr158214SLU1'b1: Traffic destined for South link which is unavailable12120x0R/WHLUPCIE_NOC_ROUTER_2_7_7_RE_HLU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_HLU_MSBPCIE_NOC_ROUTER_2_7_7_RE_HLU_LSBPCIE_NOC_ROUTER_2_7_7_RE_HLU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_HLU_RESETPCIE_NOC_ROUTER_2_7_7_RE_HLU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_HLU_GETPCIE_NOC_ROUTER_2_7_7_RE_HLU_SETns_noc_io_pcie_soc_ip.csr158225HLU1'b1: Traffic destined for H link which is unavailable13130x0R/WILUPCIE_NOC_ROUTER_2_7_7_RE_ILU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_ILU_MSBPCIE_NOC_ROUTER_2_7_7_RE_ILU_LSBPCIE_NOC_ROUTER_2_7_7_RE_ILU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_ILU_RESETPCIE_NOC_ROUTER_2_7_7_RE_ILU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_ILU_GETPCIE_NOC_ROUTER_2_7_7_RE_ILU_SETns_noc_io_pcie_soc_ip.csr158236ILU1'b1: Traffic destined for I link which is unavailable14140x0R/WJLUPCIE_NOC_ROUTER_2_7_7_RE_JLU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_JLU_MSBPCIE_NOC_ROUTER_2_7_7_RE_JLU_LSBPCIE_NOC_ROUTER_2_7_7_RE_JLU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_JLU_RESETPCIE_NOC_ROUTER_2_7_7_RE_JLU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_JLU_GETPCIE_NOC_ROUTER_2_7_7_RE_JLU_SETns_noc_io_pcie_soc_ip.csr158247JLU1'b1: Traffic destined for J link which is unavailable15150x0R/WKLUPCIE_NOC_ROUTER_2_7_7_RE_KLU_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_KLU_MSBPCIE_NOC_ROUTER_2_7_7_RE_KLU_LSBPCIE_NOC_ROUTER_2_7_7_RE_KLU_RANGEPCIE_NOC_ROUTER_2_7_7_RE_KLU_RESETPCIE_NOC_ROUTER_2_7_7_RE_KLU_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_KLU_GETPCIE_NOC_ROUTER_2_7_7_RE_KLU_SETns_noc_io_pcie_soc_ip.csr158258KLU1'b1: Traffic destined for K link which is unavailable16160x0R/WUNSD_31_14PCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_GETPCIE_NOC_ROUTER_2_7_7_RE_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr158269UNSD_31_1431170x0000Rregisterpcie_noc.router_2_7_7_remrouter_2_7_7_remPCIE_NOC_ROUTER_2_7_7_REM_ADDRESSPCIE_NOC_ROUTER_2_7_7_REM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_REM_OFFSETPCIE_NOC_ROUTER_2_7_7_REM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr158443R2_7 register rem0x54088R/W0x0001fe00Pcie_noc_router_2_7_7_remThis register is used to select whether the interrupt events in the Router Event Interrupt Status register should send an interrupt when asserted. If the corresponding bit is set to 1, an interrupt will not be sent. This register can be read and written to.falsefalsefalsefalseOVFIMPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_MSBPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_LSBPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_RANGEPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_RESETPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_GETPCIE_NOC_ROUTER_2_7_7_REM_OVFIM_SETns_noc_io_pcie_soc_ip.csr158296OVFIM1'b1: Masks or disables an interrupt from being generated by the input event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set000x0R/WCSR_PARERRMPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_MSBPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_LSBPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_RANGEPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_RESETPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_GETPCIE_NOC_ROUTER_2_7_7_REM_CSR_PARERRM_SETns_noc_io_pcie_soc_ip.csr158307CSR_PARERRM1'b1: Mask CSR parity error interrupt110x0R/WOVFOMPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_MSBPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_LSBPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_RANGEPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_RESETPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_GETPCIE_NOC_ROUTER_2_7_7_REM_OVFOM_SETns_noc_io_pcie_soc_ip.csr158321OVFOM1'b1: Masks or disables an interrupt from being generated by the output event count overflow status bit (RE)1'b0: Enables an interrupt to be generated when event counter status bit is set220x0R/WUNSD_7_3PCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_MSBPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_LSBPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_RANGEPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_RESETPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_GETPCIE_NOC_ROUTER_2_7_7_REM_UNSD_7_3_SETns_noc_io_pcie_soc_ip.csr158332UNSD_7_3730x00RPGMPCIE_NOC_ROUTER_2_7_7_REM_PGM_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_PGM_MSBPCIE_NOC_ROUTER_2_7_7_REM_PGM_LSBPCIE_NOC_ROUTER_2_7_7_REM_PGM_RANGEPCIE_NOC_ROUTER_2_7_7_REM_PGM_RESETPCIE_NOC_ROUTER_2_7_7_REM_PGM_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_PGM_GETPCIE_NOC_ROUTER_2_7_7_REM_PGM_SETns_noc_io_pcie_soc_ip.csr158343PGM1'b1: Mask PGE error interrupt880x0R/WMNPCIE_NOC_ROUTER_2_7_7_REM_MN_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MN_MSBPCIE_NOC_ROUTER_2_7_7_REM_MN_LSBPCIE_NOC_ROUTER_2_7_7_REM_MN_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MN_RESETPCIE_NOC_ROUTER_2_7_7_REM_MN_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MN_GETPCIE_NOC_ROUTER_2_7_7_REM_MN_SETns_noc_io_pcie_soc_ip.csr158354MN1'b1: Mask NLU error interrupt990x1R/WMEPCIE_NOC_ROUTER_2_7_7_REM_ME_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_ME_MSBPCIE_NOC_ROUTER_2_7_7_REM_ME_LSBPCIE_NOC_ROUTER_2_7_7_REM_ME_RANGEPCIE_NOC_ROUTER_2_7_7_REM_ME_RESETPCIE_NOC_ROUTER_2_7_7_REM_ME_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_ME_GETPCIE_NOC_ROUTER_2_7_7_REM_ME_SETns_noc_io_pcie_soc_ip.csr158365ME1'b1: Mask ELU error interrupt10100x1R/WMWPCIE_NOC_ROUTER_2_7_7_REM_MW_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MW_MSBPCIE_NOC_ROUTER_2_7_7_REM_MW_LSBPCIE_NOC_ROUTER_2_7_7_REM_MW_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MW_RESETPCIE_NOC_ROUTER_2_7_7_REM_MW_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MW_GETPCIE_NOC_ROUTER_2_7_7_REM_MW_SETns_noc_io_pcie_soc_ip.csr158376MW1'b1: Mask WLU error interrupt11110x1R/WMSPCIE_NOC_ROUTER_2_7_7_REM_MS_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MS_MSBPCIE_NOC_ROUTER_2_7_7_REM_MS_LSBPCIE_NOC_ROUTER_2_7_7_REM_MS_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MS_RESETPCIE_NOC_ROUTER_2_7_7_REM_MS_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MS_GETPCIE_NOC_ROUTER_2_7_7_REM_MS_SETns_noc_io_pcie_soc_ip.csr158387MS1'b1: Mask SLU error interrupt12120x1R/WMHPCIE_NOC_ROUTER_2_7_7_REM_MH_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MH_MSBPCIE_NOC_ROUTER_2_7_7_REM_MH_LSBPCIE_NOC_ROUTER_2_7_7_REM_MH_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MH_RESETPCIE_NOC_ROUTER_2_7_7_REM_MH_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MH_GETPCIE_NOC_ROUTER_2_7_7_REM_MH_SETns_noc_io_pcie_soc_ip.csr158398MH1'b1: Mask HLU error interrupt13130x1R/WMIPCIE_NOC_ROUTER_2_7_7_REM_MI_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MI_MSBPCIE_NOC_ROUTER_2_7_7_REM_MI_LSBPCIE_NOC_ROUTER_2_7_7_REM_MI_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MI_RESETPCIE_NOC_ROUTER_2_7_7_REM_MI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MI_GETPCIE_NOC_ROUTER_2_7_7_REM_MI_SETns_noc_io_pcie_soc_ip.csr158409MI1'b1: Mask ILU error interrupt14140x1R/WMJPCIE_NOC_ROUTER_2_7_7_REM_MJ_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MJ_MSBPCIE_NOC_ROUTER_2_7_7_REM_MJ_LSBPCIE_NOC_ROUTER_2_7_7_REM_MJ_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MJ_RESETPCIE_NOC_ROUTER_2_7_7_REM_MJ_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MJ_GETPCIE_NOC_ROUTER_2_7_7_REM_MJ_SETns_noc_io_pcie_soc_ip.csr158420MJ1'b1: Mask JLU error interrupt15150x1R/WMKPCIE_NOC_ROUTER_2_7_7_REM_MK_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_MK_MSBPCIE_NOC_ROUTER_2_7_7_REM_MK_LSBPCIE_NOC_ROUTER_2_7_7_REM_MK_RANGEPCIE_NOC_ROUTER_2_7_7_REM_MK_RESETPCIE_NOC_ROUTER_2_7_7_REM_MK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_MK_GETPCIE_NOC_ROUTER_2_7_7_REM_MK_SETns_noc_io_pcie_soc_ip.csr158431MK1'b1: Mask KLU error interrupt16160x1R/WUNSD_31_14PCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_WIDTHPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_MSBPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_LSBPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_RANGEPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_RESETPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_GETPCIE_NOC_ROUTER_2_7_7_REM_UNSD_31_14_SETns_noc_io_pcie_soc_ip.csr158442UNSD_31_1431170x0000Rregisterpcie_noc.router_2_7_7_idrouter_2_7_7_idPCIE_NOC_ROUTER_2_7_7_ID_ADDRESSPCIE_NOC_ROUTER_2_7_7_ID_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_ID_OFFSETPCIE_NOC_ROUTER_2_7_7_ID_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr158512R2_7 register id0x540A0R0x010000e2Pcie_noc_router_2_7_7_idThis register holds layer and position information for the router. It is a read-only register. It can be used for debugging software access to the NoC elements by confirming that a read has successfully targeted the correct NoC element.falsefalsefalsefalseLAYERPCIE_NOC_ROUTER_2_7_7_ID_LAYER_WIDTHPCIE_NOC_ROUTER_2_7_7_ID_LAYER_MSBPCIE_NOC_ROUTER_2_7_7_ID_LAYER_LSBPCIE_NOC_ROUTER_2_7_7_ID_LAYER_RANGEPCIE_NOC_ROUTER_2_7_7_ID_LAYER_RESETPCIE_NOC_ROUTER_2_7_7_ID_LAYER_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_ID_LAYER_GETPCIE_NOC_ROUTER_2_7_7_ID_LAYER_SETns_noc_io_pcie_soc_ip.csr158468LAYER5-bit identifier of the NoC layer on which this router is located400x02RPOSPCIE_NOC_ROUTER_2_7_7_ID_POS_WIDTHPCIE_NOC_ROUTER_2_7_7_ID_POS_MSBPCIE_NOC_ROUTER_2_7_7_ID_POS_LSBPCIE_NOC_ROUTER_2_7_7_ID_POS_RANGEPCIE_NOC_ROUTER_2_7_7_ID_POS_RESETPCIE_NOC_ROUTER_2_7_7_ID_POS_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_ID_POS_GETPCIE_NOC_ROUTER_2_7_7_ID_POS_SETns_noc_io_pcie_soc_ip.csr158479POS16-bit position ID of this router in the NoC2050x0007RZEROPCIE_NOC_ROUTER_2_7_7_ID_ZERO_WIDTHPCIE_NOC_ROUTER_2_7_7_ID_ZERO_MSBPCIE_NOC_ROUTER_2_7_7_ID_ZERO_LSBPCIE_NOC_ROUTER_2_7_7_ID_ZERO_RANGEPCIE_NOC_ROUTER_2_7_7_ID_ZERO_RESETPCIE_NOC_ROUTER_2_7_7_ID_ZERO_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_ID_ZERO_GETPCIE_NOC_ROUTER_2_7_7_ID_ZERO_SETns_noc_io_pcie_soc_ip.csr158490ZEROZeroes23210x0RONEPCIE_NOC_ROUTER_2_7_7_ID_ONE_WIDTHPCIE_NOC_ROUTER_2_7_7_ID_ONE_MSBPCIE_NOC_ROUTER_2_7_7_ID_ONE_LSBPCIE_NOC_ROUTER_2_7_7_ID_ONE_RANGEPCIE_NOC_ROUTER_2_7_7_ID_ONE_RESETPCIE_NOC_ROUTER_2_7_7_ID_ONE_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_ID_ONE_GETPCIE_NOC_ROUTER_2_7_7_ID_ONE_SETns_noc_io_pcie_soc_ip.csr158501ONEOne24240x1RUNSD_31_25PCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_WIDTHPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_MSBPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_LSBPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_RANGEPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_RESETPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_GETPCIE_NOC_ROUTER_2_7_7_ID_UNSD_31_25_SETns_noc_io_pcie_soc_ip.csr158511UNSD_31_2531250x00Rregisterpcie_noc.router_2_7_7_rcgorouter_2_7_7_rcgoPCIE_NOC_ROUTER_2_7_7_RCGO_ADDRESSPCIE_NOC_ROUTER_2_7_7_RCGO_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_RCGO_OFFSETPCIE_NOC_ROUTER_2_7_7_RCGO_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr158551R2_7 register rcgo0x540B0R/W0x00000000Pcie_noc_router_2_7_7_rcgoThis register is used by coarse grained clock gating logic. This register can be set to override coarse clock gating for the entire router. Coarse clock gating for selective routers can be overridden by locally setting this register, if the user does not want incur and aggregate coarse clock gating cycle penalty over a "fast path/critical path" through the NoC.falsefalsefalsefalseFPOPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_WIDTHPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_MSBPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_LSBPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_RANGEPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_RESETPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_GETPCIE_NOC_ROUTER_2_7_7_RCGO_FPO_SETns_noc_io_pcie_soc_ip.csr158539FPO1'b1: Coarse clock gating is locally disabled (for fast path)1'b0: Coarse clock gating is locally enabled000x0R/WUNSD_31_1PCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_WIDTHPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_MSBPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_LSBPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_RANGEPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_RESETPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_GETPCIE_NOC_ROUTER_2_7_7_RCGO_UNSD_31_1_SETns_noc_io_pcie_soc_ip.csr158550UNSD_31_13110x00000000Rregisterpcie_noc.router_2_7_7_p0_rperrrouter_2_7_7_p0_rperrPCIE_NOC_ROUTER_2_7_7_P0_RPERR_ADDRESSPCIE_NOC_ROUTER_2_7_7_P0_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_P0_RPERR_OFFSETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr158842R2_7 register p0_rperr0x540B8R/W0x00000000Pcie_noc_router_2_7_7_p0_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_SETns_noc_io_pcie_soc_ip.csr158594D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr158605SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr158616PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr158627RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr158638CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr158649UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr158660D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr158671SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr158683PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr158694RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr158706D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr158718SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr158731PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr158743RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr158755D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr158767SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr158780PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr158792RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr158804D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr158816SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr158829PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr158841RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_7_7_p3_rperrrouter_2_7_7_p3_rperrPCIE_NOC_ROUTER_2_7_7_P3_RPERR_ADDRESSPCIE_NOC_ROUTER_2_7_7_P3_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_P3_RPERR_OFFSETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr159133R2_7 register p3_rperr0x540D0R/W0x00000000Pcie_noc_router_2_7_7_p3_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_SETns_noc_io_pcie_soc_ip.csr158885D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr158896SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr158907PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr158918RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr158929CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr158940UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr158951D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr158962SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr158974PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr158985RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr158997D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr159009SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr159022PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr159034RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr159046D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr159058SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr159071PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr159083RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr159095D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr159107SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr159120PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr159132RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_7_7_p4_rperrrouter_2_7_7_p4_rperrPCIE_NOC_ROUTER_2_7_7_P4_RPERR_ADDRESSPCIE_NOC_ROUTER_2_7_7_P4_RPERR_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_P4_RPERR_OFFSETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr159424R2_7 register p4_rperr0x540D8R/W0x00000000Pcie_noc_router_2_7_7_p4_rperrThere is one register for each router port capturing parity error events occurring on the port. Parity errors are monitored on router physical link and also on data read from VC buffers of the router. Error status bits are sticky. First detected error while the status bit is in cleared state sets the bit. The bit needs to be explicitly cleared using zero write, before another error can be logged for that status bit. Following fields of information transported over the NoC are monitored for error at router ports. [FATAL] all bits in this register are classified as fatal for interrupt purpose.- Data Parity: Parity is checked over multiple segments of data in each flit. Parity error in any segment will be recorded in the data parity status bit. Note that parity is checked on data only if parity mode error check is enabled on the router's layer. In ECC mode, data parity is not monitored on each router.- User sideband parity: Similar to data field above.- Packet control parity: Parity over start of packet, end of packet, byte valid and data valid fields of a flit.- Routing information parity: Parity over routing information carried in every flit.- Credit parity: Parity monitored over credits returned downstream port.falsefalsefalsefalseDPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_SETns_noc_io_pcie_soc_ip.csr159176D1'b1: Parity Error in Link Data000x0R/WSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_SETns_noc_io_pcie_soc_ip.csr159187SB1'b1: Parity Error in Link User Sideband110x0R/WPKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_SETns_noc_io_pcie_soc_ip.csr159198PK1'b1: Parity Error in Link Packet Delineation Controls220x0R/WRIPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_SETns_noc_io_pcie_soc_ip.csr159209RI1'b1: Parity Error in Link Routing Information330x0R/WCRPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_CR_SETns_noc_io_pcie_soc_ip.csr159220CR1'b1: Parity Error in Link Credit From Downstream Router440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr159231UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_0_SETns_noc_io_pcie_soc_ip.csr159242D_01'b1: Parity Error in VC 0 Buffer Data16160x0R/WSB_0PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_0_SETns_noc_io_pcie_soc_ip.csr159253SB_01'b1: Parity Error in VC 0 Buffer User Sideband17170x0R/WPK_0PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_0_SETns_noc_io_pcie_soc_ip.csr159265PK_01'b1: Parity Error in VC 0 Buffer Packet Delineation Controls18180x0R/WRI_0PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_0_SETns_noc_io_pcie_soc_ip.csr159276RI_01'b1: Parity Error in VC 0 Buffer Routing Information19190x0R/WD_1PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_1_SETns_noc_io_pcie_soc_ip.csr159288D_11'b1: Parity Error in VC 1 Buffer Data20200x0RSB_1PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_1_SETns_noc_io_pcie_soc_ip.csr159300SB_11'b1: Parity Error in VC 1 Buffer User Sideband21210x0RPK_1PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_1_SETns_noc_io_pcie_soc_ip.csr159313PK_11'b1: Parity Error in VC 1 Buffer Packet Delineation Controls22220x0RRI_1PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_1_SETns_noc_io_pcie_soc_ip.csr159325RI_11'b1: Parity Error in VC 1 Buffer Routing Information23230x0RD_2PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_2_SETns_noc_io_pcie_soc_ip.csr159337D_21'b1: Parity Error in VC 2 Buffer Data24240x0RSB_2PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_2_SETns_noc_io_pcie_soc_ip.csr159349SB_21'b1: Parity Error in VC 2 Buffer User Sideband25250x0RPK_2PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_2_SETns_noc_io_pcie_soc_ip.csr159362PK_21'b1: Parity Error in VC 2 Buffer Packet Delineation Controls26260x0RRI_2PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_2_SETns_noc_io_pcie_soc_ip.csr159374RI_21'b1: Parity Error in VC 2 Buffer Routing Information27270x0RD_3PCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_D_3_SETns_noc_io_pcie_soc_ip.csr159386D_31'b1: Parity Error in VC 3 Buffer Data28280x0RSB_3PCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_SB_3_SETns_noc_io_pcie_soc_ip.csr159398SB_31'b1: Parity Error in VC 3 Buffer User Sideband29290x0RPK_3PCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_PK_3_SETns_noc_io_pcie_soc_ip.csr159411PK_31'b1: Parity Error in VC 3 Buffer Packet Delineation Controls30300x0RRI_3PCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERR_RI_3_SETns_noc_io_pcie_soc_ip.csr159423RI_31'b1: Parity Error in VC 3 Buffer Routing Information31310x0Rregisterpcie_noc.router_2_7_7_p0_rperrmrouter_2_7_7_p0_rperrmPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_OFFSETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr159682R2_7 register p0_rperrm0x540F8R/W0x00000000Pcie_noc_router_2_7_7_p0_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr159446DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr159457SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr159468PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr159479RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr159490CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr159501UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr159512D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr159523SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr159535PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr159546RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr159557D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr159568SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr159580PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr159591RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr159602D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr159613SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr159625PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr159636RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr159647D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr159658SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr159670PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_7_7_P0_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr159681RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_7_7_p3_rperrmrouter_2_7_7_p3_rperrmPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_OFFSETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr159940R2_7 register p3_rperrm0x54110R/W0x00000000Pcie_noc_router_2_7_7_p3_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr159704DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr159715SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr159726PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr159737RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr159748CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr159759UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr159770D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr159781SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr159793PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr159804RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr159815D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr159826SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr159838PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr159849RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr159860D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr159871SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr159883PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr159894RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr159905D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr159916SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr159928PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_7_7_P3_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr159939RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/Wregisterpcie_noc.router_2_7_7_p4_rperrmrouter_2_7_7_p4_rperrmPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_ADDRESSPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_BYTE_ADDRESSPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_OFFSETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_BYTE_OFFSETns_noc_io_pcie_soc_ip.csr160198R2_7 register p4_rperrm0x54118R/W0x00000000Pcie_noc_router_2_7_7_p4_rperrmOne mask register bit for each parity status bit in RPERR. When mask bit is set, corresponding parity error does not cause an interrupt. Default state is reset for all mask bits, allowing interrupt on any parity error eventfalsefalsefalsefalseDPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_SETns_noc_io_pcie_soc_ip.csr159962DMaskParity Error in Link Data.000x0R/WSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_SETns_noc_io_pcie_soc_ip.csr159973SBMask Parity Error in Link User Sideband.110x0R/WPKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_SETns_noc_io_pcie_soc_ip.csr159984PKMask Parity Error in Link Packet Delineation Controls.220x0R/WRIPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_SETns_noc_io_pcie_soc_ip.csr159995RIMask Parity Error in Link Routing Information.330x0R/WCRPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_CR_SETns_noc_io_pcie_soc_ip.csr160006CRMask Parity Error in Link Credit From Downstream Router.440x0R/WUNSD_15_5PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_UNSD_15_5_SETns_noc_io_pcie_soc_ip.csr160017UNSD_15_51550x000RD_0PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_0_SETns_noc_io_pcie_soc_ip.csr160028D_0Mask Parity Error in VC 0 Buffer Data.16160x0R/WSB_0PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_0_SETns_noc_io_pcie_soc_ip.csr160039SB_0Mask Parity Error in VC 0 Buffer User Sideband.17170x0R/WPK_0PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_0_SETns_noc_io_pcie_soc_ip.csr160051PK_0Mask Parity Error in VC 0 Buffer Packet Delineation Controls.18180x0R/WRI_0PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_0_SETns_noc_io_pcie_soc_ip.csr160062RI_0Mask Parity Error in VC 0 Buffer Routing Information.19190x0R/WD_1PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_1_SETns_noc_io_pcie_soc_ip.csr160073D_1Mask Parity Error in VC 1 Buffer Data.20200x0R/WSB_1PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_1_SETns_noc_io_pcie_soc_ip.csr160084SB_1Mask Parity Error in VC 1 Buffer User Sideband.21210x0R/WPK_1PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_1_SETns_noc_io_pcie_soc_ip.csr160096PK_1Mask Parity Error in VC 1 Buffer Packet Delineation Controls.22220x0R/WRI_1PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_1_SETns_noc_io_pcie_soc_ip.csr160107RI_1Mask Parity Error in VC 1 Buffer Routing Information.23230x0R/WD_2PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_2_SETns_noc_io_pcie_soc_ip.csr160118D_2Mask Parity Error in VC 2 Buffer Data.24240x0R/WSB_2PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_2_SETns_noc_io_pcie_soc_ip.csr160129SB_2Mask Parity Error in VC 2 Buffer User Sideband.25250x0R/WPK_2PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_2_SETns_noc_io_pcie_soc_ip.csr160141PK_2Mask Parity Error in VC 2 Buffer Packet Delineation Controls.26260x0R/WRI_2PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_2_SETns_noc_io_pcie_soc_ip.csr160152RI_2Mask Parity Error in VC 2 Buffer Routing Information.27270x0R/WD_3PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_D_3_SETns_noc_io_pcie_soc_ip.csr160163D_3Mask Parity Error in VC 3 Buffer Data.28280x0R/WSB_3PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_SB_3_SETns_noc_io_pcie_soc_ip.csr160174SB_3Mask Parity Error in VC 3 Buffer User Sideband.29290x0R/WPK_3PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_PK_3_SETns_noc_io_pcie_soc_ip.csr160186PK_3Mask Parity Error in VC 3 Buffer Packet Delineation Controls.30300x0R/WRI_3PCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_WIDTHPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_MSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_LSBPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_RANGEPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_RESETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_FIELD_MASKPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_GETPCIE_NOC_ROUTER_2_7_7_P4_RPERRM_RI_3_SETns_noc_io_pcie_soc_ip.csr160197RI_3Mask Parity Error in VC 3 Buffer Routing Information.31310x0R/W
Addressmap Information for 'ns_noc_io_pcie_soc_ip'